diff --git a/reset_set.sv b/reset_set.sv index 2da07a8..e23eadd 100644 --- a/reset_set.sv +++ b/reset_set.sv @@ -4,8 +4,8 @@ //-------------------------------------------------------------------------------- // INFO -------------------------------------------------------------------------------- -// SR trigger variant -// No metastable state. SET dominates here +// Synchronous SR trigger variant +// No metastable state. SET signal dominates here /* --- INSTANTIATION TEMPLATE BEGIN --- @@ -32,11 +32,11 @@ module reset_set( ); always_ff @(posedge clk) begin - if (~nrst) begin + if( ~nrst ) begin q = 0; end else begin - if r q = 0; - if s q = 1; + if( r ) q = 1'b0; + if( s ) q = 1'b1; end end diff --git a/reset_set_comb.sv b/reset_set_comb.sv new file mode 100644 index 0000000..efb25f9 --- /dev/null +++ b/reset_set_comb.sv @@ -0,0 +1,67 @@ +//-------------------------------------------------------------------------------- +// reset_set_comb.sv +// Konstantin Pavlov, pavlovconst@gmail.com +//-------------------------------------------------------------------------------- + +// INFO -------------------------------------------------------------------------------- +// Synchronous SR trigger, but has a combinational output that changes +// "with no delay" after inputs +// No metastable state. SET signal dominates here + + +// | | +---+ | | | | | | SET +// | | | | | | | | | | +// +------------+ +--------------------------------+ +// | | | | | | | | | | +// | | | | | | +---+ | | RESET +// | | | | | | | | | | +// +----------------------------+ +----------------+ +// | | | | | | | | | | +// | | | +---------------+ | | Q output, original +// | | | | | | | | | | reset_set.sv +// +----------------+ | | | +----------------+ +// | | | | | | | | | | +// | | +---------------+ | | | Q output, this module +// | | | | | | | | | | reset_set_comb.sv +// +------------+ | | | +--------------------+ +// | | | | | | | | | | +// | | | | | | | | | | + + +/* --- INSTANTIATION TEMPLATE BEGIN --- + +reset_set_comb RS1 ( + .clk( clk ), + .nrst( 1'b1 ), + .s( ), + .r( ), + .q( ), + .nq( ) +); + +--- INSTANTIATION TEMPLATE END ---*/ + + +module reset_set_comb( + input clk, + input nrst, + input s, + input r, + output q, + output nq +); + +logic q_reg = 0; +always_ff @(posedge clk) begin + if( ~nrst ) begin + q_reg = 0; + end else begin + if( r ) q_reg = 1'b0; + if( s ) q_reg = 1'b1; + end +end + +assign q = s || (q_reg && ~r); +assign nq = ~q; + +endmodule \ No newline at end of file diff --git a/set_reset.sv b/set_reset.sv index db19305..317f5a5 100644 --- a/set_reset.sv +++ b/set_reset.sv @@ -4,8 +4,8 @@ //-------------------------------------------------------------------------------- // INFO -------------------------------------------------------------------------------- -// SR trigger variant -// No metastable state. RESET dominates here +// Synchronous SR trigger variant +// No metastable state. RESET signal dominates here /* --- INSTANTIATION TEMPLATE BEGIN --- @@ -32,11 +32,11 @@ module set_reset( ); always_ff @(posedge clk) begin - if (~nrst) begin + if( ~nrst ) begin q = 0; end else begin - if s q = 1; - if r q = 0; + if( s ) q = 1'b1; + if( r ) q = 1'b0; end end diff --git a/set_reset_comb.sv b/set_reset_comb.sv new file mode 100644 index 0000000..b9d122e --- /dev/null +++ b/set_reset_comb.sv @@ -0,0 +1,67 @@ +//-------------------------------------------------------------------------------- +// set_reset_comb.sv +// Konstantin Pavlov, pavlovconst@gmail.com +//-------------------------------------------------------------------------------- + +// INFO -------------------------------------------------------------------------------- +// Synchronous SR trigger, but has a combinational output that changes +// "with no delay" after inputs +// No metastable state. RESET signal dominates here + + +// | | +---+ | | | | | | SET +// | | | | | | | | | | +// +------------+ +--------------------------------+ +// | | | | | | | | | | +// | | | | | | +---+ | | RESET +// | | | | | | | | | | +// +----------------------------+ +----------------+ +// | | | | | | | | | | +// | | | +---------------+ | | Q output, original +// | | | | | | | | | | set_reset.sv +// +----------------+ | | | +----------------+ +// | | | | | | | | | | +// | | +---------------+ | | | Q output, this module +// | | | | | | | | | | set_reset_comb.sv +// +------------+ | | | +--------------------+ +// | | | | | | | | | | +// | | | | | | | | | | + + +/* --- INSTANTIATION TEMPLATE BEGIN --- + +set_reset_comb SR1 ( + .clk( clk ), + .nrst( 1'b1 ), + .s( ), + .r( ), + .q( ), + .nq( ) +); + +--- INSTANTIATION TEMPLATE END ---*/ + + +module set_reset_comb( + input clk, + input nrst, + input s, + input r, + output q, + output nq +); + +logic q_reg = 0; +always_ff @(posedge clk) begin + if( ~nrst ) begin + q_reg = 0; + end else begin + if( s ) q_reg = 1'b1; + if( r ) q_reg = 1'b0; + end +end + +assign q = (s || q_reg) && ~r; +assign nq = ~q; + +endmodule \ No newline at end of file