mirror of
https://github.com/pConst/basic_verilog.git
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Added Intel HLS scripts and boilerplate
This commit is contained in:
Konstantin Pavlov
parent
6c5ef366e7
commit
2499f3a2ea
198
scripts_for_intel_hls/b.bat
Executable file
198
scripts_for_intel_hls/b.bat
Executable file
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@echo off
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rem ----------------------------------------------------------------------------
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rem b.bat
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rem build script for Intel High Level Synthesis projects for Windows
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rem Konstantin Pavlov, pavlovconst@gmail.com
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rem ----------------------------------------------------------------------------
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setlocal enabledelayedexpansion
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set "COMPONENT=test"
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set "FPGA_SERIES=CycloneV"
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set "FPGA_CLOCK=100MHz"
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set "SOURCE_FILES=test.cpp"
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set "HLS_CXX_FLAGS=-v --debug-log"
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for /f "tokens=2-4 delims=/ " %%a in ('date /t') do (set Z_DATE=%%c-%%a-%%b)
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for /f "tokens=1-2 delims=/:" %%a in ('time /t') do (set Z_TIME=%%a-%%b)
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echo DBG: start timestamp is %Z_DATE%_%Z_TIME%
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set "Z_PATH="C:\Program Files\7-Zip\7z.exe""
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echo DBG: 7z.exe path is %Z_PATH%
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:: Accept the user's target, else default to e[mulation]
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if not "%1"=="" (
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set "TARGET=%1"
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) else (
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set "TARGET=e"
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echo No target specified, defaulting to !TARGET!
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echo Available targets: e[mulation], s[imulation], m[svc], c[lean], r[eport], v[sim], q[uartus]
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)
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echo DBG: target is !TARGET!
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:: Any tools installed with HLS can be found relative to the location of i++
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for %%I in (i++.exe) do (
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set "HLS_INSTALL_DIR=%%~dp$PATH:I"
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)
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set "HLS_INSTALL_DIR=%HLS_INSTALL_DIR%.."
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echo DBG: HLS_INSTALL_DIR is %HLS_INSTALL_DIR%
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set "TARGET_INIT=!TARGET!"
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:: Set up the compile variables
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if "!TARGET!" == "e" (
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:: Dont gesitate that FPGA_FAMILY is shown as Arria 10 here.
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:: This is just an emulation anyway
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call :clean_e_subroutine
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set "CXX=i++"
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set "CXXFLAGS=%HLS_CXX_FLAGS% -march=x86-64"
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set "LFLAGS=-o !TARGET!.exe"
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)
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if "!TARGET!" == "s" (
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call :clean_s_subroutine
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set "CXX=i++"
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set "CXXFLAGS=%HLS_CXX_FLAGS% --clock %FPGA_CLOCK% -ghdl -march=%FPGA_SERIES%
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set "LFLAGS=-o !TARGET!.exe"
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)
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if "!TARGET!" == "q" (
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::Dont make special project folder for Quartus
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set "INIT_TARGET=q"
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set "TARGET=s"
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echo DBG: target is !TARGET!
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call :clean_s_subroutine
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set "CXX=i++"
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set "CXXFLAGS=%HLS_CXX_FLAGS% --clock %FPGA_CLOCK% --quartus-compile -ghdl -march=%FPGA_SERIES%
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set "LFLAGS=-o !TARGET!.exe"
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)
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if "!TARGET!" == "m" (
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::Dont make special project folder for VC
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set "TARGET=s"
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echo DBG: target is !TARGET!
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call :clean_s_subroutine
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set "CXX=cl"
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set "CXXFLAGS=/I ""%HLS_INSTALL_DIR%\include"" /nologo /EHsc /wd4068 /DWIN32 /MD"
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set "LFLAGS=/link ""/libpath:%HLS_INSTALL_DIR%\host\windows64\lib"" hls_emul.lib /out:!TARGET!.exe"
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)
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if "!TARGET!" == "c" (
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call :clean_all_subroutine
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goto:eof
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)
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if "!TARGET!" == "r" (
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call :open_report_subroutine
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goto:eof
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)
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if "!TARGET!" == "v" (
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if exist ".\s.prj\verification\vsim.wlf" (
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echo:
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echo DBG: vsim.wlf file - open in Mdelsim
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modelsim.exe -view ".\s.prj\verification\vsim.wlf" -do "add wave -position insertpoint vsim:/tb/%COMPONENT%_inst/*"
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rem @pause
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) else (
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echo:
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echo ERR: =================================
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echo ERR: vsim.wlf file - doesn`t exist !
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echo ERR: =================================
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)
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goto:eof
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)
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::set "OBJ=%SOURCE_FILES:cpp=o%"
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:: Replace "" with " in the flags
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set "CXXFLAGS=%CXXFLAGS:""="%"
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set "LFLAGS=%LFLAGS:""="%"
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:: Kick off the compile
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echo DBG: executing %CXX% %CXXFLAGS% %SOURCE_FILES% %LFLAGS%
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%CXX% %CXXFLAGS% %SOURCE_FILES% %LFLAGS%
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if not ERRORLEVEL 0 (
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echo:
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echo ERR: ======================
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echo ERR: COMPILATION FAILED !
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echo ERR: ======================
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exit /b 1
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)
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::echo %CXX% %CXXFLAGS% --x86-only %SOURCE_FILES% %LFLAGS%
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::%CXX% %CXXFLAGS% --x86-only -c %SOURCE_FILES% %LFLAGS%
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::echo %CXX% %CXXFLAGS% --fpga-only -c %SOURCE_FILES% %LFLAGS%
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::%CXX% %CXXFLAGS% --fpga-only -c %SOURCE_FILES% %LFLAGS%
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:: Execute the test
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echo:
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echo DBG: Executing the test
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call !TARGET!.exe
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if not ERRORLEVEL 0 (
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echo:
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echo ERR: ==============
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echo ERR: RUN FAILED !
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echo ERR: ==============
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exit /b 1
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)
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if "%TARGET_INIT%" == "q" (
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echo:
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echo DBG: Quartus timing
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findstr /r /c:"Analysis & Synthesis ; 0" %~dp0s.prj\quartus\quartus_compile.flow.rpt
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findstr /r /c:"Partition Merge ; 0" %~dp0s.prj\quartus\quartus_compile.flow.rpt
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findstr /r /c:"Fitter ; 0" %~dp0s.prj\quartus\quartus_compile.flow.rpt
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findstr /r /c:"Fitter ; 0" %~dp0s.prj\quartus\quartus_compile.flow.rpt
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findstr /r /c:"Timing Analyzer ; 0" %~dp0s.prj\quartus\quartus_compile.flow.rpt
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findstr /r /c:"Total ; 0" %~dp0s.prj\quartus\quartus_compile.flow.rpt
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echo:
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call :open_report_subroutine
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)
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:: Make a backup
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echo:
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echo DBG: Making a backup
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:: enabledelayedexpansion turned on. With this mode, ! symbols have special
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:: meaning, and to make matters more interesting, there are two parse passes
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:: on each line, meaning you'll need to double escape them to have the symbol
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:: pass through to the target application
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%Z_PATH% a -t7z .\backup\%Z_DATE%_%Z_TIME%.7z *.* -x^^!backup | findstr /I "Add"
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for /f "tokens=2-4 delims=/ " %%a in ('date /t') do (set Z_DATE=%%c-%%a-%%b)
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for /f "tokens=1-2 delims=/:" %%a in ('time /t') do (set Z_TIME=%%a-%%b)
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echo DBG: end timestamp is %Z_DATE%_%Z_TIME%
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echo DBG: Recipe done
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goto:eof
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:clean_all_subroutine
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call :clean_e_subroutine
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call :clean_s_subroutine
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exit /b
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:clean_e_subroutine
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del /S /F /Q e.exe > NUL
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echo DBG: Cleaning emulation done
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exit /b
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:clean_s_subroutine
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del /S /F /Q m.exe s.exe s.prj > NUL
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rmdir /S /Q s.prj > NUL
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echo DBG: Cleaning simulation done
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exit /b
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:open_report_subroutine
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echo DBG: Opening the report
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start "" .\s.prj\reports\report.html
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exit /b
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29
scripts_for_intel_hls/hls_type_size_win64.txt
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29
scripts_for_intel_hls/hls_type_size_win64.txt
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char 1
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signed char 1
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unsigned char 1
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short 2
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short int 2
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signed short 2
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signed short int 2
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unsigned short 2
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unsigned short int 2
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int 4
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signed 4
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signed int 4
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unsigned 4
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unsigned int 4
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long 4
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long int 4
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signed long 4
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signed long int 4
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unsigned long 4
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unsigned long int 4
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long long 8
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long long int 8
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signed long long 8
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signed long long int 8
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unsigned long long 8
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unsigned long long int 8
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float 4
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double 8
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long double 8
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10
scripts_for_intel_hls/i.bat
Executable file
10
scripts_for_intel_hls/i.bat
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:: 1. Place this file into:
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:: C:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\
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:: 2. Find link with this name in Start menu
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:: "Visual Studio x64 Win64 Command Prompt (2010)"
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:: 3. Copy the link to the desktop. Launch. Execute following command
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:: i.bat[Enter]
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:: 4. Intel HLS should be initialized now
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cd "C:\intelFPGA\18.0\hls\"
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call "init_hls.bat"
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40
scripts_for_intel_hls/test.cpp
Executable file
40
scripts_for_intel_hls/test.cpp
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#include "HLS/hls.h"
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#include <HLS/stdio.h>
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#include <HLS/math.h>
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#include <stdint.h>
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using namespace ihc;
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//component unsigned int test() {
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// static unsigned int cnt = 0;
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// return cnt++;
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//}
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component int dut(int a, int b) {
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return a*b;
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}
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int main (void) {
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//int x1, x2, x3;
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int x[3];
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for (int i = 0; i < 3; i++) x[i]=1;
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printf("1: x1 = %d, x2 = %d, x3 = %d\n", x[0], x[1], x[2]);
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x[0] = dut(7, 8);
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x[1] = dut(9, 10);
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x[2] = dut(11, 12);
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printf("2: x1 = %d, x2 = %d, x3 = %d\n", x[0], x[1], x[2]);
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for (int i = 0; i < 3; i++) x[i]=2;
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printf("3: x1 = %d, x2 = %d, x3 = %d\n", x[0], x[1], x[2]);
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ihc_hls_enqueue((int*)(x+0), &dut, 7, 8);
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ihc_hls_enqueue((int*)(x+1), &dut, 9, 10);
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ihc_hls_enqueue((int*)(x+2), &dut, 11, 12);
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ihc_hls_component_run_all(dut);
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printf("4: x1 = %d, x2 = %d, x3 = %d\n", x[0], x[1], x[2]);
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return 0;
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}
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