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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00

Added scripts

This commit is contained in:
Konstantin Pavlov 2022-08-24 12:42:56 +03:00
parent 3d0bb13dda
commit 2543bcd567
2 changed files with 29 additions and 0 deletions

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@echo off
rem ----------------------------------------------------------------------------
rem compile_flow_quartus.bat
rem Konstantin Pavlov, pavlovconst@gmail.com
rem ----------------------------------------------------------------------------
rem The simplest way to compile Quartus project from commandline
for /R %%f in (*.qpf) do (
echo "Project name is %%~nf"
quartus_sh --flow compile %%~nf
)
echo "DONE!"
pause
exit

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@echo off
rem ----------------------------------------------------------------------------
rem convert_sof_to_jic.bat
rem Konstantin Pavlov, pavlovconst@gmail.com
rem ----------------------------------------------------------------------------
echo "onverting .SOF to .JIC"
del /s /q .\out\SYNC_MM_PG_prj_128.jic
quartus_cpf -c -d EPCQ128 -s 5CGXFC4C7 .\out\PRJ_NAME.sof .\out\PRJ_NAME_128.jic