FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity

Fix template typo, 'block' paramerer is default

Browse Source
This commit is contained in:
Konstantin Pavlov 2022-11-16 17:07:08 +03:00
parent 65e4657650
commit 257c7fdff7
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
true_dual_port_write_first_2_clock_ram.sv
View File

@ -41,7 +41,7 @@ module true_dual_port_write_first_2_clock_ram #( parameter
RAM_DEPTH = 8,
// optional initialization parameters
RAM_STYLE = "",
RAM_STYLE = "block",
INIT_FILE = ""
)(
input clka,

6
true_single_port_write_first_ram.sv
View File

@ -15,8 +15,8 @@
true_single_port_write_first_ram #(
.RAM_WIDTH( DATA_W ),
.RAM_DEPTH( DEPTH ),
.RAM_STYLE( "init.mem" ), // "block","register","M10K","logic",...
.INIT_FILE( "" )
.RAM_STYLE( "block" ), // "block","register","M10K","logic",...
.INIT_FILE( "init.mem" )
) SR1 (
.clka( w_clk ),
.addra( w_ptr[DEPTH_W-1:0] ),
@ -34,7 +34,7 @@ module true_single_port_write_first_ram #( parameter
RAM_DEPTH = 8,
// optional initialization parameters
RAM_STYLE = "",
RAM_STYLE = "block",
INIT_FILE = ""
)(
input clka,