From 257c7fdff7c7b96fb551961c433b8b36ee852494 Mon Sep 17 00:00:00 2001 From: Konstantin Pavlov Date: Wed, 16 Nov 2022 17:07:08 +0300 Subject: [PATCH] Fix template typo, 'block' paramerer is default --- true_dual_port_write_first_2_clock_ram.sv | 2 +- true_single_port_write_first_ram.sv | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/true_dual_port_write_first_2_clock_ram.sv b/true_dual_port_write_first_2_clock_ram.sv index baa52d9..124fe40 100755 --- a/true_dual_port_write_first_2_clock_ram.sv +++ b/true_dual_port_write_first_2_clock_ram.sv @@ -41,7 +41,7 @@ module true_dual_port_write_first_2_clock_ram #( parameter RAM_DEPTH = 8, // optional initialization parameters - RAM_STYLE = "", + RAM_STYLE = "block", INIT_FILE = "" )( input clka, diff --git a/true_single_port_write_first_ram.sv b/true_single_port_write_first_ram.sv index c0b1ae1..cba091f 100755 --- a/true_single_port_write_first_ram.sv +++ b/true_single_port_write_first_ram.sv @@ -15,8 +15,8 @@ true_single_port_write_first_ram #( .RAM_WIDTH( DATA_W ), .RAM_DEPTH( DEPTH ), - .RAM_STYLE( "init.mem" ), // "block","register","M10K","logic",... - .INIT_FILE( "" ) + .RAM_STYLE( "block" ), // "block","register","M10K","logic",... + .INIT_FILE( "init.mem" ) ) SR1 ( .clka( w_clk ), .addra( w_ptr[DEPTH_W-1:0] ), @@ -34,7 +34,7 @@ module true_single_port_write_first_ram #( parameter RAM_DEPTH = 8, // optional initialization parameters - RAM_STYLE = "", + RAM_STYLE = "block", INIT_FILE = "" )( input clka,