Lots of minor edits

00_obsolete/main_tb.v

@@ -1,87 +0,0 @@
-//------------------------------------------------------------------------------
-// main_tb.v
-// Konstantin Pavlov, pavlovconst@gmail.com
-//------------------------------------------------------------------------------
-
-// INFO ------------------------------------------------------------------------
-// Testbench template with basic clocking, reset and random stimulus signals
-// See main_tb.sv file for SystemVerilog version of this module
-
-`timescale 1ns / 1ps
-
-module main_tb();
-
-reg clk200;
-initial begin
-  #0 clk200 = 1;
-  forever
-    #2.5 clk200 = ~clk200;
-end
-
-reg rst;
-initial begin
-  #10.2 rst = 1;
-  #5 rst = 0;
-  //#10000;
-  forever begin
-    #9985 rst = ~rst;
-    #5 rst = ~rst;
-  end
-end
-wire nrst = ~rst;
-
-reg rst_once;
-initial begin       // initializing non-X data before PLL starts
-  #10.2 rst_once = 1;
-  #5 rst_once = 0;
-end
-initial begin
-  #510.2 rst_once = 1;    // PLL starts at 500ns, clock appears, so doing the reset for modules
-  #5 rst_once = 0;
-end
-wire nrst_once = ~rst_once;
-
-wire [31:0] DerivedClocks;
-ClkDivider CD1 (
-  .clk( clk200 ),
-  .nrst( nrst_once ),
-  .out( DerivedClocks[31:0] )
-);
-defparam CD1.WIDTH = 32;
-
-wire [31:0] E_DerivedClocks;
-EdgeDetect ED1 (
-  .clk( clk200 ),
-  .nrst( nrst_once ),
-  .in( DerivedClocks[31:0] ),
-  .rising( E_DerivedClocks[31:0] ),
-  .falling(  ),
-  .both(  )
-);
-defparam ED1.WIDTH = 32;
-
-wire [15:0] RandomNumber1;
-c_rand RNG1 (
-  .clk( clk200 ),
-  .rst( rst_once ),
-  .reseed( 1'b0 ),
-  .seed_val( DerivedClocks[31:0] ),
-  .out( RandomNumber1[15:0] )
-);
-
-reg start;
-initial begin
-  #100.2 start = 1;
-  #5 start = 0;
-end
-
-// Module under test ==========================================================
-
-wire out1,out2;
-Main M (    // module under test
-  clk200,~clk200,
-  rst_once,
-  out1,out2   // for compiler not to remove logic
-);
-
-endmodule

README.md

@@ -1,6 +1,7 @@
 # basic_verilog
 ### Some basic must-have verilog modules
 (licensed under CC BY-SA 4_0)
+Author: Konstantin Pavlov, pavlovconst@gmail.com
 
 
 ### CONTENTS:
@@ -11,30 +12,32 @@
 
 * **Main_tb.v**   - basic testbench template
 
+* **compile.tcl**   - tcl script to configure and run Modelsim compilation without need to create simulation project manually
+
 * **ActionBurst**   - multichannel one-shot triggering module
 * **ActionBurst2**    - multichannel one-shot triggering with variable steps module
 * **bin2pos**   - converts binary coded value to positional (one-hot) code
-* **ClkDivider**    - wide reference clock divider
+* **clk_divider**    - wide reference clock divider
-* **DeBounce**    - two-cycle debounce for input buttons
+* **debounce**    - two-cycle debounce for input buttons
-* **DynDelay**    - dynamic delay for arbitrary input signal made on general-purpose trigger elements
+* **dynamic_delay**    - dynamic delay for arbitrary input signal made on general-purpose trigger elements
-* **EdgeDetect**    - edge detector, gives one-tick pulses on every signal edge
+* **edge_detect**    - edge detector, gives one-tick pulses on every signal edge
-* **Encoder**   - digital encoder input logic module
+* **encoder**   - digital encoder input logic module
 * **fifo**    - single-clock FIFO buffer (queue) implementation
 * **NDivide**   - primitive integer divider
 * **lifo**   - single-clock LIFO buffer (stack) implementation
+* **leave_one_hot**   - leaves only lowest hot bit in vector
 * **PulseGen**    - generates pulses with given width and delay
-* **bin2pos**   - converts positional (one-hot) value to binary representation
+* **pos2bin**   - converts positional (one-hot) value to binary representation
-* **ResetSet**    - SR trigger variant w/o metastable state, set dominates here
+* **reset_set**    - SR trigger variant w/o metastable state, set dominates here
-* **ReverseVector**    - reverses signal order within multi-bit bus
+* **reverse_vector**    - reverses signal order within multi-bit bus
-* **SetReset**    - SR trigger variant w/o metastable state, reset dominates here
+* **set_reset**    - SR trigger variant w/o metastable state, reset dominates here
-* **StaticDelay**   - static delay for arbitrary input signal made on Xilinx`s SRL16E primitives. Also serves as input synchronizer, a standard way to get rid of metastability issues
+* **spi_master**    - universal spi master module
+* **delay**    - static delay for arbitrary input signal made on Xilinx`s SRL16E primitives. Also serves as input synchronizer, a standard way to get rid of metastability issues
 * **UartRx**    - straightforward yet simple UART receiver implementation for FPGA written in Verilog
 * **UartTx**    - straightforward yet simple UART transmitter implementation for FPGA written in Verilog
 * **UartRxExtreme**   - extreme minimal UART receiver implementation for FPGA written in Verilog
 * **UartTxExtreme**   - extreme minimal UART transmitter implementation for FPGA written in Verilog
 
-Also added some simple testbenches for selected modules
 
-
+Also added testbenches for selected modules
-Author: Konstantin Pavlov, pavlovconst@gmail.com
 

bin2pos.sv

@@ -22,7 +22,7 @@ bin2pos #(
 --- INSTANTIATION TEMPLATE END ---*/
 
 
-module bin2pos #(
+module bin2pos #( parameter
   BIN_WIDTH = 8,
   POS_WIDTH = 2**BIN_WIDTH
 )(

clk_divider.sv

@@ -21,7 +21,7 @@ clk_divider #(
 --- INSTANTIATION TEMPLATE END ---*/
 
 
-module clk_divider #(
+module clk_divider #( parameter
   WIDTH = 32
 )(
   input clk,

debounce.v

@@ -1,16 +1,17 @@
 //--------------------------------------------------------------------------------
-// DeBounce.v
+// debounce.v
 // Konstantin Pavlov, pavlovconst@gmail.com
 //--------------------------------------------------------------------------------
 
 // INFO --------------------------------------------------------------------------------
-// Debounce for two inpus signal samples. Signal may and maynot be periodic
+// Debounce for two inpus signal samples
+// Signal may and maynot be periodic
 // Switches up and down with 3 ticks delay
 
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
-DeBounce DB1 (
+debounce DB1 (
 	.clk(),
 	.nrst( 1'b1 ),
 	.en( 1'b1 ),
@@ -22,7 +23,7 @@ defparam DB1.WIDTH = 1;
 --- INSTANTIATION TEMPLATE END ---*/
 
 
-module DeBounce(clk,nrst,en,in,out);
+module debounce(clk,nrst,en,in,out);
 
 input wire clk;
 input wire nrst;
@@ -51,7 +52,7 @@ end
 
 wire [(WIDTH-1):0] switch_hi = (d2[(WIDTH-1):0] & d1[(WIDTH-1):0]);
 wire [(WIDTH-1):0] n_switch_lo = (d2[(WIDTH-1):0] | d1[(WIDTH-1):0]);
-    
+
 SetReset SR (
 	.clk(clk),
 	.nrst(nrst),

debounce_tb.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// DeBounce_tb.v
+// debounce_tb.v
 // Konstantin Pavlov, pavlovconst@gmail.com
 //--------------------------------------------------------------------------------
 
@@ -9,12 +9,12 @@
 
 `timescale 1ns / 1ps
 
-module DeBounce_tb();
+module debounce_tb();
 
 reg clk200;
 initial begin
         #0 clk200 = 1;
-        forever 
+        forever
             #2.5 clk200 = ~clk200;
 end
 
@@ -77,7 +77,7 @@ end
 
 wire den = RandomNumber1[1] && RandomNumber1[2];
 wire dbout;
-DeBounce DB1 (
+debounce DB1 (
 	.clk(clk200),
 	.nrst(nrst_once),
 	.en(den),
@@ -85,6 +85,5 @@ DeBounce DB1 (
 	.out(dbout)
 	);
 defparam DB1.WIDTH = 1;
-    
+
 endmodule
-	

delay.sv

@@ -28,15 +28,15 @@ delay #(
 --- INSTANTIATION TEMPLATE END ---*/
 
 
-module delay #(
+module delay #( parameter
-  parameter LENGTH = 2;   // delay/synchronizer chain length
+  LENGTH = 2              // delay/synchronizer chain length
                           // default length for synchronizer chain is 2
 )(
   input clk,
   input nrst,
   input ena,
   input in,
-  output out,
+  output out
 );
 
 

dynamic_delay.sv

@@ -28,7 +28,7 @@ dynamic_delay #(
 --- INSTANTIATION TEMPLATE END ---*/
 
 
-module dynamic_delay #(
+module dynamic_delay #( parameter
   LENGTH = 8,               // maximum delay chain width
   SEL_W = $clog2(LENGTH)    // output selector width
 )(
@@ -56,4 +56,4 @@ always_ff @(posedge clk) begin
   end
 end
 
-endmodule
+endmodule

encoder.v

@@ -1,13 +1,13 @@
 //--------------------------------------------------------------------------------
-// Encoder.v
+// encoder.v
 // Konstantin Pavlov, pavlovconst@gmail.com
 //--------------------------------------------------------------------------------
 
 // INFO --------------------------------------------------------------------------------
-//  Digital encoder logic
+//  Digital encoder
 
 
-/*Encoder E1(
+/*encoder E1(
 	.clk(),
 	.nrst(),
 	.incA(),
@@ -17,7 +17,7 @@
 	);*/
 
 
-module Encoder(clk,nrst,incA,incB,plus1,minus1);
+module encoder(clk,nrst,incA,incB,plus1,minus1);
 
 input wire clk;
 input wire nrst;

encoder_tb.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Encoder_tb.v
+// encoder_tb.v
 // Konstantin Pavlov, pavlovconst@gmail.com
 //--------------------------------------------------------------------------------
 
@@ -9,12 +9,12 @@
 
 `timescale 1ns / 1ps
 
-module Encoder_tb();
+module encoder_tb();
 
 reg clk200;
 initial begin
         #0 clk200 = 1;
-        forever 
+        forever
             #2.5 clk200 = ~clk200;
 end
 
@@ -71,7 +71,7 @@ end
 //=================================================
 
 wire p,m;
-Encoder E1(
+encoder E1(
 	.clk(clk200),
 	.nrst(nrst),
 	.incA(RandomNumber1[0]),
@@ -79,6 +79,5 @@ Encoder E1(
 	.plus1(p),
 	.minus1(m)
 	);
-    
+
 endmodule
-	

main_tb.sv

@@ -41,14 +41,11 @@ logic nrst;
 assign nrst = ~rst;
 
 logic rst_once;
-initial begin       // initializing non-X data before PLL starts
+initial begin
   #0 rst_once = 1'b0;
   #10.2 rst_once = 1'b1;
   #5 rst_once = 1'b0;
 end
-initial begin
-  #510.2 rst_once = 1'b1;    // PLL starts at 500ns, clock appears, so doing the reset for modules
-  #5 rst_once = 1'b0;
 end
 
 logic nrst_once;

pos2bin.sv

@@ -25,7 +25,7 @@ pos2bin #(
 --- INSTANTIATION TEMPLATE END ---*/
 
 
-module pos2bin #(
+module pos2bin #( parameter
   BIN_WIDTH = 8,
   POS_WIDTH = 2**BIN_WIDTH
 )(

reverse_vector.sv

@@ -21,7 +21,7 @@ reverse_vector #(
 --- INSTANTIATION TEMPLATE END ---*/
 
 
-module reverse_vector #(
+module reverse_vector #( parameter
   WIDTH = 8         // WIDTH must be >=2
 )(
   input [(WIDTH-1):0] in,