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https://github.com/pConst/basic_verilog.git
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Updated lifo module to support FWFT and normal modes
This commit is contained in:
Konstantin Pavlov
parent
452b3574ff
commit
2845a2a836
97
lifo.sv
97
lifo.sv
@ -4,19 +4,29 @@
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Simple single-clock LIFO buffer implementation, also known as "stack"
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// Features one write- and one read- port in FWFT mode
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// See also "fifo.sv" module for similar FIFO buffer implementation
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// Single-clock LIFO buffer implementation, also known as "stack"
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//
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// Features:
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// - single clock operation
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// - configurable depth and data width
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// - one write- and one read- port in "FWFT" or "normal" mode
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// - protected against overflow and underflow
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// - simultaneous read and write operations supported if not full and not empty
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// - only read operation is performed when (full && r_req && w_req)
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// - only write operation is performed when (empty && r_req && w_req)
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//
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// See also "fifo_Single_clock_reg_*.sv" modules for similar FIFO buffer implementation
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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lifo #(
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.FWFT_MODE( "TRUE" ),
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.DEPTH( 8 ),
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.DATA_W( 32 )
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) FF1 (
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) LF1 (
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.clk( clk ),
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.rst( 1'b0 ),
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.nrst( 1'b1 ),
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.w_req( ),
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.w_data( ),
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@ -33,7 +43,10 @@ lifo #(
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module lifo #( parameter
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DEPTH = 4, // max elements count == DEPTH, DEPTH MUST be power of 2
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FWFT_MODE = "TRUE", // "TRUE" - first word fall-trrough" mode
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// "FALSE" - normal fifo mode
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DEPTH = 8, // max elements count == DEPTH, DEPTH MUST be power of 2
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DEPTH_W = $clog2(DEPTH)+1, // elements counter width, extra bit to store
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// "fifo full" state, see cnt[] variable comments
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@ -41,7 +54,7 @@ module lifo #( parameter
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)(
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input clk,
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input rst, // non-inverted reset
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input nrst, // inverted reset
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// input port
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input w_req,
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@ -52,7 +65,7 @@ module lifo #( parameter
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output logic [DATA_W-1:0] r_data,
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// helper ports
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output logic [DATA_W-1:0] cnt = 0,
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output logic [DEPTH_W-1:0] cnt = '0,
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output logic empty,
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output logic full,
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@ -60,51 +73,71 @@ module lifo #( parameter
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);
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// lifo data
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logic [DEPTH-1:0][DATA_W-1:0] data = 0;
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logic [DEPTH-1:0][DATA_W-1:0] data = '0;
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// data output buffer for normal fifo mode
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logic [DATA_W-1:0] data_buf = '0;
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// cnt[] vector always holds lifo elements count
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// data[cnt[]] points to the first empty lifo slot
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// when lifo is full data[cnt[]] points "outside" of data[]
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// please take attention to the case when cnt[]==0 && r_req==1'b1 && w_req==1'b1
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// this case makes no read/write to the lifo and should be handled externally
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// filtered requests
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logic w_req_f;
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assign w_req_f = w_req && ~full;
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logic r_req_f;
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assign r_req_f = r_req && ~empty;
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integer i;
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always_ff @(posedge clk) begin
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if ( rst ) begin
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data <= 0;
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cnt <= 0;
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if ( ~nrst ) begin
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data <= '0;
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cnt[DEPTH_W-1:0] <= '0;
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data_buf[DATA_W-1:0] <= '0;
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end else begin
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case ({w_req, r_req})
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unique case ({w_req_f, r_req_f})
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2'b00: ; // nothing
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2'b01 : begin // reading out
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if ( cnt[DATA_W-1:0] > 1'b0 ) begin
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cnt[DATA_W-1:0] <= cnt[DATA_W-1:0] - 1'b1;
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for ( i = (DEPTH-1); i > 0; i-- ) begin
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data[i-1] <= data[i];
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end
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cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] - 1'b1;
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end
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2'b10 : begin // writing in
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if ( ~full ) begin
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data[cnt[DATA_W-1:0]] <= w_data;
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cnt[DATA_W-1:0] <= cnt[DATA_W-1:0] + 1'b1;
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end
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data[cnt[DEPTH_W-1:0]] <= w_data[DATA_W-1:0];
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cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] + 1'b1;
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end
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2'b11 : begin // simultaneously reading and writing
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if ( cnt[DATA_W-1:0] > 1'b0 ) begin
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data[cnt[DATA_W-1:0]-1] <= w_data;
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end
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// cnt[DATA_W-1:0] <= cnt[DATA_W-1:0]; // data counter does not change
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data[cnt[DEPTH_W-1:0]-1] <= w_data[DATA_W-1:0];
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// data counter does not change here
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end
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default: ;
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endcase
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// data buffer works only for normal lifo mode
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if( r_req_f ) begin
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data_buf[DATA_W-1:0] <= data[0];
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end
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end
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end
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always_comb begin
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empty = ( cnt[DATA_W-1:0] == 0 );
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full = ( cnt[DATA_W-1:0] == DEPTH );
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if (~empty) begin
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r_data[DATA_W-1:0] = data[cnt[DATA_W-1:0]]; // first-word fall-through mode
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always_comb begin
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empty = ( cnt[DEPTH_W-1:0] == '0 );
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full = ( cnt[DEPTH_W-1:0] == DEPTH );
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if( FWFT_MODE == "TRUE" ) begin
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if (~empty) begin
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r_data[DATA_W-1:0] = data[0]; // first-word fall-through mode
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end else begin
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r_data[DATA_W-1:0] = '0;
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end
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end else begin
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r_data[DATA_W-1:0] = 0;
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r_data[DATA_W-1:0] = data_buf[DATA_W-1:0]; // normal mode
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end
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fail = ( empty && r_req ) ||
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105
lifo_tb.sv
105
lifo_tb.sv
@ -13,15 +13,24 @@ module lifo_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1;
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33;
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initial begin
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#0 clk33 = 1'b0;
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forever
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#15.151 clk33 = ~clk33;
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end
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logic rst;
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initial begin
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#10.2 rst = 1;
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#5 rst = 0;
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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@ -33,29 +42,27 @@ logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin // initializing non-X data before PLL starts
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#10.2 rst_once = 1;
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#5 rst_once = 0;
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end
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initial begin
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#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
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#5 rst_once = 0;
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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ClkDivider #(
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clk_divider #(
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.WIDTH( 32 )
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) CD1 (
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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EdgeDetect ED1[31:0] (
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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@ -65,44 +72,84 @@ EdgeDetect ED1[31:0] (
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);
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logic [15:0] RandomNumber1;
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c_rand RNG1 (
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c_rand rng1 (
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.clk(clk200),
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.rst(rst_once),
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.reseed(1'b0),
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.seed_val(DerivedClocks[31:0]),
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.out(RandomNumber1[15:0]));
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.out( RandomNumber1[15:0] )
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);
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/*logic start;
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logic start;
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initial begin
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#0 start = 1'b0;
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#100.2 start = 1'b1;
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#5 start = 1'b0;
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end*/
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logic read;
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initial begin
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#0 read = 1'b0;
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#1000.2 read = 1'b1;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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// Module under test ==========================================================
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// comment or uncomment to test FWFT and normal fifo modes
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//`define TEST_FWFT yes
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// comment or uncomment to sweep-test or random test
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`define TEST_SWEEP yes
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logic full1, empty1;
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logic full1_d1, empty1_d1;
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logic direction1 = 1'b0;
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always_ff @(posedge clk200) begin
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if( ~nrst ) begin
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direction1 <= 1'b0;
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end else begin
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// sweep logic
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if( full1_d1 ) begin
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direction1 <= 1'b1;
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end else if( empty1_d1 ) begin
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direction1 <= 1'b0;
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end
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// these signals allow "erroring" requests testing:
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// - reads from the empty fifo
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// - writes to the filled fifo
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full1_d1 <= full1;
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empty1_d1 <= empty1;
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end
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end
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logic [3:0] cnt1;
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logic [15:0] data_out1;
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lifo #(
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`ifdef TEST_FWFT
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.FWFT_MODE( "TRUE" ),
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`else
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.FWFT_MODE( "FALSE" ),
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`endif
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.DEPTH( 8 ),
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.DATA_W( 16 )
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) LF1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.nrst( nrst_once ),
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`ifdef TEST_SWEEP
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.w_req( ~direction1 && &RandomNumber1[10] ),
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.w_data( RandomNumber1[15:0] ),
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.r_req( direction1 && &RandomNumber1[10] ),
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.r_data( data_out1[15:0] ),
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`else
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.w_req( &RandomNumber1[10:9] ),
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.w_data( RandomNumber1[15:0] ),
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.r_req( read ),
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.r_data( ),
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.r_req( &RandomNumber1[8:7] ),
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.r_data( data_out1[15:0] ),
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`endif
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.cnt( ),
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.empty( ),
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.full( )
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.cnt( cnt1[3:0] ),
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.empty( empty1 ),
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.full( full1 )
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);
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