From 2d2041a663a4c83d25b883ace75469511ea7dd1d Mon Sep 17 00:00:00 2001 From: Konstantin Pavlov Date: Fri, 30 Oct 2020 11:51:59 +0300 Subject: [PATCH] Fixed usedw[] calculations in preview_fifo. Other minor fixes --- dynamic_delay.sv | 16 +++++++------- preview_fifo.sv | 52 ++++++++++++++++++++++++++++------------------ preview_fifo_tb.sv | 6 +++--- pulse_stretch.sv | 4 ++-- 4 files changed, 46 insertions(+), 32 deletions(-) diff --git a/dynamic_delay.sv b/dynamic_delay.sv index e4a3d33..302fe70 100755 --- a/dynamic_delay.sv +++ b/dynamic_delay.sv @@ -34,18 +34,20 @@ dynamic_delay #( module dynamic_delay #( parameter - LENGTH = 63, // maximum delay chain length - WIDTH = 4, // data width + LENGTH = 63, // maximum delay chain length + WIDTH = 4, // data width - SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width - // plus one is for zero delay element + SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width + // plus one is for zero delay element )( input clk, input nrst, input ena, - input [WIDTH-1:0] in, // input data - input [SEL_W-1:0] sel, // output selector - output logic [WIDTH-1:0] out // output data + input [WIDTH-1:0] in, // input data + // bit in[0] is the "oldest" one + // bit in[WIDTH] is considered the most recent + input [SEL_W-1:0] sel, // output selector + output logic [WIDTH-1:0] out // output data ); diff --git a/preview_fifo.sv b/preview_fifo.sv index 8085cee..e593dbb 100644 --- a/preview_fifo.sv +++ b/preview_fifo.sv @@ -18,20 +18,25 @@ preview_fifo #( .WIDTH( 16 ), - .DEPTH( 16 ) + .DEPTH( 16 ) // must be at least 8 ) pf ( .clk( clk ), .nrst( nrst ), // input port - .wrreq( ), // 3 bit one-hot - .id0( ), // first word - .id1( ), // secong word + .wrreq( ), // 3 bit one-hot + .id0( ), // first word + .id1( ), // secong word // output port - .rdreq( ), // 3 bit one-hot - .od0( ), // first word - .od1( ) // second word + .rdreq( ), // 3 bit one-hot + .od0( ), // first word + .od1( ), // second word + + .empty( [1:0] ), // 2'b00, 2'b10 or 2'b11 + .full( [1:0] ), // 2'b11, 2'b01 or 2'b00 + .usedw( [USED_W:0] ) // attention to the width! + ); --- INSTANTIATION TEMPLATE END ---*/ @@ -66,7 +71,8 @@ module preview_fifo #( parameter // when FIFO has no words - // both of these flags will be active output [1:0] full, // "full" flags, logic is similar to "empty" - output [USED_W-1:0] usedw // word count + output logic[USED_W:0] usedw // word count, attention to the additional + // MSB for holding word count when full ); @@ -81,10 +87,6 @@ logic [1:0][WIDTH-1:0] f_wrdata; logic [1:0] f_rdreq; logic [1:0][WIDTH-1:0] f_rddata; -// usedw0[] == usedw1[] OR usedw0[] == (usedw1[]-1) combinations are possible -logic [1:0][USED_W-2:0] f_usedw; - - // underflow and owerflow protection flags logic w0_valid, w1_valid, w2_valid; logic r0_valid, r1_valid, r2_valid; @@ -148,11 +150,11 @@ always_ff @(posedge clk) begin end else begin if( wr_ptr ) begin if( wrreq[2:0] == 3'b010 && w1_valid ) begin - wr_ptr = ~wr_ptr; // no protection against full + wr_ptr = ~wr_ptr; end end else begin if( wrreq[2:0] == 3'b010 && w0_valid ) begin - wr_ptr = ~wr_ptr; // no protection against full + wr_ptr = ~wr_ptr; end end end // nrst @@ -221,6 +223,9 @@ end // internal FIFOs itself ======================================================= + logic [1:0][USED_W-2:0] f_usedw_i; + logic [1:0][USED_W-1:0] f_usedw; + scfifo #( .LPM_WIDTH( WIDTH ), .LPM_NUMWORDS( DEPTH/2 ), // must be at least 4 @@ -231,7 +236,7 @@ end .ENABLE_ECC( "FALSE" ), .ALLOW_RWCYCLE_WHEN_FULL( "ON" ), .USE_EAB( "ON" ) - ) fifo0 ( + ) internal_fifo0 ( .clock( clk ), .aclr( 1'b0 ), .sclr( ~nrst ), @@ -243,7 +248,7 @@ end .q( f_rddata[0][WIDTH-1:0] ), .empty( empty[0] ), .full( full[0] ), - .usedw( f_usedw[0][USED_W-2:0] ) + .usedw( f_usedw_i[0][USED_W-2:0] ) ); scfifo #( @@ -256,7 +261,7 @@ end .ENABLE_ECC( "FALSE" ), .ALLOW_RWCYCLE_WHEN_FULL( "ON" ), .USE_EAB( "ON" ) - ) fifo1 ( + ) internal_fifo1 ( .clock( clk ), .aclr( 1'b0 ), .sclr( ~nrst ), @@ -268,11 +273,18 @@ end .q( f_rddata[1][WIDTH-1:0] ), .empty( empty[1] ), .full( full[1] ), - .usedw( f_usedw[1][USED_W-2:0] ) + .usedw( f_usedw_i[1][USED_W-2:0] ) ); -assign usedw[USED_W-1:0] = f_usedw[0][USED_W-2:0] + f_usedw[1][USED_W-2:0]; - + always_comb begin + f_usedw[0][USED_W-1:0] = ( full[0] )? + ( 1<<(USED_W-1) ): + ( {1'b0,f_usedw_i[0][USED_W-2:0]} ); + f_usedw[1][USED_W-1:0] = ( full[1] )? + ( 1<<(USED_W-1) ): + ( {1'b0,f_usedw_i[1][USED_W-2:0]} ); + usedw[USED_W:0] = f_usedw[0][USED_W-1:0] + f_usedw[1][USED_W-1:0]; + end endmodule diff --git a/preview_fifo_tb.sv b/preview_fifo_tb.sv index b68a4ef..c337be5 100644 --- a/preview_fifo_tb.sv +++ b/preview_fifo_tb.sv @@ -126,7 +126,7 @@ end logic [1:0] empty; logic [1:0] full; -logic [4:0] usedw; +logic [5:0] usedw; logic [7:0] od0; logic [7:0] od1; @@ -134,7 +134,7 @@ logic [7:0] od1; logic [2:0] rdreq; always_ff @(posedge clk200) begin `ifdef R_ENA - if( (usedw[4:0] >= 4) ) begin //&& dis_writes ) begin + if( (usedw[5:0] >= 4) ) begin //&& dis_writes ) begin if( RandomNumber1[14:13] == 2'b11 ) begin rdreq[2:0] <= 3'b010; //$display("RD 1 %h",od0[7:0]); @@ -197,7 +197,7 @@ preview_fifo #( .empty( empty[1:0] ), .full( full[1:0] ), - .usedw( usedw[4:0] ) + .usedw( usedw[5:0] ) ); diff --git a/pulse_stretch.sv b/pulse_stretch.sv index 740ccef..714f028 100644 --- a/pulse_stretch.sv +++ b/pulse_stretch.sv @@ -13,8 +13,8 @@ /* --- INSTANTIATION TEMPLATE BEGIN --- pulse_stretch #( - .WIDTH( 8 ) - .USE_COUNTER(0) + .WIDTH( 8 ), + .USE_CNTR( 0 ) ) ps1 ( .clk( clk ), .nrst( nrst ),