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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

snake_case for reverse_vector module and its testbench

This commit is contained in:
Konstantin Pavlov (fm) 2019-01-09 14:32:02 +03:00
parent 842496f0da
commit 2d8e67db35
2 changed files with 8 additions and 8 deletions

6
ReverseVector.sv → reverse_vector.sv Executable file → Normal file
View File

@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
// ReverseVector.sv
// reverse_vector.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
@ -11,7 +11,7 @@
/* --- INSTANTIATION TEMPLATE BEGIN ---
ReverseVector #(
reverse_vector #(
.WIDTH( 8 ) // WIDTH must be >=2
) RV1 (
.in( smth[7:0] ),
@ -21,7 +21,7 @@ ReverseVector #(
--- INSTANTIATION TEMPLATE END ---*/
module ReverseVector #(
module reverse_vector #(
WIDTH = 8 // WIDTH must be >=2
)(
input [(WIDTH-1):0] in,

10
ReverseVector_tb.sv → reverse_vector_tb.sv Executable file → Normal file
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@ -1,15 +1,15 @@
//------------------------------------------------------------------------------
// ReverseVector_tb.sv
// reverse_vector_tb.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
// INFO ------------------------------------------------------------------------
// testbench for ReverseVector module
// testbench for reverse_vector module
`timescale 1ns / 1ps
module main_tb();
module reverse_vector_tb();
logic clk200;
initial begin
@ -84,7 +84,7 @@ end
// odd width
logic [14:0] reversed1;
ReverseVector #(
reverse_vector #(
.WIDTH( 15 ) // WIDTH must be >=2
) RV1 (
.in( RandomNumber1[14:0] ),
@ -93,7 +93,7 @@ ReverseVector #(
// even width
logic [13:0] reversed2;
ReverseVector #(
reverse_vector #(
.WIDTH( 14 ) // WIDTH must be >=2
) RV2 (
.in( reversed1[13:0] ),