diff --git a/ReverseVector.sv b/reverse_vector.sv old mode 100755 new mode 100644 similarity index 95% rename from ReverseVector.sv rename to reverse_vector.sv index 770b5ca..f580417 --- a/ReverseVector.sv +++ b/reverse_vector.sv @@ -1,5 +1,5 @@ //------------------------------------------------------------------------------ -// ReverseVector.sv +// reverse_vector.sv // Konstantin Pavlov, pavlovconst@gmail.com //------------------------------------------------------------------------------ @@ -11,7 +11,7 @@ /* --- INSTANTIATION TEMPLATE BEGIN --- -ReverseVector #( +reverse_vector #( .WIDTH( 8 ) // WIDTH must be >=2 ) RV1 ( .in( smth[7:0] ), @@ -21,7 +21,7 @@ ReverseVector #( --- INSTANTIATION TEMPLATE END ---*/ -module ReverseVector #( +module reverse_vector #( WIDTH = 8 // WIDTH must be >=2 )( input [(WIDTH-1):0] in, diff --git a/ReverseVector_tb.sv b/reverse_vector_tb.sv old mode 100755 new mode 100644 similarity index 93% rename from ReverseVector_tb.sv rename to reverse_vector_tb.sv index 0a4a7e4..7bccabe --- a/ReverseVector_tb.sv +++ b/reverse_vector_tb.sv @@ -1,15 +1,15 @@ //------------------------------------------------------------------------------ -// ReverseVector_tb.sv +// reverse_vector_tb.sv // Konstantin Pavlov, pavlovconst@gmail.com //------------------------------------------------------------------------------ // INFO ------------------------------------------------------------------------ -// testbench for ReverseVector module +// testbench for reverse_vector module `timescale 1ns / 1ps -module main_tb(); +module reverse_vector_tb(); logic clk200; initial begin @@ -84,7 +84,7 @@ end // odd width logic [14:0] reversed1; -ReverseVector #( +reverse_vector #( .WIDTH( 15 ) // WIDTH must be >=2 ) RV1 ( .in( RandomNumber1[14:0] ), @@ -93,7 +93,7 @@ ReverseVector #( // even width logic [13:0] reversed2; -ReverseVector #( +reverse_vector #( .WIDTH( 14 ) // WIDTH must be >=2 ) RV2 ( .in( reversed1[13:0] ),