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Updated debounce
This commit is contained in:
Konstantin Pavlov
parent
0a7385391a
commit
2e3551056b
66
debounce.v
66
debounce.v
@ -1,66 +0,0 @@
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//--------------------------------------------------------------------------------
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// debounce.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Debounce for two inpus signal samples
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// Signal may and maynot be periodic
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// Switches up and down with 3 ticks delay
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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debounce DB1 (
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.clk(),
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.nrst( 1'b1 ),
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.en( 1'b1 ),
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.in(),
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.out()
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);
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defparam DB1.WIDTH = 1;
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--- INSTANTIATION TEMPLATE END ---*/
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module debounce(clk,nrst,en,in,out);
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input wire clk;
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input wire nrst;
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input wire en;
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input wire [(WIDTH-1):0] in;
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output wire [(WIDTH-1):0] out; // also "present state"
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parameter WIDTH = 1;
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reg [(WIDTH-1):0] d1 = 0;
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reg [(WIDTH-1):0] d2 = 0;
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always @ (posedge clk) begin
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if (~nrst) begin
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d1[(WIDTH-1):0] <= 0;
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d2[(WIDTH-1):0] <= 0;
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end
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else begin
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if (en) begin
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d1[(WIDTH-1):0] <= d2[(WIDTH-1):0];
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d2[(WIDTH-1):0] <= in[(WIDTH-1):0];
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end; // if
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end // else
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end
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wire [(WIDTH-1):0] switch_hi = (d2[(WIDTH-1):0] & d1[(WIDTH-1):0]);
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wire [(WIDTH-1):0] n_switch_lo = (d2[(WIDTH-1):0] | d1[(WIDTH-1):0]);
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SetReset SR (
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.clk(clk),
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.nrst(nrst),
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.s(switch_hi[(WIDTH-1):0]),
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.r(~n_switch_lo[(WIDTH-1):0]),
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.q(out[(WIDTH-1):0]),
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.nq()
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);
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defparam SR.WIDTH = WIDTH;
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endmodule
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@ -1,89 +0,0 @@
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//--------------------------------------------------------------------------------
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// debounce_tb.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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//
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//
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`timescale 1ns / 1ps
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module debounce_tb();
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reg clk200;
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initial begin
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#0 clk200 = 1;
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forever
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#2.5 clk200 = ~clk200;
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end
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reg rst;
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initial begin
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#10.2 rst = 1;
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#5 rst = 0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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wire nrst = ~rst;
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reg rst_once;
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initial begin // initializing non-X data before PLL starts
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#10.2 rst_once = 1;
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#5 rst_once = 0;
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end
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initial begin
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#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
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#5 rst_once = 0;
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end
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wire nrst_once = ~rst_once;
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wire [31:0] DerivedClocks;
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ClkDivider CD1 (
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.clk(clk200),
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.nrst(nrst_once),
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.out(DerivedClocks[31:0]));
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defparam CD1.WIDTH = 32;
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wire [31:0] E_DerivedClocks;
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EdgeDetect ED1 (
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.clk(clk200),
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.nrst(nrst_once),
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.in(DerivedClocks[31:0]),
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.rising(E_DerivedClocks[31:0]),
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.falling(),
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.both()
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);
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defparam ED1.WIDTH = 32;
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wire [15:0] RandomNumber1;
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c_rand RNG1 (
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.clk(clk200),
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.rst(rst_once),
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.reseed(1'b0),
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.seed_val(DerivedClocks[31:0]),
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.out(RandomNumber1[15:0]));
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reg start;
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initial begin
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#100.2 start = 1;
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#5 start = 0;
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end
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//=================================================
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wire den = RandomNumber1[1] && RandomNumber1[2];
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wire dbout;
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debounce DB1 (
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.clk(clk200),
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.nrst(nrst_once),
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.en(den),
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.in(RandomNumber1[0]),
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.out(dbout)
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);
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defparam DB1.WIDTH = 1;
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endmodule
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118
debounce_v1.v
Normal file
118
debounce_v1.v
Normal file
@ -0,0 +1,118 @@
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//------------------------------------------------------------------------------
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// debounce_v1.v
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Button debounce v1
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//
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// - sampling inputs using configurable divided clock (ithis is the
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// simplest form of low-pass filter)
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// - switching output only when both samples have equal level
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// (this gives some form of hysteresis in case we sample unstable data)
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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debounce_v1 #(
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.WIDTH( 4 ),
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.SAMPLING_FACTOR( 16 )
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) DB1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.ena( 1'b1 ),
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.in( btn[3:0] ),
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.out( btn_db[3:0] )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module debounce_v1 #( parameter
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WIDTH = 1,
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SAMPLING_FACTOR = 16 // 0 - sampling every clk
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// 1 - sampling on clk/2
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// 2 - sampling on clk/4 etc....
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// only one or none should be enabled
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TREAT_UNSTABLE_AS_HIGH = 0,
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TREAT_UNSTABLE_AS_LOW = 0
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)(
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input clk,
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input nrst,
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input ena,
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input [WIDTH-1:0] in,
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output reg [WIDTH-1:0] out
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);
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localparam SAMPLING_RANGE = 32;
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wire [SAMPLING_RANGE-1:0] s_clk;
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clk_divider #(
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.WIDTH( SAMPLING_RANGE )
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) clk_div (
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.clk( clk ),
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.nrst( nrst ),
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.ena( 1'b1 ),
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.out( s_clk[SAMPLING_RANGE-1:0] )
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);
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wire [SAMPLING_RANGE-1:0] s_clk_rise;
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edge_detect #(
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.WIDTH( SAMPLING_RANGE )
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) clk_div_ed (
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.clk( clk ),
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.anrst( nrst ),
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.in( s_clk[SAMPLING_RANGE-1:0] ),
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.rising( s_clk_rise[SAMPLING_RANGE-1:0] )
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);
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wire do_sample;
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assign do_sample = s_clk_rise[SAMPLING_FACTOR];
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reg [WIDTH-1:0] in_d1 = 0;
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reg [WIDTH-1:0] in_d2 = 0;
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always @(posedge clk) begin
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if (~nrst) begin
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in_d1[WIDTH-1:0] <= 0;
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in_d2[WIDTH-1:0] <= 0;
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end else if (ena && do_sample) begin
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in_d1[WIDTH-1:0] <= in_d2[WIDTH-1:0];
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in_d2[WIDTH-1:0] <= in[WIDTH-1:0];
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end // if
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end
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integer i;
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always @(posedge clk) begin
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if( ~nrst ) begin
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out[WIDTH-1:0] <= 0;
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end else begin
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// every input has its own state
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for (i = 0; i < WIDTH; i=i+1) begin
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case ( {in_d2[i],in_d1[i]} )
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2'b00: out[i] <= 1'b0;
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2'b11: out[i] <= 1'b1;
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default: begin
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if (TREAT_UNSTABLE_AS_HIGH) begin
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out[i] <= 1'b1;
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end else if (TREAT_UNSTABLE_AS_LOW) begin
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out[i] <= 1'b0;
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end
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end
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endcase
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end // for
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end
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end
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endmodule
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126
debounce_v2.sv
Normal file
126
debounce_v2.sv
Normal file
@ -0,0 +1,126 @@
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//------------------------------------------------------------------------------
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// debounce_v2.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Button debounce v2, SystemVerilog version
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//
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// - sampling inputs using configurable divided clock (ithis is the
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// simplest form of low-pass filter)
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//
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// - in contrast with debounce_v1.v this implementation is switching output only
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// when input had stable level IN ALL CLOCK CYCLES within the sample window
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// (this gives some form of hysteresis in case we sample unstable data)
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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debounce_v2 #(
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.WIDTH( 4 ),
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.SAMPLING_FACTOR( 16 )
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) DB1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.ena( 1'b1 ),
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.in( btn[3:0] ),
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.out( btn_db[3:0] )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module debounce_v2 #( parameter
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WIDTH = 1,
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SAMPLING_FACTOR = 16, // 0 - sampling every clk
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// 1 - sampling on clk/2
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// 2 - sampling on clk/4 etc....
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// only one or none should be enabled
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TREAT_UNSTABLE_AS_HIGH = 0,
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TREAT_UNSTABLE_AS_LOW = 0
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)(
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input clk,
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input nrst,
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input ena,
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input [WIDTH-1:0] in,
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output logic [WIDTH-1:0] out
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);
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localparam SAMPLING_RANGE = 32;
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logic [SAMPLING_RANGE-1:0] s_clk;
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clk_divider #(
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.WIDTH( SAMPLING_RANGE )
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) clk_div (
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.clk( clk ),
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.nrst( nrst ),
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.ena( 1'b1 ),
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.out( s_clk[SAMPLING_RANGE-1:0] )
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);
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logic [SAMPLING_RANGE-1:0] s_clk_rise;
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edge_detect #(
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.WIDTH( SAMPLING_RANGE )
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) clk_div_ed (
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.clk( clk ),
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.anrst( nrst ),
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.in( s_clk[SAMPLING_RANGE-1:0] ),
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.rising( s_clk_rise[SAMPLING_RANGE-1:0] )
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);
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wire do_sample;
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assign do_sample = s_clk_rise[SAMPLING_FACTOR];
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logic [WIDTH-1:0] in_is_high = 0;
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logic [WIDTH-1:0] in_is_low = 0;
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always_ff @(posedge clk) begin
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if (~nrst) begin
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out[WIDTH-1:0] <= 0;
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in_is_high[WIDTH-1:0] <= 0;
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in_is_low[WIDTH-1:0] <= 0;
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end else if (ena && do_sample) begin
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// making decisions for outputs
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for (integer i = 0; i < WIDTH; i++) begin
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case ( {in_is_high[i],in_is_low[i]} )
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2'b01: out[i] <= 1'b0;
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2'b10: out[i] <= 1'b1;
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default: begin
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if (TREAT_UNSTABLE_AS_HIGH) begin
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out[i] <= 1'b1;
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end else if (TREAT_UNSTABLE_AS_LOW) begin
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out[i] <= 1'b0;
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end
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end
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endcase
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end // for
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// resetting flags to initialize new sample window
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in_is_high[WIDTH-1:0] <= 0;
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in_is_low[WIDTH-1:0] <= 0;
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end else begin
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// collecting data
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for (integer i = 0; i < WIDTH; i++) begin
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if ( in[i] ) begin
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in_is_high[i] <= 1'b1;
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end else begin
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in_is_low[i] <= 1'b1;
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end
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end // for
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end // if
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end
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endmodule
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127
debounce_v2.v
Normal file
127
debounce_v2.v
Normal file
@ -0,0 +1,127 @@
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//------------------------------------------------------------------------------
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// debounce_v2.v
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
|
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
|
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// Button debounce v2
|
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//
|
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// - sampling inputs using configurable divided clock (ithis is the
|
||||
// simplest form of low-pass filter)
|
||||
//
|
||||
// - in contrast with debounce_v1.v this implementation is switching output only
|
||||
// when input had stable level IN ALL CLOCK CYCLES within the sample window
|
||||
// (this gives some form of hysteresis in case we sample unstable data)
|
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//
|
||||
|
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|
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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debounce_v2 #(
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.WIDTH( 4 ),
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.SAMPLING_FACTOR( 16 )
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) DB1 (
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.clk( clk ),
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.nrst( 1'b1 ),
|
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.ena( 1'b1 ),
|
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.in( btn[3:0] ),
|
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.out( btn_db[3:0] )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module debounce_v2 #( parameter
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WIDTH = 1,
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SAMPLING_FACTOR = 16, // 0 - sampling every clk
|
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// 1 - sampling on clk/2
|
||||
// 2 - sampling on clk/4 etc....
|
||||
|
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// only one or none should be enabled
|
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TREAT_UNSTABLE_AS_HIGH = 0,
|
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TREAT_UNSTABLE_AS_LOW = 0
|
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)(
|
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input clk,
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input nrst,
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input ena,
|
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|
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input [WIDTH-1:0] in,
|
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output reg [WIDTH-1:0] out
|
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);
|
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localparam SAMPLING_RANGE = 32;
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wire [SAMPLING_RANGE-1:0] s_clk;
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clk_divider #(
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.WIDTH( SAMPLING_RANGE )
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) clk_div (
|
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.clk( clk ),
|
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.nrst( nrst ),
|
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.ena( 1'b1 ),
|
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.out( s_clk[SAMPLING_RANGE-1:0] )
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);
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wire [SAMPLING_RANGE-1:0] s_clk_rise;
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edge_detect #(
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.WIDTH( SAMPLING_RANGE )
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) clk_div_ed (
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.clk( clk ),
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.anrst( nrst ),
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.in( s_clk[SAMPLING_RANGE-1:0] ),
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.rising( s_clk_rise[SAMPLING_RANGE-1:0] )
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);
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wire do_sample;
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assign do_sample = s_clk_rise[SAMPLING_FACTOR];
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reg [WIDTH-1:0] in_is_high = 0;
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reg [WIDTH-1:0] in_is_low = 0;
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integer i;
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always @(posedge clk) begin
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if (~nrst) begin
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out[WIDTH-1:0] <= 0;
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in_is_high[WIDTH-1:0] <= 0;
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in_is_low[WIDTH-1:0] <= 0;
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end else if (ena && do_sample) begin
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|
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// making decisions for outputs
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for (i = 0; i < WIDTH; i=i+1) begin
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case ( {in_is_high[i],in_is_low[i]} )
|
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2'b01: out[i] <= 1'b0;
|
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2'b10: out[i] <= 1'b1;
|
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default: begin
|
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if (TREAT_UNSTABLE_AS_HIGH) begin
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out[i] <= 1'b1;
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end else if (TREAT_UNSTABLE_AS_LOW) begin
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out[i] <= 1'b0;
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end
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end
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endcase
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end // for
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|
||||
// resetting flags to initialize new sample window
|
||||
in_is_high[WIDTH-1:0] <= 0;
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in_is_low[WIDTH-1:0] <= 0;
|
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end else begin
|
||||
|
||||
// collecting data
|
||||
for (i = 0; i < WIDTH; i=i+1) begin
|
||||
if ( in[i] ) begin
|
||||
in_is_high[i] <= 1'b1;
|
||||
end else begin
|
||||
in_is_low[i] <= 1'b1;
|
||||
end
|
||||
end // for
|
||||
|
||||
end // if
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
220
debounce_v2_tb.sv
Normal file
220
debounce_v2_tb.sv
Normal file
@ -0,0 +1,220 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// debounce_v2_tb_tb.sv
|
||||
// published as part of https://github.com/pConst/basic_verilog
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// debounce_v2 testbench
|
||||
|
||||
// use this define to make some things differently in simulation
|
||||
`define SIMULATION yes
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module debounce_v2_tb();
|
||||
|
||||
initial begin
|
||||
// Print out time markers in nanoseconds
|
||||
// Example: $display("[T=%0t] start=%d", $realtime, start);
|
||||
$timeformat(-9, 3, " ns");
|
||||
|
||||
// seed value setting is intentionally manual to achieve repeatability between sim runs
|
||||
$urandom( 1 ); // SEED value
|
||||
end
|
||||
|
||||
logic clk200;
|
||||
sim_clk_gen #(
|
||||
.FREQ( 200_000_000 ), // in Hz
|
||||
.PHASE( 0 ), // in degrees
|
||||
.DUTY( 50 ), // in percentage
|
||||
.DISTORT( 10 ) // in picoseconds
|
||||
) clk200_gen (
|
||||
.ena( 1'b1 ),
|
||||
.clk( clk200 ),
|
||||
.clkd( )
|
||||
);
|
||||
|
||||
logic nrst_once;
|
||||
|
||||
logic [31:0] clk200_div;
|
||||
clk_divider #(
|
||||
.WIDTH( 32 )
|
||||
) cd1 (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
.ena( 1'b1 ),
|
||||
.out( clk200_div[31:0] )
|
||||
);
|
||||
|
||||
logic [31:0] clk200_div_rise;
|
||||
edge_detect ed1[31:0] (
|
||||
.clk( {32{clk200}} ),
|
||||
.anrst( {32{nrst_once}} ),
|
||||
.in( clk200_div[31:0] ),
|
||||
.rising( clk200_div_rise[31:0] ),
|
||||
.falling( ),
|
||||
.both( )
|
||||
);
|
||||
|
||||
// external device "asynchronous" clock
|
||||
logic clk33;
|
||||
logic clk33d;
|
||||
sim_clk_gen #(
|
||||
.FREQ( 200_000_000 ), // in Hz
|
||||
.PHASE( 0 ), // in degrees
|
||||
.DUTY( 50 ), // in percentage
|
||||
.DISTORT( 1000 ) // in picoseconds
|
||||
) clk33_gen (
|
||||
.ena( 1'b1 ),
|
||||
.clk( clk33 ),
|
||||
.clkd( clk33d )
|
||||
);
|
||||
|
||||
|
||||
logic rst;
|
||||
initial begin
|
||||
rst = 1'b0; // initialization
|
||||
repeat( 1 ) @(posedge clk200);
|
||||
|
||||
forever begin
|
||||
repeat( 1 ) @(posedge clk200); // synchronous rise
|
||||
rst = 1'b1;
|
||||
//$urandom( 1 ); // uncomment to get the same random pattern EVERY nrst
|
||||
|
||||
repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst pulse width
|
||||
rst = 1'b0;
|
||||
|
||||
repeat( 100 ) @(posedge clk200); // controls test body width
|
||||
end
|
||||
end
|
||||
logic nrst;
|
||||
assign nrst = ~rst;
|
||||
|
||||
|
||||
logic rst_once;
|
||||
initial begin
|
||||
rst_once = 1'b0; // initialization
|
||||
repeat( 1 ) @(posedge clk200);
|
||||
|
||||
repeat( 1 ) @(posedge clk200); // synchronous rise
|
||||
rst_once = 1'b1;
|
||||
|
||||
repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst_once pulse width
|
||||
rst_once = 1'b0;
|
||||
end
|
||||
//logic nrst_once; // declared before
|
||||
assign nrst_once = ~rst_once;
|
||||
|
||||
|
||||
// random pattern generation
|
||||
logic [31:0] rnd_data;
|
||||
always_ff @(posedge clk200) begin
|
||||
rnd_data[31:0] <= $urandom;
|
||||
end
|
||||
|
||||
initial forever begin
|
||||
@(posedge nrst);
|
||||
$display("[T=%0t] rnd_data[]=%h", $realtime, rnd_data[31:0]);
|
||||
end
|
||||
|
||||
|
||||
// helper start strobe appears unpredictable up to 20 clocks after nrst
|
||||
logic start;
|
||||
initial forever begin
|
||||
start = 1'b0; // initialization
|
||||
|
||||
@(posedge nrst); // synchronous rise after EVERY nrst
|
||||
repeat( $urandom_range(0, 20) ) @(posedge clk200);
|
||||
start = 1'b1;
|
||||
|
||||
@(posedge clk200); // synchronous fall exactly 1 clock after rise
|
||||
start = 1'b0;
|
||||
end
|
||||
|
||||
|
||||
initial begin
|
||||
// #10000 $stop;
|
||||
// #10000 $finish;
|
||||
end
|
||||
|
||||
// sweeping pulses
|
||||
logic sp = 1'b1;
|
||||
logic [4:0] sp_duty_cycle = 8'd0;
|
||||
initial forever begin
|
||||
if( sp_duty_cycle[4:0] == 0 ) begin
|
||||
sp = 1'b1;
|
||||
repeat( 10 ) @(posedge clk200);
|
||||
end
|
||||
sp = 1'b0;
|
||||
repeat( 1 ) @(posedge clk200);
|
||||
sp = 1'b1;
|
||||
repeat( 1 ) @(posedge clk200);
|
||||
sp = 1'b0;
|
||||
repeat( sp_duty_cycle ) @(posedge clk200);
|
||||
sp_duty_cycle[4:0] = sp_duty_cycle[4:0] + 1'b1; // overflow is expected here
|
||||
end
|
||||
|
||||
|
||||
// Module under test ===========================================================
|
||||
|
||||
logic [15:0] seq_cntr = '0;
|
||||
|
||||
logic [31:0] id = '0;
|
||||
always_ff @(posedge clk200) begin
|
||||
if( ~nrst_once ) begin
|
||||
seq_cntr[15:0] <= '0;
|
||||
id[31:0] <= '0;
|
||||
end else begin
|
||||
// incrementing sequence counter
|
||||
if( seq_cntr[15:0]!= '1 ) begin
|
||||
seq_cntr[15:0] <= seq_cntr[15:0] + 1'b1;
|
||||
end
|
||||
|
||||
if( seq_cntr[15:0]<300 ) begin
|
||||
id[31:0] <= '1;
|
||||
//id[31:0] <= {4{rnd_data[15:0]}};
|
||||
end else begin
|
||||
id[31:0] <= '0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
debounce_v2 #(
|
||||
.WIDTH( 8 ),
|
||||
.SAMPLING_FACTOR( 2 )
|
||||
) M (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
.ena( 1'b1 ),
|
||||
.in( rnd_data[7:0] ),
|
||||
.out( )
|
||||
);
|
||||
|
||||
debounce_v2 #(
|
||||
.WIDTH( 8 ),
|
||||
.SAMPLING_FACTOR( 2 ),
|
||||
.TREAT_UNSTABLE_AS_HIGH( 1 )
|
||||
) MH (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
.ena( 1'b1 ),
|
||||
.in( rnd_data[7:0] ),
|
||||
.out( )
|
||||
);
|
||||
|
||||
debounce_v2 #(
|
||||
.WIDTH( 8 ),
|
||||
.SAMPLING_FACTOR( 2 ),
|
||||
.TREAT_UNSTABLE_AS_LOW( 1 )
|
||||
) ML (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
.ena( 1'b1 ),
|
||||
.in( rnd_data[7:0] ),
|
||||
.out( )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user