Added module to switch dims in a 2D systemverilog array

reverse_dimensions.sv

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+//------------------------------------------------------------------------------
+// reverse_dimensions.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  "Physically" reverses dimension order in systemv_erilog 2D vector
+//  Thus in[7][1] signal becomes out[1][7], in[6][10] becomes out[10][6] and vise-versa
+//  Module is no doubt synthesizable, but its instance does NOT occupy any FPGA resources!
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+reverse_dimensions #(
+  .D1_WIDTH( 8 ),
+  .D2_WIDTH( 3 )
+) RD1 (
+  .in( smth[7:0][2:0] ),
+  .out( htms[2:0][7:0] )   // reversed bit order
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module reverse_dimensions #( parameter
+  D1_WIDTH = 8,        // first dimention width
+  D2_WIDTH = 3         // second dimention width
+)(
+  input [D1_WIDTH-1:0][D2_WIDTH-1:0] in,
+  output logic [D2_WIDTH-1:0][D1_WIDTH-1:0] out
+);
+
+
+genvar i;
+genvar j;
+generate
+  for (i = 0; i < D1_WIDTH ; i++) begin : gen_i
+  for (j = 0; j < D2_WIDTH ; j++) begin : gen_j
+
+    always_comb begin
+      out[j][i] = in[i][j];
+    end // always_comb
+
+  end // for
+  end // for
+endgenerate
+
+endmodule

reverse_dimensions_tb/c_rand.v

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+// Copyright 2007 Altera Corporation. All rights reserved.  
+// Altera products are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.  
+//
+// This reference design file, and your use thereof, is subject to and governed
+// by the terms and conditions of the applicable Altera Reference Design 
+// License Agreement (either as signed by you or found at www.altera.com).  By
+// using this reference design file, you indicate your acceptance of such terms
+// and conditions between you and Altera Corporation.  In the event that you do
+// not agree with such terms and conditions, you may not use the reference 
+// design file and please promptly destroy any copies you have made.
+//
+// This reference design file is being provided on an "as-is" basis and as an 
+// accommodation and therefore all warranties, representations or guarantees of 
+// any kind (whether express, implied or statutory) including, without 
+// limitation, warranties of merchantability, non-infringement, or fitness for
+// a particular purpose, are specifically disclaimed.  By making this reference
+// design file available, Altera expressly does not recommend, suggest or 
+// require that this reference design file be used in combination with any 
+// other product not provided by Altera.
+/////////////////////////////////////////////////////////////////////////////
+
+// C runtime library random number generator
+//
+// uses 32 logic cells for DFF/ADD and 8 DSP blocks for the
+// 32x18=>32 multiply
+
+module c_rand (clk,rst,reseed,seed_val,out);
+input clk,rst,reseed;
+input [31:0] seed_val;
+output [15:0] out;
+wire [15:0] out;
+
+reg [31:0] state;
+
+always @(posedge clk or posedge rst) begin
+	if (rst) state <= 0;
+	else begin
+		if (reseed) state <= seed_val;
+		else begin
+			state <= state * 32'h343fd + 32'h269EC3;
+		end
+	end
+end
+
+assign out = (state >> 16) & 16'h7fff;
+
+endmodule

reverse_dimensions_tb/compile.bat

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+modelsim.exe -do compile.tcl

reverse_dimensions_tb/compile.sh

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+#!/bin/bash
+
+#  compile.sh
+#  Konstantin Pavlov, pavlovconst@gmail.com
+#
+#  This is a support script for launching "Modelsim compile script" on Linux
+
+
+vsim -do compile.tcl

reverse_dimensions_tb/compile.tcl

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+#------------------------------------------------------------------------------
+# compile.tcl
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# INFO ------------------------------------------------------------------------
+# Modelsim compile script
+# based on "ModelSimSE general compile script version 1.1" by Doulos
+
+# launch the script by "vsim -do compile.tcl" command on linux
+# or by "modelsim.exe -do compile.tcl" on windows
+
+
+# Simply change the project settings in this section
+# for each new project. There should be no need to
+# modify the rest of the script.
+set library_file_list {
+
+  work {reverse_dimensions_tb.sv
+        ../reverse_dimensions.sv
+        c_rand.v
+        ../edge_detect.sv
+        ../clk_divider.sv}
+}
+
+set vsim_params "-L altera_mf_ver -L altera_mf -L lpm_ver -L lpm"
+
+set top_level work.reverse_dimensions_tb
+
+# Console commands:
+# r = Recompile changed and dependent files
+# rr = Recompile everything
+# q = Quit without confirmation
+
+# After sourcing the script from ModelSim for the
+# first time use these commands to recompile.
+proc r  {} {uplevel #0 source compile.tcl}
+proc rr {} {global last_compile_time
+            set last_compile_time 0
+            r                            }
+proc q  {} {quit -force                  }
+
+#Does this installation support Tk?
+set tk_ok 1
+if [catch {package require Tk}] {set tk_ok 0}
+
+# Prefer a fixed point font for the transcript
+set PrefMain(font) {Courier 10 roman normal}
+
+# Compile out of date files
+set time_now [clock seconds]
+if [catch {set last_compile_time}] {
+  set last_compile_time 0
+}
+foreach {library file_list} $library_file_list {
+  vlib $library
+  vmap work $library
+  foreach file $file_list {
+    if { $last_compile_time < [file mtime $file] } {
+      if [regexp {.vhdl?$} $file] {
+        vcom -93 $file
+      } else {
+        vlog -sv $file
+      }
+      set last_compile_time 0
+    }
+  }
+}
+set last_compile_time $time_now
+
+# Load the simulation
+eval vsim $top_level $vsim_params
+
+# Load saved wave patterns
+do wave.do
+
+# Run the simulation
+run 100us
+
+wave zoom range 0 100us
+
+# How long since project began?
+if {[file isfile start_time.txt] == 0} {
+  set f [open start_time.txt w]
+  puts $f "Start time was [clock seconds]"
+  close $f
+} else {
+  set f [open start_time.txt r]
+  set line [gets $f]
+  close $f
+  regexp {\d+} $line start_time
+  set total_time [expr ([clock seconds]-$start_time)/60]
+  puts "Project time is $total_time minutes"
+}
+

reverse_dimensions_tb/reverse_dimensions_tb.sv

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+//------------------------------------------------------------------------------
+// reverse_dimensions_tb.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// testbench for reverse_dimensions module
+
+
+`timescale 1ns / 1ps
+
+module reverse_dimensions_tb();
+
+logic clk200;
+initial begin
+  #0 clk200 = 1;
+  forever
+    #2.5 clk200 = ~clk200;
+end
+
+logic rst;
+initial begin
+  #10.2 rst = 1;
+  #5 rst = 0;
+  //#10000;
+  forever begin
+    #9985 rst = ~rst;
+    #5 rst = ~rst;
+  end
+end
+
+logic nrst;
+assign nrst = ~rst;
+
+logic rst_once;
+initial begin       // initializing non-X data before PLL starts
+  #10.2 rst_once = 1;
+  #5 rst_once = 0;
+end
+initial begin
+  #510.2 rst_once = 1;    // PLL starts at 500ns, clock appears, so doing the reset for modules
+  #5 rst_once = 0;
+end
+
+logic nrst_once;
+assign nrst_once = ~rst_once;
+
+logic [31:0] DerivedClocks;
+clk_divider #(
+  .WIDTH( 32 )
+) CD1 (
+  .clk( clk200 ),
+  .nrst( nrst_once ),
+  .ena( 1'b1 ),
+  .out( DerivedClocks[31:0] )
+);
+
+logic [31:0] E_DerivedClocks;
+edge_detect ED1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
+  .in( DerivedClocks[31:0] ),
+  .rising( E_DerivedClocks[31:0] ),
+  .falling(  ),
+  .both(  )
+);
+
+logic [15:0] RandomNumber1;
+c_rand RNG1 (
+  .clk( clk200 ),
+  .rst( rst_once ),
+  .reseed( 1'b0 ),
+  .seed_val( DerivedClocks[31:0] ),
+  .out( RandomNumber1[15:0] )
+);
+
+logic start;
+initial begin
+  #0 start = 1'b0;
+  #100.2 start = 1'b1;
+  #5 start = 1'b0;
+end
+
+// Module under test ==========================================================
+
+logic [1:0][7:0] in;
+assign in = RandomNumber1[15:0];
+
+
+logic [7:0][1:0] out;
+reverse_dimensions #(
+  .D1_WIDTH( 2 ),
+  .D2_WIDTH( 8 )
+) RD1 (
+  .in(   in ),
+  .out( out )
+);
+
+endmodule

reverse_dimensions_tb/wave.do

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+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix binary -childformat {{{/reverse_dimensions_tb/RD1/in[1]} -radix binary} {{/reverse_dimensions_tb/RD1/in[0]} -radix binary}} -expand -subitemconfig {{/reverse_dimensions_tb/RD1/in[1]} {-radix binary} {/reverse_dimensions_tb/RD1/in[0]} {-radix binary}} /reverse_dimensions_tb/RD1/in
+add wave -noupdate -radix binary -childformat {{{/reverse_dimensions_tb/RD1/out[7]} -radix binary} {{/reverse_dimensions_tb/RD1/out[6]} -radix binary} {{/reverse_dimensions_tb/RD1/out[5]} -radix binary} {{/reverse_dimensions_tb/RD1/out[4]} -radix binary -childformat {{{[1]} -radix hexadecimal} {{[0]} -radix hexadecimal}}} {{/reverse_dimensions_tb/RD1/out[3]} -radix binary} {{/reverse_dimensions_tb/RD1/out[2]} -radix binary} {{/reverse_dimensions_tb/RD1/out[1]} -radix binary} {{/reverse_dimensions_tb/RD1/out[0]} -radix binary}} -expand -subitemconfig {{/reverse_dimensions_tb/RD1/out[7]} {-radix binary} {/reverse_dimensions_tb/RD1/out[6]} {-radix binary} {/reverse_dimensions_tb/RD1/out[5]} {-radix binary} {/reverse_dimensions_tb/RD1/out[4]} {-radix binary -childformat {{{[1]} -radix hexadecimal} {{[0]} -radix hexadecimal}}} {/reverse_dimensions_tb/RD1/out[4][1]} {-radix hexadecimal} {/reverse_dimensions_tb/RD1/out[4][0]} {-radix hexadecimal} {/reverse_dimensions_tb/RD1/out[3]} {-radix binary} {/reverse_dimensions_tb/RD1/out[2]} {-radix binary} {/reverse_dimensions_tb/RD1/out[1]} {-radix binary} {/reverse_dimensions_tb/RD1/out[0]} {-radix binary}} /reverse_dimensions_tb/RD1/out
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {21806 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue right
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {4609 ps} {81173 ps}