mirror of
https://github.com/pConst/basic_verilog.git
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Updated test projects to support dev boards
This commit is contained in:
Konstantin Pavlov
parent
db847e6e7e
commit
322fa85652
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Quartus IDE test project template
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# main reference clock, 500 MHz
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create_clock -period 2.000 -waveform { 0.000 1.000 } [get_ports {clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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//------------------------------------------------------------------------------
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// main.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Test project template, v3
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//
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// - use this as a boilerplate project for fast prototyping
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// - inputs and outputs are registered to allow valid timequest output
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// even if your custom logic/IPs have combinational outputs
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// - SDC constraint file assigns clk to 500MHz to force fitter to synthesize
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// the fastest possible circuit
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//
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`define WIDTH
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module main(
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input clk,
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input nrst,
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input [`WIDTH-1:0] in_data,
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output logic [`WIDTH-1:0] out_data
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);
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// input registers
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logic [`WIDTH-1:0] in_data_reg = 0;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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in_data_reg[`WIDTH-1:0] <= '0;
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end else begin
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in_data_reg[`WIDTH-1:0] <= in_data;
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end
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end
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// place your test logic here ==================================================
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logic [31:0] div_clk;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk ),
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.nrst( nrst ),
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.ena( 1'b1 ),
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.out( div_clk[31:0] )
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);
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logic [`WIDTH-1:0] out_data_comb = 0;
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always_comb begin
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out_data_comb[`WIDTH-1:0] <= in_data_reg[`WIDTH-1:0] ^ div_clk[31:0];
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end
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// =============================================================================
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// output registers
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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out_data[`WIDTH-1:0] <= '0;
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end else begin
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out_data[`WIDTH-1:0] <= out_data_comb[`WIDTH-1:0];
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end
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end
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endmodule
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verilog rtl code directory
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rtl code testbenches directory
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CGXFC4C7F27C8
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name TOP_LEVEL_ENTITY main
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set_global_assignment -name SYSTEMVERILOG_FILE ./src/main.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ./src/clk_divider.sv
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set_global_assignment -name SDC_FILE ./src/main.sdc
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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BIN
example_projects/quartus_test_prj_template_v4.7z
Executable file
BIN
example_projects/quartus_test_prj_template_v4.7z
Executable file
Binary file not shown.
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#------------------------------------------------------------------------------
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# .gitignore for Intel Quartus
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# Konstantin Pavlov, pavlovconst@gmail.com
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#------------------------------------------------------------------------------
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# INFO ------------------------------------------------------------------------
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# rename the file to ".gitignore" and place into your Quartus project directory
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#
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# junk files
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*.qws
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*_assignment_defaults.qdf
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c5_pin_model_dump.txt
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*.ipregen.rpt
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*_summary.csv
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*_early_pwr.csv
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# junk directories
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/.qsys_edit
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/db
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/incremental_db
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/greybox_tmp
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# design space explorer
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/dse
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dse1_base.qpf
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dse1_base.qsf
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*.dse.rpt
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*.archive.rpt
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/out
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#------------------------------------------------------------------------------
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# .gitignore for Intel Quartus
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# Konstantin Pavlov, pavlovconst@gmail.com
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#------------------------------------------------------------------------------
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# INFO ------------------------------------------------------------------------
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# rename the file to ".gitignore" and place into your Quartus project directory
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#
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# junk files
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*.qws
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*_assignment_defaults.qdf
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c5_pin_model_dump.txt
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*.ipregen.rpt
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*_summary.csv
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*_early_pwr.csv
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# junk directories
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/.qsys_edit
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/db
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/incremental_db
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/greybox_tmp
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# design space explorer
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/dse
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dse1_base.qpf
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dse1_base.qsf
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*.dse.rpt
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*.archive.rpt
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/out
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44
example_projects/quartus_test_prj_template_v4/clean_quartus.bat
Executable file
44
example_projects/quartus_test_prj_template_v4/clean_quartus.bat
Executable file
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@echo off
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rem ------------------------------------------------------------------------------
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rem clean_quartus.bat
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rem Konstantin Pavlov, pavlovconst@gmail.com
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rem ------------------------------------------------------------------------------
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rem Use this file as a boilerplate for your custom clean script
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rem for Quartus projects
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SET PROJ=test
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rem Common junk files
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del /s /q .\%PROJ%.qws
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del /s /q .\c5_pin_model_dump.txt
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del /s /q .\%PROJ%.ipregen.rpt
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del /s /f /q .\.qsys_edit\*
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rmdir /s /q .\.qsys_edit\
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del /s /q .\%PROJ%_assignment_defaults.qdf
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rem Compilation databases
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del /s /f /q .\db\*
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rmdir /s /q .\db\
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del /s /f /q .\incremental_db\*
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rmdir /s /q .\incremental_db\
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del /s /f /q .\greybox_tmp\*
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rmdir /s /q .\greybox_tmp\
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rem Output directory
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del /s /f /q .\out\*
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rmdir /s /q .\out\
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rem Design space explorer files
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del /s /f /q .\dse\*
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rmdir /s /q .\dse\
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del /s /q .\dse1_base.qpf
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del /s /q .\dse1_base.qsf
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del /s /q .\%PROJ%.dse.rpt
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del /s /q .\%PROJ%.archive.rpt
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rem Early power estimator files
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del /s /q .\%PROJ%_early_pwr.csv
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pause
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goto :eof
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1470
example_projects/quartus_test_prj_template_v4/debug/in_out_data.stp
Executable file
1470
example_projects/quartus_test_prj_template_v4/debug/in_out_data.stp
Executable file
File diff suppressed because it is too large
Load Diff
2
example_projects/quartus_test_prj_template_v4/ip/.qsys_edit/filters.xml
Executable file
2
example_projects/quartus_test_prj_template_v4/ip/.qsys_edit/filters.xml
Executable file
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<?xml version="1.0" encoding="UTF-8"?>
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<filters version="20.1" />
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2167
example_projects/quartus_test_prj_template_v4/ip/.qsys_edit/jtag_io.xml
Executable file
2167
example_projects/quartus_test_prj_template_v4/ip/.qsys_edit/jtag_io.xml
Executable file
File diff suppressed because it is too large
Load Diff
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst unsaved.clk_0 -pg 1 -lvl 1 -y 30
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preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.reset,(SLAVE)clk_0.clk_in_reset) 1 0 1 NJ
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)clk_0.clk_in,(SLAVE)unsaved.clk) 1 0 1 NJ
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levelinfo -pg 1 0 50 270
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levelinfo -hier unsaved 60 90 260
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14
example_projects/quartus_test_prj_template_v4/ip/.qsys_edit/preferences.xml
Executable file
14
example_projects/quartus_test_prj_template_v4/ip/.qsys_edit/preferences.xml
Executable file
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<?xml version="1.0" encoding="UTF-8"?>
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<preferences>
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<debug showDebugMenu="0" />
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<systemtable filter="All Interfaces">
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<columns>
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<connections preferredWidth="95" />
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<irq preferredWidth="34" />
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</columns>
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</systemtable>
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<library
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expandedCategories="Library/Processors and Peripherals/Peripherals,Library/Interface Protocols/Audio & Video,Library/University Program/Audio & Video/Video,Library,Library/Basic Functions/Bridges and Adaptors,Library/Interface Protocols/PCI Express,Library/Processors and Peripherals/Co-Processors,Library/Interface Protocols/PCI Express/Example Design Components,Library/Basic Functions/Simulation; Debug and Verification/Debug and Performance,Project,Library/Processors and Peripherals/Embedded Processors,Library/Interface Protocols/PCI Express/QSYS Example Designs,Library/Basic Functions/Configuration and Programming,Library/Basic Functions/Clocks; PLLs and Resets,Library/Basic Functions/Bridges and Adaptors/Streaming,Library/Interface Protocols/Ethernet,Library/University Program/Generic IO,Library/Basic Functions/Bridges and Adaptors/Memory Mapped,Library/Basic Functions/Clocks; PLLs and Resets/PLL,Library/Processors and Peripherals/Co-Processors/Nios II Custom Instructions,Library/Interface Protocols/RapidIO,Library/University Program,Library/Interface Protocols/Transceiver PHY,Library/Processors and Peripherals,Library/Basic Functions/Simulation; Debug and Verification,Library/Basic Functions,Library/Interface Protocols,Library/Basic Functions/Simulation; Debug and Verification/Simulation,Library/Interface Protocols/Ethernet/Reference Design Components,Library/University Program/Clock,Library/University Program/Audio & Video" />
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<window width="1928" height="1062" x="-4" y="-4" />
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<generation path="_PROJECT_NAME_/" block_symbol_file="0" />
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</preferences>
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217
example_projects/quartus_test_prj_template_v4/ip/jtag_io.qsys
Executable file
217
example_projects/quartus_test_prj_template_v4/ip/jtag_io.qsys
Executable file
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags=""
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categories="" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element clk_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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element in0
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{
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datum _sortIndex
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{
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value = "4";
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type = "int";
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}
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}
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element in1
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{
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datum _sortIndex
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{
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value = "5";
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type = "int";
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}
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}
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element master_0
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{
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datum _sortIndex
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{
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value = "1";
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type = "int";
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}
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}
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element out0
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{
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datum _sortIndex
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{
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value = "2";
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type = "int";
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}
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}
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element out1
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{
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datum _sortIndex
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{
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value = "3";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="device" value="5CSEBA6U23I7" />
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<parameter name="deviceFamily" value="Cyclone V" />
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<parameter name="deviceSpeedGrade" value="7" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="false" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
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<interface
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name="in0"
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internal="in0.external_connection"
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type="conduit"
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dir="end" />
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<interface
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name="in1"
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internal="in1.external_connection"
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type="conduit"
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dir="end" />
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<interface
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name="out0"
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internal="out0.external_connection"
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type="conduit"
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dir="end" />
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<interface
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name="out1"
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internal="out1.external_connection"
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type="conduit"
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dir="end" />
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<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
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<module name="clk_0" kind="clock_source" version="20.1" enabled="1">
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<parameter name="clockFrequency" value="50000000" />
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<parameter name="clockFrequencyKnown" value="true" />
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<parameter name="inputClockFrequency" value="0" />
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<parameter name="resetSynchronousEdges" value="NONE" />
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</module>
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<module name="in0" kind="altera_avalon_pio" version="20.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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<parameter name="clockRate" value="50000000" />
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<parameter name="direction" value="Input" />
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<parameter name="edgeType" value="RISING" />
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<parameter name="generateIRQ" value="false" />
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<parameter name="irqType" value="LEVEL" />
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<parameter name="resetValue" value="0" />
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<parameter name="simDoTestBenchWiring" value="false" />
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module name="in1" kind="altera_avalon_pio" version="20.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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<parameter name="clockRate" value="50000000" />
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<parameter name="direction" value="Input" />
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<parameter name="edgeType" value="RISING" />
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<parameter name="generateIRQ" value="false" />
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<parameter name="irqType" value="LEVEL" />
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<parameter name="resetValue" value="0" />
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<parameter name="simDoTestBenchWiring" value="false" />
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module
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name="master_0"
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kind="altera_jtag_avalon_master"
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version="20.1"
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enabled="1">
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<parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
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<parameter name="COMPONENT_CLOCK" value="0" />
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<parameter name="FAST_VER" value="0" />
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<parameter name="FIFO_DEPTHS" value="2" />
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<parameter name="PLI_PORT" value="50000" />
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<parameter name="USE_PLI" value="0" />
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</module>
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<module name="out0" kind="altera_avalon_pio" version="20.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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<parameter name="captureEdge" value="false" />
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<parameter name="clockRate" value="50000000" />
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<parameter name="direction" value="Output" />
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<parameter name="edgeType" value="RISING" />
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<parameter name="generateIRQ" value="false" />
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<parameter name="irqType" value="LEVEL" />
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<parameter name="resetValue" value="0" />
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<parameter name="simDoTestBenchWiring" value="false" />
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
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<module name="out1" kind="altera_avalon_pio" version="20.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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||||
<parameter name="captureEdge" value="false" />
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<parameter name="clockRate" value="50000000" />
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<parameter name="direction" value="Output" />
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<parameter name="edgeType" value="RISING" />
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<parameter name="generateIRQ" value="false" />
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<parameter name="irqType" value="LEVEL" />
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<parameter name="resetValue" value="0" />
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<parameter name="simDoTestBenchWiring" value="false" />
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<parameter name="simDrivenValue" value="0" />
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<parameter name="width" value="32" />
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</module>
|
||||
<connection kind="avalon" version="20.1" start="master_0.master" end="out0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="avalon" version="20.1" start="master_0.master" end="out1.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0010" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="avalon" version="20.1" start="master_0.master" end="in0.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0020" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="avalon" version="20.1" start="master_0.master" end="in1.s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0030" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="clock" version="20.1" start="clk_0.clk" end="out0.clk" />
|
||||
<connection kind="clock" version="20.1" start="clk_0.clk" end="master_0.clk" />
|
||||
<connection kind="clock" version="20.1" start="clk_0.clk" end="out1.clk" />
|
||||
<connection kind="clock" version="20.1" start="clk_0.clk" end="in0.clk" />
|
||||
<connection kind="clock" version="20.1" start="clk_0.clk" end="in1.clk" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="20.1"
|
||||
start="clk_0.clk_reset"
|
||||
end="master_0.clk_reset" />
|
||||
<connection kind="reset" version="20.1" start="clk_0.clk_reset" end="out0.reset" />
|
||||
<connection kind="reset" version="20.1" start="clk_0.clk_reset" end="out1.reset" />
|
||||
<connection kind="reset" version="20.1" start="clk_0.clk_reset" end="in0.reset" />
|
||||
<connection kind="reset" version="20.1" start="clk_0.clk_reset" end="in1.reset" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
</system>
|
||||
4690
example_projects/quartus_test_prj_template_v4/ip/jtag_io.sopcinfo
Executable file
4690
example_projects/quartus_test_prj_template_v4/ip/jtag_io.sopcinfo
Executable file
File diff suppressed because it is too large
Load Diff
104
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io.bsf
Executable file
104
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io.bsf
Executable file
@ -0,0 +1,104 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 256 304)
|
||||
(text "jtag_io" (rect 109 -1 133 11)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 288 20 300)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
|
||||
(text "reset_reset_n" (rect 4 61 82 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 96 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
|
||||
(text "clk_clk" (rect 4 101 46 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 96 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 232)
|
||||
(input)
|
||||
(text "in0_export[31..0]" (rect 0 0 64 12)(font "Arial" (font_size 8)))
|
||||
(text "in0_export[31..0]" (rect 4 221 106 232)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 232)(pt 96 232)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 272)
|
||||
(input)
|
||||
(text "in1_export[31..0]" (rect 0 0 63 12)(font "Arial" (font_size 8)))
|
||||
(text "in1_export[31..0]" (rect 4 261 106 272)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 272)(pt 96 272)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 152)
|
||||
(output)
|
||||
(text "out0_export[31..0]" (rect 0 0 70 12)(font "Arial" (font_size 8)))
|
||||
(text "out0_export[31..0]" (rect 4 141 112 152)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 152)(pt 96 152)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 192)
|
||||
(output)
|
||||
(text "out1_export[31..0]" (rect 0 0 69 12)(font "Arial" (font_size 8)))
|
||||
(text "out1_export[31..0]" (rect 4 181 112 192)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 192)(pt 96 192)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "reset" (rect 67 43 164 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 101 67 244 144)(font "Arial" (color 0 0 0)))
|
||||
(text "clk" (rect 81 83 180 179)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 101 107 220 224)(font "Arial" (color 0 0 0)))
|
||||
(text "out0" (rect 72 123 168 259)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 101 147 238 304)(font "Arial" (color 0 0 0)))
|
||||
(text "out1" (rect 74 163 172 339)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 101 187 238 384)(font "Arial" (color 0 0 0)))
|
||||
(text "in0" (rect 80 203 178 419)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 101 227 238 464)(font "Arial" (color 0 0 0)))
|
||||
(text "in1" (rect 82 243 182 499)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 101 267 238 544)(font "Arial" (color 0 0 0)))
|
||||
(text " system " (rect 221 288 490 586)(font "Arial" ))
|
||||
(line (pt 96 32)(pt 160 32)(line_width 1))
|
||||
(line (pt 160 32)(pt 160 288)(line_width 1))
|
||||
(line (pt 96 288)(pt 160 288)(line_width 1))
|
||||
(line (pt 96 32)(pt 96 288)(line_width 1))
|
||||
(line (pt 97 52)(pt 97 76)(line_width 1))
|
||||
(line (pt 98 52)(pt 98 76)(line_width 1))
|
||||
(line (pt 97 92)(pt 97 116)(line_width 1))
|
||||
(line (pt 98 92)(pt 98 116)(line_width 1))
|
||||
(line (pt 97 132)(pt 97 156)(line_width 1))
|
||||
(line (pt 98 132)(pt 98 156)(line_width 1))
|
||||
(line (pt 97 172)(pt 97 196)(line_width 1))
|
||||
(line (pt 98 172)(pt 98 196)(line_width 1))
|
||||
(line (pt 97 212)(pt 97 236)(line_width 1))
|
||||
(line (pt 98 212)(pt 98 236)(line_width 1))
|
||||
(line (pt 97 252)(pt 97 276)(line_width 1))
|
||||
(line (pt 98 252)(pt 98 276)(line_width 1))
|
||||
(line (pt 0 0)(pt 256 0)(line_width 1))
|
||||
(line (pt 256 0)(pt 256 304)(line_width 1))
|
||||
(line (pt 0 304)(pt 256 304)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 304)(line_width 1))
|
||||
)
|
||||
)
|
||||
11
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io.cmp
Executable file
11
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io.cmp
Executable file
@ -0,0 +1,11 @@
|
||||
component jtag_io is
|
||||
port (
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
in0_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
|
||||
in1_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
|
||||
out0_export : out std_logic_vector(31 downto 0); -- export
|
||||
out1_export : out std_logic_vector(31 downto 0); -- export
|
||||
reset_reset_n : in std_logic := 'X' -- reset_n
|
||||
);
|
||||
end component jtag_io;
|
||||
|
||||
1152
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io.html
Executable file
1152
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io.html
Executable file
File diff suppressed because it is too large
Load Diff
2497
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io.xml
Executable file
2497
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io.xml
Executable file
File diff suppressed because one or more lines are too long
16
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io_bb.v
Executable file
16
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io_bb.v
Executable file
@ -0,0 +1,16 @@
|
||||
|
||||
module jtag_io (
|
||||
reset_reset_n,
|
||||
clk_clk,
|
||||
out0_export,
|
||||
out1_export,
|
||||
in0_export,
|
||||
in1_export);
|
||||
|
||||
input reset_reset_n;
|
||||
input clk_clk;
|
||||
output [31:0] out0_export;
|
||||
output [31:0] out1_export;
|
||||
input [31:0] in0_export;
|
||||
input [31:0] in1_export;
|
||||
endmodule
|
||||
@ -0,0 +1,65 @@
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate J:\basic_verilog\example_projects\quartus_test_prj_template_v4\ip\jtag_io.qsys --synthesis=VERILOG --output-directory=J:\basic_verilog\example_projects\quartus_test_prj_template_v4\ip\jtag_io\synthesis --family="Cyclone V" --part=5CSEBA6U23I7
|
||||
Progress: Loading ip/jtag_io.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding clk_0 [clock_source 20.1]
|
||||
Progress: Parameterizing module clk_0
|
||||
Progress: Adding in0 [altera_avalon_pio 20.1]
|
||||
Progress: Parameterizing module in0
|
||||
Progress: Adding in1 [altera_avalon_pio 20.1]
|
||||
Progress: Parameterizing module in1
|
||||
Progress: Adding master_0 [altera_jtag_avalon_master 20.1]
|
||||
Progress: Parameterizing module master_0
|
||||
Progress: Adding out0 [altera_avalon_pio 20.1]
|
||||
Progress: Parameterizing module out0
|
||||
Progress: Adding out1 [altera_avalon_pio 20.1]
|
||||
Progress: Parameterizing module out1
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: jtag_io.in0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: jtag_io.in1: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: jtag_io: Generating jtag_io "jtag_io" for QUARTUS_SYNTH
|
||||
Info: in0: Starting RTL generation for module 'jtag_io_in0'
|
||||
Info: in0: Generation command is [exec C:/intelfpga_lite/20.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/20.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/20.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/20.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/20.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/20.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/20.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=jtag_io_in0 --dir=C:/Users/Pavlov/AppData/Local/Temp/alt9083_1757229078663084904.dir/0002_in0_gen/ --quartus_dir=C:/intelfpga_lite/20.1/quartus --verilog --config=C:/Users/Pavlov/AppData/Local/Temp/alt9083_1757229078663084904.dir/0002_in0_gen//jtag_io_in0_component_configuration.pl --do_build_sim=0 ]
|
||||
Info: in0: Done RTL generation for module 'jtag_io_in0'
|
||||
Info: in0: "jtag_io" instantiated altera_avalon_pio "in0"
|
||||
Info: master_0: "jtag_io" instantiated altera_jtag_avalon_master "master_0"
|
||||
Info: out0: Starting RTL generation for module 'jtag_io_out0'
|
||||
Info: out0: Generation command is [exec C:/intelfpga_lite/20.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/20.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/20.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/20.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/20.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/20.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/20.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=jtag_io_out0 --dir=C:/Users/Pavlov/AppData/Local/Temp/alt9083_1757229078663084904.dir/0003_out0_gen/ --quartus_dir=C:/intelfpga_lite/20.1/quartus --verilog --config=C:/Users/Pavlov/AppData/Local/Temp/alt9083_1757229078663084904.dir/0003_out0_gen//jtag_io_out0_component_configuration.pl --do_build_sim=0 ]
|
||||
Info: out0: Done RTL generation for module 'jtag_io_out0'
|
||||
Info: out0: "jtag_io" instantiated altera_avalon_pio "out0"
|
||||
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
|
||||
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
|
||||
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
|
||||
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
|
||||
Info: mm_interconnect_0: "jtag_io" instantiated altera_mm_interconnect "mm_interconnect_0"
|
||||
Info: rst_controller: "jtag_io" instantiated altera_reset_controller "rst_controller"
|
||||
Info: jtag_phy_embedded_in_jtag_master: "master_0" instantiated altera_jtag_dc_streaming "jtag_phy_embedded_in_jtag_master"
|
||||
Info: timing_adt: "master_0" instantiated timing_adapter "timing_adt"
|
||||
Info: fifo: "master_0" instantiated altera_avalon_sc_fifo "fifo"
|
||||
Info: b2p: "master_0" instantiated altera_avalon_st_bytes_to_packets "b2p"
|
||||
Info: p2b: "master_0" instantiated altera_avalon_st_packets_to_bytes "p2b"
|
||||
Info: transacto: "master_0" instantiated altera_avalon_packets_to_master "transacto"
|
||||
Info: b2p_adapter: "master_0" instantiated channel_adapter "b2p_adapter"
|
||||
Info: p2b_adapter: "master_0" instantiated channel_adapter "p2b_adapter"
|
||||
Info: master_0_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "master_0_master_translator"
|
||||
Info: out0_s1_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "out0_s1_translator"
|
||||
Info: master_0_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "master_0_master_agent"
|
||||
Info: out0_s1_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "out0_s1_agent"
|
||||
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
|
||||
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
|
||||
Info: master_0_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "master_0_master_limiter"
|
||||
Info: Reusing file J:/basic_verilog/example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/altera_avalon_sc_fifo.v
|
||||
Info: Reusing file J:/basic_verilog/example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/altera_avalon_st_pipeline_base.v
|
||||
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
|
||||
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
|
||||
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
|
||||
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
|
||||
Info: Reusing file J:/basic_verilog/example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/submodules/altera_merlin_arbitrator.sv
|
||||
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
|
||||
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
|
||||
Info: jtag_io: Done "jtag_io" with 27 modules, 42 files
|
||||
Info: qsys-generate succeeded.
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
9
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io_inst.v
Executable file
9
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io_inst.v
Executable file
@ -0,0 +1,9 @@
|
||||
jtag_io u0 (
|
||||
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
|
||||
.clk_clk (<connected-to-clk_clk>), // clk.clk
|
||||
.out0_export (<connected-to-out0_export>), // out0.export
|
||||
.out1_export (<connected-to-out1_export>), // out1.export
|
||||
.in0_export (<connected-to-in0_export>), // in0.export
|
||||
.in1_export (<connected-to-in1_export>) // in1.export
|
||||
);
|
||||
|
||||
21
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io_inst.vhd
Executable file
21
example_projects/quartus_test_prj_template_v4/ip/jtag_io/jtag_io_inst.vhd
Executable file
@ -0,0 +1,21 @@
|
||||
component jtag_io is
|
||||
port (
|
||||
reset_reset_n : in std_logic := 'X'; -- reset_n
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
out0_export : out std_logic_vector(31 downto 0); -- export
|
||||
out1_export : out std_logic_vector(31 downto 0); -- export
|
||||
in0_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
|
||||
in1_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
|
||||
);
|
||||
end component jtag_io;
|
||||
|
||||
u0 : component jtag_io
|
||||
port map (
|
||||
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
|
||||
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
|
||||
out0_export => CONNECTED_TO_out0_export, -- out0.export
|
||||
out1_export => CONNECTED_TO_out1_export, -- out1.export
|
||||
in0_export => CONNECTED_TO_in0_export, -- in0.export
|
||||
in1_export => CONNECTED_TO_in1_export -- in1.export
|
||||
);
|
||||
|
||||
7130
example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/jtag_io.debuginfo
Executable file
7130
example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/jtag_io.debuginfo
Executable file
File diff suppressed because one or more lines are too long
786
example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/jtag_io.qip
Executable file
786
example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/jtag_io.qip
Executable file
@ -0,0 +1,786 @@
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_TOOL_NAME "Qsys"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -library "jtag_io" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../jtag_io.sopcinfo"]
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name SLD_INFO "QSYS_NAME jtag_io HAS_SOPCINFO 1 GENERATION_ID 1648805399"
|
||||
set_global_assignment -library "jtag_io" -name MISC_FILE [file join $::quartus(qip_path) "../jtag_io.cmp"]
|
||||
set_global_assignment -library "jtag_io" -name SLD_FILE [file join $::quartus(qip_path) "jtag_io.regmap"]
|
||||
set_global_assignment -library "jtag_io" -name SLD_FILE [file join $::quartus(qip_path) "jtag_io.debuginfo"]
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_QSYS_MODE "SYSTEM"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "jtag_io" -name MISC_FILE [file join $::quartus(qip_path) "../../jtag_io.qsys"]
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pbw=="
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "anRhZ19pbw=="
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY0ODgwNTM5OQ==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNTRUJBNlUyM0k3::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
|
||||
set_global_assignment -entity "jtag_io" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX3Jlc2V0X2NvbnRyb2xsZXI="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIFJlc2V0IENvbnRyb2xsZXI="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "Rm9yIHN5c3RlbXMgd2l0aCBtdWx0aXBsZSByZXNldCBpbnB1dHMsIHRoZSBNZXJsaW4gUmVzZXQgQ29udHJvbGxlciBPUnMgYWxsIHJlc2V0IGlucHV0cyBhbmQgZ2VuZXJhdGVzIGEgc2luZ2xlIHJlc2V0IG91dHB1dC4="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TlVNX1JFU0VUX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIGlucHV0cw=="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "T1VUUFVUX1JFU0VUX1NZTkNfRURHRVM=::ZGVhc3NlcnQ=::T3V0cHV0IFJlc2V0IFN5bmNocm9ub3VzIEVkZ2Vz"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1lOQ19ERVBUSA==::Mg==::U3luY2hyb25pemVyIGRlcHRo"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRVUVTVF9QUkVTRU5U::MA==::UmVzZXQgcmVxdWVzdCBsb2dpYyBlbmFibGU="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX1dBSVRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCB3YWl0IHRpbWU="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUlOX1JTVF9BU1NFUlRJT05fVElNRQ==::Mw==::TWluaW11bSByZXNldCBhc3NlcnRpb24gdGltZQ=="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX0VBUkxZX0RTUlRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCBkZWFzc2VydCB0aW1pbmc="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4w::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjA="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4x::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4y::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjI="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4z::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjM="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU40::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjQ="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU41::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjU="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU42::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjY="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU43::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjc="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU44::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjg="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU45::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjk="
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEw"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEx"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMg==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEy"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMw==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEz"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE0"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE1"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU5QVVQ=::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcmVzZXRfaW5wdXRz"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QURBUFRfUkVTRVRfUkVRVUVTVA==::MA==::T25seSBhZGFwdCBvbmx5IHJlc2V0IHJlcXVlc3Q="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TU0gSW50ZXJjb25uZWN0"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_INTERNAL "On"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "TU0gSW50ZXJjb25uZWN0"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNTRUJBNlUyM0k3::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMF9hdmFsb25fc3RfYWRhcHRlcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEFkYXB0ZXI="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QWRhcHQgbWlzbWF0Y2hlZCBBdmFsb24tU1QgZW5kcG9pbnRz"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MzQ=::U3ltYm9sIFdpZHRo"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::MA==::VXNlIFBhY2tldA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5EYXRhV2lkdGg=::MzQ=::U291cmNlIERhdGEgV2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::U291cmNlIE1heCBDaGFubmVs"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::U291cmNlIENoYW5uZWwgUG9ydCBXaWR0aA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::U291cmNlIEVycm9yIFBvcnQgV2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::MA==::U291cmNlIFVzZXMgRW1wdHkgUG9ydA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5FbXB0eVdpZHRo::MQ==::U291cmNlIEVtcHR5IFBvcnQgV2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::MQ==::U291cmNlIFVzZXMgVmFsaWQgUG9ydA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::MQ==::U291cmNlIFVzZXMgUmVhZHkgUG9ydA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::U291cmNlIFJlYWR5IExhdGVuY3k="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0RGF0YVdpZHRo::MzQ=::U2luayBEYXRhIFdpZHRo"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::U2luayBNYXggQ2hhbm5lbA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::U2luayBDaGFubmVsIFBvcnQgV2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::U2luayBFcnJvciBQb3J0IFdpZHRo"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0VXNlRW1wdHlQb3J0::MA==::U2luayBVc2VzIEVtcHR5IFBvcnQ="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0RW1wdHlXaWR0aA==::MQ==::U2luayBFbXB0eSBQb3J0IFdpZHRo"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::MQ==::U2luayBVc2VzIFZhbGlkIFBvcnQ="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::MQ==::U2luayBVc2VzIFJlYWR5IFBvcnQ="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::U2luayBSZWFkeSBMYXRlbmN5"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNTRUJBNlUyM0k3::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMF9hdmFsb25fc3RfYWRhcHRlcl9lcnJvcl9hZGFwdGVyXzA="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEVycm9yIEFkYXB0ZXI="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::MzQ=::RGF0YSBCaXRzIFBlciBTeW1ib2w="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::ZmFsc2U=::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0RXJyb3JXaWR0aA==::MQ==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMF9yc3BfbXV4"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::NA==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MA==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NzI=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::bm8tYXJi::QXJiaXRyYXRpb24gc2NoZW1l"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MSwxLDEsMQ==::QXJiaXRyYXRpb24gc2hhcmVz"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMF9yc3BfZGVtdXg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::UGFja2V0IGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::MQ==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::MQ==::VmFsaWQgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMF9jbWRfbXV4"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBNdWx0aXBsZXhlcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QXJiaXRyYXRlcyBiZXR3ZWVuIHJlcXVlc3RpbmcgbWFzdGVycyB1c2luZyBhbiBlcXVhbCBzaGFyZSwgcm91bmQtcm9iaW4gYWxnb3JpdGhtLiBUaGUgYXJiaXRyYXRpb24gc2NoZW1lIGNhbiBiZSBjaGFuZ2VkIHRvIHdlaWdodGVkIHJvdW5kLXJvYmluIGJ5IHNwZWNpZnlpbmcgYSByZWxhdGl2ZSBudW1iZXIgb2YgYXJiaXRyYXRpb24gc2hhcmVzIHRvIHRoZSBtYXN0ZXJzIHRoYXQgYWNjZXNzIGEgcGFydGljdWxhciBzbGF2ZS4="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TlVNX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIG11eCBpbnB1dHM="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVfQVJC::MQ==::UGlwZWxpbmVkIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0VYVEVSTkFMX0FSQg==::MA==::VXNlIGV4dGVybmFsIGFyYml0cmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NzI=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0NIRU1F::cm91bmQtcm9iaW4=::QXJiaXRyYXRpb24gc2NoZW1l"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVJCSVRSQVRJT05fU0hBUkVT::MQ==::QXJiaXRyYXRpb24gc2hhcmVz"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMF9jbWRfZGVtdXg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBEZW11bHRpcGxleGVy"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjaGFubmVsaXplZCBkYXRhIG9uIGl0cyBzaW5rIGludGVyZmFjZSBhbmQgdHJhbnNtaXRzIHRoZSBkYXRhIG9uIG9uZSBvZiBpdHMgc291cmNlIGludGVyZmFjZXMu"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::UGFja2V0IGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TlVNX09VVFBVVFM=::NA==::TnVtYmVyIG9mIGRlbXV4IG91dHB1dHM="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::NA==::VmFsaWQgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl90cmFmZmljX2xpbWl0ZXI="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBUcmFmZmljIExpbWl0ZXI="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "RW5zdXJlcyB0aGUgcmVzcG9uc2VzIGFycml2ZSBpbiBvcmRlciwgc2ltcGxpZnlpbmcgdGhlIFFzeXMgcmVzcG9uc2UgbmV0d29yay4="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::OTA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODk=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::ODg=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::NzY=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzQ=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::Njk=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9I::OTE=::UGFja2V0IHRocmVhZCBJRCBmaWVsZCBpbmRleCBNU0I="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9M::OTE=::UGFja2V0IHRocmVhZCBJRCBmaWVsZCBpbmRleCBMU0I="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUX0xFTkdUSA==::MQ==::TWF4aW11bSBidXJzdCBsZW5ndGg="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUFYX09VVFNUQU5ESU5HX1JFU1BPTlNFUw==::MQ==::TWF4aW11bSBvdXRzdGFuZGluZyByZXNwb25zZXM="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UElQRUxJTkVE::MA==::UGlwZWxpbmU="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VkFMSURfV0lEVEg=::NA==::VmFsaWQgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RU5GT1JDRV9PUkRFUg==::MQ==::RW5mb3JjZSBvcmRlcg=="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UFJFVkVOVF9IQVpBUkRT::MA==::UHJldmVudCBoYXphcmRz"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1VQUE9SVFNfUE9TVEVEX1dSSVRFUw==::MQ==::SGF6YXJkIHByZXZlbnRpb246IHBvc3RlZCB3cml0ZSBzdXBwb3J0"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1VQUE9SVFNfTk9OUE9TVEVEX1dSSVRFUw==::MA==::SGF6YXJkIHByZXZlbnRpb246IG5vbi1wb3N0ZWQgd3JpdGUgc3VwcG9ydA=="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UkVPUkRFUg==::MA==::RW5hYmxlIHJlb3JkZXIgYnVmZmVy"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMF9yb3V0ZXJfMDAx"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MA==::RGVzdGluYXRpb24gSUQ="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MQ==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgw::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MQ==::Tm9uLXNlY3VyZWQgdGFncw=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::Njc=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::OTA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODk=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NzE=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MDoxOjB4MDoweDA6Ym90aDoxOjA6MDox::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MQ==::RGVjb2RlciB0eXBl"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::MA==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tbV9pbnRlcmNvbm5lY3RfMF9yb3V0ZXI="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "TWVtb3J5IE1hcHBlZCBSb3V0ZXI="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "Um91dGVzIGNvbW1hbmQgcGFja2V0cyBmcm9tIHRoZSBtYXN0ZXIgdG8gdGhlIHNsYXZlIGFuZCByZXNwb25zZSBwYWNrZXRzIGZyb20gdGhlIHNsYXZlIHRvIHRoZSBtYXN0ZXIu"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVTVElOQVRJT05fSUQ=::MiwzLDAsMQ==::RGVzdGluYXRpb24gSUQ="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9JRA==::MDAwMSwwMDEwLDAxMDAsMTAwMA==::QmluYXJ5IENoYW5uZWwgU3RyaW5n"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VFlQRV9PRl9UUkFOU0FDVElPTg==::Ym90aCxib3RoLHJlYWQscmVhZA==::VHlwZSBvZiBUcmFuc2FjdGlvbg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RBUlRfQUREUkVTUw==::MHgwLDB4MTAsMHgyMCwweDMw::U3RhcnQgYWRkcmVzc2VzIChpbmNsdXNpdmUp"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RU5EX0FERFJFU1M=::MHgxMCwweDIwLDB4MzAsMHg0MA==::RW5kIGFkZHJlc3NlcyAoZXhjbHVzaXZlKQ=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Tk9OX1NFQ1VSRURfVEFH::MSwxLDEsMQ==::Tm9uLXNlY3VyZWQgdGFncw=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9QQUlSUw==::MCwwLDAsMA==::TnVtYmVyIG9mIHNlY3VyZWQgcmFuZ2UgcGFpcnM="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U0VDVVJFRF9SQU5HRV9MSVNU::MCwwLDAsMA==::U2VjdXJlZCByYW5nZSBwYWlycw=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::Njc=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTQ=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTI=::UGFja2V0IEFYSSBwcm90ZWN0aW9uIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::OTA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODk=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NzE=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U0xBVkVTX0lORk8=::MjowMDAxOjB4MDoweDEwOmJvdGg6MTowOjA6MSwzOjAwMTA6MHgxMDoweDIwOmJvdGg6MTowOjA6MSwwOjAxMDA6MHgyMDoweDMwOnJlYWQ6MTowOjA6MSwxOjEwMDA6MHgzMDoweDQwOnJlYWQ6MTowOjA6MQ==::U0xBVkVTX0lORk8="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVDT0RFUl9UWVBF::MA==::RGVjb2RlciB0eXBl"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9DSEFOTkVM::MA==::RGVmYXVsdCBjaGFubmVs"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9XUl9DSEFOTkVM::LTE=::RGVmYXVsdCB3ciBjaGFubmVs"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9SRF9DSEFOTkVM::LTE=::RGVmYXVsdCByZCBjaGFubmVs"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "REVGQVVMVF9ERVNUSUQ=::Mg==::RGVmYXVsdCBkZXN0aW5hdGlvbiBJRA=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVNT1JZX0FMSUFTSU5HX0RFQ09ERQ==::MA==::TWVtb3J5IEFsaWFzaW5nIERlY29kZQ=="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zY19maWZv"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFNpbmdsZSBDbG9jayBGSUZP"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1lNQk9MU19QRVJfQkVBVA==::MQ==::U3ltYm9scyBwZXIgYmVhdA=="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QklUU19QRVJfU1lNQk9M::OA==::Qml0cyBwZXIgc3ltYm9s"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RklGT19ERVBUSA==::NjQ=::RklGTyBkZXB0aA=="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSA==::MA==::Q2hhbm5lbCB3aWR0aA=="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RVJST1JfV0lEVEg=::MA==::RXJyb3Igd2lkdGg="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1BBQ0tFVFM=::MA==::VXNlIHBhY2tldHM="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0ZJTExfTEVWRUw=::MA==::VXNlIGZpbGwgbGV2ZWw="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RU1QVFlfTEFURU5DWQ==::Mw==::TGF0ZW5jeQ=="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX01FTU9SWV9CTE9DS1M=::MQ==::VXNlIG1lbW9yeSBibG9ja3M="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1NUT1JFX0ZPUldBUkQ=::MA==::VXNlIHN0b3JlIGFuZCBmb3J3YXJk"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0FMTU9TVF9GVUxMX0lG::MA==::VXNlIGFsbW9zdCBmdWxsIHN0YXR1cw=="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0FMTU9TVF9FTVBUWV9JRg==::MA==::VXNlIGFsbW9zdCBlbXB0eSBzdGF0dXM="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0VYUExJQ0lUX01BWENIQU5ORUw=::ZmFsc2U=::RW5hYmxlIGV4cGxpY2l0IG1heENoYW5uZWw="
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RVhQTElDSVRfTUFYQ0hBTk5FTA==::MA==::RXhwbGljaXQgbWF4Q2hhbm5lbA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9zbGF2ZV9hZ2VudA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIFNsYXZlIEFnZW50"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QWNjZXB0cyBjb21tYW5kIHBhY2tldHMgYW5kIGlzc3VlcyB0aGUgcmVzdWx0aW5nIHRyYW5zYWN0aW9ucyB0byB0aGUgQXZhbG9uIGludGVyZmFjZS4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgZXhwbGFuYXRpb25zIG9mIHRoZSBidXJzdGluZyBwcm9wZXJ0aWVzLg=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0g=::MTAz::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0w=::MTAx::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19I::MTAw::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19M::OTk=::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfSA==::ODA=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfTA==::Nzg=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NzI=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JFR0lOX0JVUlNU::ODU=::UGFja2V0IGJlZ2luIGJ1cnN0IGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTQ=::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTI=::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9I::Nzc=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9M::Nzc=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::NzY=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzQ=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::Njc=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::Njg=::UGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::Njk=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NzE=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfSA==::MzE=::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfTA==::MA==::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::ODg=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::OTA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODk=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1NZTUJPTF9X::OA==::UGFja2V0IHN5bWJvbCB3aWR0aA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfU1lNQk9MUw==::MA==::YnVyc3Rjb3VudFN5bWJvbHM="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZTX0JVUlNUQ09VTlRfVw==::Mw==::YnVyc3Rjb3VudCB3aWR0aA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1VQUFJFU1NfMF9CWVRFRU5fQ01E::MA==::U3VwcHJlc3MgMC1ieXRlZW5hYmxlIHRyYW5zYWN0aW9ucw=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UFJFVkVOVF9GSUZPX09WRVJGTE9X::MQ==::UHJldmVudCBGSUZPIG92ZXJmbG93"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUFYX0JZVEVfQ05U::NA==::TWF4aW11bSBieXRlLWNvdW50IHZhbHVl"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUFYX0JVUlNUV1JBUA==::MQ==::TWF4aW11bSBidXJzdHdyYXAgdmFsdWU="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "SUQ=::Mg==::U2xhdmUgSUQ="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U="
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RUNDX0VOQUJMRQ==::MA==::RUNDX0VOQUJMRQ=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9tYXN0ZXJfYWdlbnQ="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIE1hc3RlciBBZ2VudA=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "VHJhbnNsYXRlcyBBdmFsb24tTU0gbWFzdGVyIHRyYW5zYWN0aW9ucyBpbnRvIFFzeXMgY29tbWFuZCBwYWNrZXRzIGFuZCB0cmFuc2xhdGVzIHRoZSBRc3lzIEF2YWxvbi1NTSBzbGF2ZSByZXNwb25zZSBwYWNrZXRzIGludG8gQXZhbG9uLU1NIHJlc3BvbnNlcy4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgYW4gZXhwbGFuYXRpb24gb2YgYnVyc3RpbmcgYmVoYXZpb3Iu"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0g=::MTAz::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX09SSV9CVVJTVF9TSVpFX0w=::MTAx::UGFja2V0IG9yaWdpbmFsIGJ1cnN0IHNpemUgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19I::MTAw::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1JFU1BPTlNFX1NUQVRVU19M::OTk=::UGFja2V0IHJlc3BvbnNlIHN0YXR1cyBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1FPU19I::ODY=::UGFja2V0IHFvcyBzaWRlYmFuZCBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1FPU19M::ODY=::UGFja2V0IHFvcyBzaWRlYmFuZCBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfU0lERUJBTkRfSA==::ODQ=::UGFja2V0IGRhdGEgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfU0lERUJBTkRfTA==::ODQ=::UGFja2V0IGRhdGEgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfU0lERUJBTkRfSA==::ODM=::UGFja2V0IGFkZHJlc3Mgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfU0lERUJBTkRfTA==::ODM=::UGFja2V0IGFkZHJlc3Mgc2lkZWJhbmQgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfSA==::ODI=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1RZUEVfTA==::ODE=::UGFja2V0IGJ1cnN0dHlwZSBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0NBQ0hFX0g=::OTg=::UGFja2V0IGNhY2hlIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0NBQ0hFX0w=::OTU=::UGFja2V0IGNhY2hlIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9I::OTE=::UGFja2V0IHRocmVhZCBpZCBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RIUkVBRF9JRF9M::OTE=::UGFja2V0IHRocmVhZCBpZCBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfSA==::ODA=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUX1NJWkVfTA==::Nzg=::UGFja2V0IGJ1cnN0c2l6ZSBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0VYQ0xVU0lWRQ==::NzM=::UGFja2V0IGV4Y2x1c2l2ZSB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0xPQ0s=::NzI=::UGFja2V0IGxvY2sgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JFR0lOX0JVUlNU::ODU=::UGFja2V0IGJlZ2luIGJ1cnN0IGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fSA==::OTQ=::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1BST1RFQ1RJT05fTA==::OTI=::UGFja2V0IHByb3RlY3Rpb24gZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9I::Nzc=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JVUlNUV1JBUF9M::Nzc=::UGFja2V0IGJ1cnN0d3JhcCBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0g=::NzY=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVfQ05UX0w=::NzQ=::UGFja2V0IGJ5dGUgY291bnQgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfSA==::Njc=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0FERFJfTA==::MzY=::UGFja2V0IGFkZHJlc3MgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX0NPTVBSRVNTRURfUkVBRA==::Njg=::UGFja2V0IGNvbXByZXNzZWQgcmVhZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1BPU1RFRA==::Njk=::UGFja2V0IHBvc3RlZCB0cmFuc2FjdGlvbiBmaWVsZCBpbmRleA=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1dSSVRF::NzA=::UGFja2V0IHdyaXRlIHRyYW5zYWN0aW9uIGZpZWxkIGluZGV4"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1RSQU5TX1JFQUQ=::NzE=::UGFja2V0IHJlYWQgdHJhbnNhY3Rpb24gZmllbGQgaW5kZXg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfSA==::MzE=::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RBVEFfTA==::MA==::UGFja2V0IGRhdGEgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9I::MzU=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBoaWdo"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0JZVEVFTl9M::MzI=::UGFja2V0IGJ5dGVlbmFibGUgZmllbGQgaW5kZXggLSBsb3c="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9I::ODg=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGhpZ2g="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX1NSQ19JRF9M::ODc=::UGFja2V0IHNvdXJjZSBpZCBmaWVsZCBpbmRleCAtIGxvdw=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfSA==::OTA=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gaGlnaA=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UEtUX0RFU1RfSURfTA==::ODk=::UGFja2V0IGRlc3RpbmF0aW9uIGlkIGZpZWxkIGluZGV4IC0gbG93"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfREFUQV9X::MTA0::U3RyZWFtaW5nIGRhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1RfQ0hBTk5FTF9X::NA==::U3RyZWFtaW5nIGNoYW5uZWwgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::Mw==::QXZhbG9uLU1NIGJ1cnN0Y291bnQgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MA==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUVSTElOX1BBQ0tFVF9GT1JNQVQ=::b3JpX2J1cnN0X3NpemUoMTAzOjEwMSkgcmVzcG9uc2Vfc3RhdHVzKDEwMDo5OSkgY2FjaGUoOTg6OTUpIHByb3RlY3Rpb24oOTQ6OTIpIHRocmVhZF9pZCg5MSkgZGVzdF9pZCg5MDo4OSkgc3JjX2lkKDg4Ojg3KSBxb3MoODYpIGJlZ2luX2J1cnN0KDg1KSBkYXRhX3NpZGViYW5kKDg0KSBhZGRyX3NpZGViYW5kKDgzKSBidXJzdF90eXBlKDgyOjgxKSBidXJzdF9zaXplKDgwOjc4KSBidXJzdHdyYXAoNzcpIGJ5dGVfY250KDc2Ojc0KSB0cmFuc19leGNsdXNpdmUoNzMpIHRyYW5zX2xvY2soNzIpIHRyYW5zX3JlYWQoNzEpIHRyYW5zX3dyaXRlKDcwKSB0cmFuc19wb3N0ZWQoNjkpIHRyYW5zX2NvbXByZXNzZWRfcmVhZCg2OCkgYWRkcig2NzozNikgYnl0ZWVuKDM1OjMyKSBkYXRhKDMxOjAp::TWVybGluIHBhY2tldCBmb3JtYXQgZGVzY3JpcHRvcg=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1VQUFJFU1NfMF9CWVRFRU5fUlNQ::MA==::U3VwcHJlc3MgMC1ieXRlZW5hYmxlIHJlc3BvbnNlcw=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "SUQ=::MA==::TWFzdGVyIElE"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QlVSU1RXUkFQX1ZBTFVF::MQ==::QnVyc3R3cmFwIHZhbHVl"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q0FDSEVfVkFMVUU=::MA==::Q2FjaGUgdmFsdWU="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U0VDVVJFX0FDQ0VTU19CSVQ=::MQ==::U2VjdXJpdHkgYml0IHZhbHVl"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ=="
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9zbGF2ZV90cmFuc2xhdG9y"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIFNsYXZlIFRyYW5zbGF0b3I="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgdGhlIEF2YWxvbi1NTSBzbGF2ZSBpbnRlcmZhY2UgdG8gYSBzaW1wbGlmaWVkIHJlcHJlc2VudGF0aW9uIHRoYXQgdGhlIFFzeXMgbmV0d29yayB1c2VzLiBSZWZlciB0byB0aGUgQXZhbG9uIEludGVyZmFjZSBTcGVjaWZpY2F0aW9ucyAoaHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvbWFudWFsL21ubF9hdmFsb25fc3BlYy5wZGYpIGZvciBkZWZpbml0aW9ucyBvZiB0aGUgQXZhbG9uLU1NIHNpZ25hbHMgYW5kIGV4cGxhbmF0aW9ucyBvZiB0aGUgYnVyc3RpbmcgcHJvcGVydGllcyBhbmQgYWRkcmVzcyBhbGlnbm1lbnQu"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19X::Mg==::Q29tcG9uZW50IGFkZHJlc3Mgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9X::MzI=::Q29tcG9uZW50IERhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0RBVEFfVw==::MzI=::TmV0d29yayBEYXRhIHdpZHRo"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::MQ==::Q29tcG9uZW50IGJ1cnN0Y291bnQgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQllURUVOQUJMRV9X::MQ==::Q29tcG9uZW50IGJ5dGVlbmFibGUgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0JZVEVFTkFCTEVfVw==::NA==::TmV0d29yayBieXRlZW5hYmxlIHdpZHRo"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NfVw==::MzI=::TmV0d29yayBhZGRyZXNzIHdpZHRo"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0JVUlNUQ09VTlRfVw==::Mw==::TmV0d29yayBidXJzdGNvdW50IHdpZHRo"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVBRExBVEVOQ1k=::MA==::cmVhZExhdGVuY3k="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVA==::MA==::c2V0dXBUaW1l"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVA==::MA==::d3JpdGVXYWl0VGltZQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlU::MQ==::cmVhZFdhaXRUaW1l"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xE::MA==::SG9sZCB0aW1l"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfVElNSU5HX1VOSVRT::MQ==::VGltaW5nIHVuaXRz"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRB::MQ==::VXNlIHJlYWRkYXRh"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFREFUQQ==::MQ==::VXNlIHdyaXRlZGF0YQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUQ=::MA==::VXNlIHJlYWQ="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRF::MQ==::VXNlIHdyaXRl"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOQlVSU1RUUkFOU0ZFUg==::MA==::VXNlIGJlZ2luYnVyc3R0cmFuc2Zlcg=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOVFJBTlNGRVI=::MA==::VXNlIGJlZ2ludHJhbnNmZXI="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0JZVEVFTkFCTEU=::MA==::VXNlIGJ5dGVlbmFibGU="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0NISVBTRUxFQ1Q=::MQ==::VXNlIGNoaXBzZWxlY3Q="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0FERFJFU1M=::MQ==::VXNlIGFkZHJlc3M="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0JVUlNUQ09VTlQ=::MA==::VXNlIGJ1cnN0Y291bnQ="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRBVkFMSUQ=::MA==::VXNlIHJlYWRkYXRhdmFsaWQ="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dBSVRSRVFVRVNU::MA==::VXNlIHdhaXRyZXF1ZXN0"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFQllURUVOQUJMRQ==::MA==::VXNlIHdyaXRlYnl0ZWVuYWJsZQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0xPQ0s=::MA==::VXNlIGxvY2s="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0FWX0NMS0VO::MA==::VXNlIGNvbXBvbmVudCBjbGtlbg=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1VBVl9DTEtFTg==::MA==::VXNlIG5ldHdvcmsgY2xrZW4="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX09VVFBVVEVOQUJMRQ==::MA==::VXNlIG91dHB1dGVuYWJsZQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0RFQlVHQUNDRVNT::MA==::VXNlIGRlYnVnYWNjZXNz"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfU1lNQk9MU19QRVJfV09SRA==::NA==::U3ltYm9scyBwZXIgd29yZA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19TWU1CT0xT::MA==::QWRkcmVzcyBzeW1ib2xz"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9TWU1CT0xT::MA==::QnVyc3Rjb3VudCBzeW1ib2xz"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQ09OU1RBTlRfQlVSU1RfQkVIQVZJT1I=::MA==::Q29tcG9uZW50IGNvbnN0YW50QnVyc3RCZWhhdmlvcg=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0NPTlNUQU5UX0JVUlNUX0JFSEFWSU9S::MA==::TmV0d29yayBjb25zdGFudEJ1cnN0QmVoYXZpb3I="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVRVUlSRV9VTkFMSUdORURfQUREUkVTU0VT::MA==::VW5hbGlnbmVkIGFkZHJlc3Nlcw=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTlM=::MQ==::bWF4UGVuZGluZ1JlYWRUcmFuc2FjdGlvbnM="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfV1JJVEVfVFJBTlNBQ1RJT05T::MA==::bWF4UGVuZGluZ1dyaXRlVHJhbnNhY3Rpb25z"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MA==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfSU5URVJMRUFWRUJVUlNUUw==::MA==::aW50ZXJsZWF2ZUJ1cnN0cw=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQklUU19QRVJfU1lNQk9M::OA==::Qml0cy9zeW1ib2w="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfSVNCSUdFTkRJQU4=::MA==::aXNCaWdFbmRpYW4="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU0dST1VQ::MA==::Q29tcG9uZW50IGFkZHJlc3MgZ3JvdXA="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NHUk9VUA==::MA==::TmV0d29yayBhZGRyZXNzIGdyb3Vw"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJPVVRHT0lOR1NJR05BTFM=::MA==::cmVnaXN0ZXJPdXRnb2luZ1NpZ25hbHM="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJJTkNPTUlOR1NJR05BTFM=::MA==::cmVnaXN0ZXJJbmNvbWluZ1NpZ25hbHM="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQUxXQVlTQlVSU1RNQVhCVVJTVA==::MA==::QWx3YXlzIGJ1cnN0IG1heC1idXJzdA=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q0hJUFNFTEVDVF9USFJPVUdIX1JFQURMQVRFTkNZ::MA==::Q2hpcHNlbGVjdCB0aHJvdWdoIHJlYWQgbGF0ZW5jeQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfUkFURQ==::NTAwMDAwMDA=::Q0xPQ0tfUkFURQ=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlUX0NZQ0xFUw==::MQ==::QVZfUkVBRF9XQUlUX0NZQ0xFUw=="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVF9DWUNMRVM=::MA==::QVZfV1JJVEVfV0FJVF9DWUNMRVM="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVF9DWUNMRVM=::MA==::QVZfU0VUVVBfV0FJVF9DWUNMRVM="
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xEX0NZQ0xFUw==::MA==::QVZfREFUQV9IT0xEX0NZQ0xFUw=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX21lcmxpbl9tYXN0ZXJfdHJhbnNsYXRvcg=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1NIE1hc3RlciBUcmFuc2xhdG9y"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "Q29udmVydHMgdGhlIEF2YWxvbi1NTSBtYXN0ZXIgaW50ZXJmYWNlIHRvIGEgc2ltcGxlciByZXByZXNlbnRhdGlvbiB0aGF0IHRoZSBRc3lzIG5ldHdvcmsgdXNlcy4gUmVmZXIgdG8gdGhlIEF2YWxvbiBJbnRlcmZhY2UgU3BlY2lmaWNhdGlvbnMgKGh0dHA6Ly93d3cuYWx0ZXJhLmNvbS9saXRlcmF0dXJlL21hbnVhbC9tbmxfYXZhbG9uX3NwZWMucGRmKSBmb3IgZGVmaW5pdGlvbnMgb2YgdGhlIEF2YWxvbi1NTSBzaWduYWxzIGFuZCBleHBsYW5hdGlvbnMgb2YgdGhlIGJ1cnN0aW5nIHByb3BlcnRpZXMu"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19X::MzI=::Q29tcG9uZW50IGFkZHJlc3Mgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9X::MzI=::Q29tcG9uZW50IERhdGEgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9X::MQ==::Q29tcG9uZW50IGJ1cnN0Y291bnQgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQllURUVOQUJMRV9X::NA==::Q29tcG9uZW50IGJ5dGVlbmFibGUgd2lkdGg="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NfVw==::MzI=::TmV0d29yayBhZGRyZXNzIHdpZHRo"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0JVUlNUQ09VTlRfVw==::Mw==::TmV0d29yayBidXJzdGNvdW50IHdpZHRo"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVBRExBVEVOQ1k=::MA==::cmVhZExhdGVuY3k="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfV1JJVEVfV0FJVA==::MA==::d3JpdGVXYWl0VGltZQ=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVBRF9XQUlU::MQ==::cmVhZFdhaXRUaW1l"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfREFUQV9IT0xE::MA==::SG9sZCB0aW1l"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfU0VUVVBfV0FJVA==::MA==::c2V0dXBUaW1l"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRB::MQ==::VXNlIHJlYWRkYXRh"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFREFUQQ==::MQ==::VXNlIHdyaXRlZGF0YQ=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUQ=::MQ==::VXNlIHJlYWQ="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRF::MQ==::VXNlIHdyaXRl"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOQlVSU1RUUkFOU0ZFUg==::MA==::VXNlIGJlZ2luYnVyc3R0cmFuc2Zlcg=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0JFR0lOVFJBTlNGRVI=::MA==::VXNlIGJlZ2ludHJhbnNmZXI="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0JZVEVFTkFCTEU=::MQ==::VXNlIGJ5dGVlbmFibGU="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0NISVBTRUxFQ1Q=::MA==::VXNlIGNoaXBzZWxlY3Q="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0FERFJFU1M=::MQ==::VXNlIGFkZHJlc3M="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0JVUlNUQ09VTlQ=::MA==::VXNlIGJ1cnN0Y291bnQ="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0RFQlVHQUNDRVNT::MA==::VXNlIGRlYnVnYWNjZXNz"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0NMS0VO::MA==::VXNlIG5ldHdvcmsgY2xrZW4="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQUREQVRBVkFMSUQ=::MQ==::VXNlIHJlYWRkYXRhdmFsaWQ="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dBSVRSRVFVRVNU::MQ==::VXNlIHdhaXRyZXF1ZXN0"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0xPQ0s=::MA==::VXNlIGxvY2s="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1JFQURSRVNQT05TRQ==::MA==::VXNlIHJlYWRyZXNwb25zZQ=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1dSSVRFUkVTUE9OU0U=::MA==::VXNlIHdyaXRlcmVzcG9uc2U="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfU1lNQk9MU19QRVJfV09SRA==::NA==::U3ltYm9scyBwZXIgd29yZA=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU19TWU1CT0xT::MQ==::QWRkcmVzcyBzeW1ib2xz"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RDT1VOVF9TWU1CT0xT::MA==::QnVyc3Rjb3VudCBzeW1ib2xz"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQ09OU1RBTlRfQlVSU1RfQkVIQVZJT1I=::MA==::Q29tcG9uZW50IGNvbnN0YW50QnVyc3RCZWhhdmlvcg=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0NPTlNUQU5UX0JVUlNUX0JFSEFWSU9S::MA==::TmV0d29yayBjb25zdGFudEJ1cnN0QmVoYXZpb3I="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfTElORVdSQVBCVVJTVFM=::MA==::bGluZXdyYXBCdXJzdHM="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfTUFYX1BFTkRJTkdfUkVBRF9UUkFOU0FDVElPTlM=::NjQ=::bWF4UGVuZGluZ1JlYWRUcmFuc2FjdGlvbnM="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQlVSU1RCT1VOREFSSUVT::MA==::YnVyc3RPbkJ1cnN0Qm91bmRhcmllc09ubHk="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfSU5URVJMRUFWRUJVUlNUUw==::MA==::aW50ZXJsZWF2ZUJ1cnN0cw=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQklUU19QRVJfU1lNQk9M::OA==::Qml0cy9zeW1ib2w="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfSVNCSUdFTkRJQU4=::MA==::aXNCaWdFbmRpYW4="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQUREUkVTU0dST1VQ::MA==::Q29tcG9uZW50IGFkZHJlc3MgZ3JvdXA="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VUFWX0FERFJFU1NHUk9VUA==::MA==::TmV0d29yayBhZGRyZXNzIGdyb3Vw"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJPVVRHT0lOR1NJR05BTFM=::MA==::cmVnaXN0ZXJPdXRnb2luZ1NpZ25hbHM="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfUkVHSVNURVJJTkNPTUlOR1NJR05BTFM=::MA==::cmVnaXN0ZXJJbmNvbWluZ1NpZ25hbHM="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVZfQUxXQVlTQlVSU1RNQVhCVVJTVA==::MA==::QWx3YXlzIGJ1cnN0IG1heC1idXJzdA=="
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_COMPONENT_PARAMETER "U1lOQ19SRVNFVA==::MA==::VXNlIHN5bmNocm9ub3VzIHJlc2V0cw=="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19vdXQw"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08pIEludGVsIEZQR0EgSVA="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Yml0TW9kaWZ5aW5nT3V0UmVn::ZmFsc2U=::RW5hYmxlIGluZGl2aWR1YWwgYml0IHNldHRpbmcvY2xlYXJpbmc="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGlyZWN0aW9u::T3V0cHV0::RGlyZWN0aW9u"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "cmVzZXRWYWx1ZQ==::MA==::T3V0cHV0IFBvcnQgUmVzZXQgVmFsdWU="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "d2lkdGg=::MzI=::V2lkdGggKDEtMzIgYml0cyk="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::NTAwMDAwMDA=::Y2xvY2tSYXRl"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfdHJp::ZmFsc2U=::ZGVyaXZlZF9oYXNfdHJp"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfb3V0::dHJ1ZQ==::ZGVyaXZlZF9oYXNfb3V0"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaW4=::ZmFsc2U=::ZGVyaXZlZF9oYXNfaW4="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw==::ZmFsc2U=::ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw=="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9jYXB0dXJl::ZmFsc2U=::ZGVyaXZlZF9jYXB0dXJl"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lZGdlX3R5cGU=::Tk9ORQ==::ZGVyaXZlZF9lZGdlX3R5cGU="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pcnFfdHlwZQ==::Tk9ORQ==::ZGVyaXZlZF9pcnFfdHlwZQ=="
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaXJx::ZmFsc2U=::ZGVyaXZlZF9oYXNfaXJx"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tYXN0ZXJfMA=="
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "SlRBRyB0byBBdmFsb24gTWFzdGVyIEJyaWRnZQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "VGhlIEpUQUcgdG8gQXZhbG9uIE1hc3RlciBCcmlkZ2UgaXMgYSBjb2xsZWN0aW9uIG9mIHByZS13aXJlZCBjb21wb25lbnRzIHRoYXQgcHJvdmlkZSBhbiBBdmFsb24gTWFzdGVyIHVzaW5nIHRoZSBuZXcgSlRBRyBjaGFubmVsLg=="
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1BMSQ==::MA==::VXNlIFNpbXVsYXRpb24gTGluayBNb2Rl"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q09NUE9ORU5UX0NMT0NL::MA==::Q09NUE9ORU5UX0NMT0NL"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RkFTVF9WRVI=::MA==::RW5oYW5jZWQgdHJhbnNhY3Rpb24gbWFzdGVy"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNTRUJBNlUyM0k3::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tYXN0ZXJfMF9wMmJfYWRhcHRlcg=="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIENoYW5uZWwgQWRhcHRlcg=="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::OA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MjU1::TWF4IENoYW5uZWw="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::dHJ1ZQ==::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::QVVUTw==::SW5jbHVkZSBFbXB0eSBTaWduYWw="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tYXN0ZXJfMF9iMnBfYWRhcHRlcg=="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIENoYW5uZWwgQWRhcHRlcg=="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::OA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MjU1::TWF4IENoYW5uZWw="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0Q2hhbm5lbFdpZHRo::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0TWF4Q2hhbm5lbA==::MA==::TWF4IENoYW5uZWw="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::dHJ1ZQ==::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eVBvcnQ=::QVVUTw==::SW5jbHVkZSBFbXB0eSBTaWduYWw="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5SZWFkeUxhdGVuY3k=::MA==::UmVhZHkgTGF0ZW5jeQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9wYWNrZXRzX3RvX21hc3Rlcg=="
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIFBhY2tldHMgdG8gVHJhbnNhY3Rpb24gQ29udmVydGVy"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uIFBhY2tldHMgdG8gVHJhbnNhY3Rpb24gQ29udmVydGVy"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RVhQT1JUX01BU1RFUl9TSUdOQUxT::MA==::RVhQT1JUX01BU1RFUl9TSUdOQUxT"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RkFTVF9WRVI=::MA==::RW5oYW5jZWQgdHJhbnNhY3Rpb24gbWFzdGVy"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9wYWNrZXRzX3RvX2J5dGVz"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFBhY2tldHMgdG8gQnl0ZXMgQ29udmVydGVy"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLVNUIFBhY2tldHMgdG8gQnl0ZXMgQ29udmVydGVy"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSF9ERVJJVkVE::OA==::Q0hBTk5FTF9XSURUSF9ERVJJVkVE"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RU5DT0RJTkc=::MA==::RW5jb2Rpbmc="
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9ieXRlc190b19wYWNrZXRz"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEJ5dGVzIHRvIFBhY2tldHMgQ29udmVydGVy"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_DESCRIPTION "QXZhbG9uLVNUIEJ5dGVzIHRvIFBhY2tldHMgQ29udmVydGVy"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTF9XSURUSF9ERVJJVkVE::OA==::Q0hBTk5FTF9XSURUSF9ERVJJVkVE"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RU5DT0RJTkc=::MA==::RW5jb2Rpbmc="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19tYXN0ZXJfMF90aW1pbmdfYWR0"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIFRpbWluZyBBZGFwdGVy"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5DaGFubmVsV2lkdGg=::MA==::Q2hhbm5lbCBTaWduYWwgV2lkdGggKGJpdHMp"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5NYXhDaGFubmVs::MA==::TWF4IENoYW5uZWw="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5CaXRzUGVyU3ltYm9s::OA==::RGF0YSBCaXRzIFBlciBTeW1ib2w="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VQYWNrZXRz::ZmFsc2U=::SW5jbHVkZSBQYWNrZXQgU3VwcG9ydA=="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VFbXB0eQ==::ZmFsc2U=::aW5Vc2VFbXB0eQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5TeW1ib2xzUGVyQmVhdA==::MQ==::RGF0YSBTeW1ib2xzIFBlciBCZWF0"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VSZWFkeQ==::ZmFsc2U=::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0VXNlUmVhZHk=::dHJ1ZQ==::U3VwcG9ydCBCYWNrcHJlc3N1cmUgd2l0aCB0aGUgcmVhZHkgc2lnbmFs"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0UmVhZHlMYXRlbmN5::MA==::UmVhZHkgTGF0ZW5jeQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5FcnJvcldpZHRo::MA==::RXJyb3IgU2lnbmFsIFdpZHRoIChiaXRzKQ=="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "aW5Vc2VWYWxpZA==::dHJ1ZQ==::SW5jbHVkZSBWYWxpZCBTaWduYWw="
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_COMPONENT_PARAMETER "b3V0VXNlVmFsaWQ=::dHJ1ZQ==::SW5jbHVkIFZhbGlkIFNpZ25hbA=="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zdF9qdGFnX2ludGVyZmFjZQ=="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uLVNUIEpUQUcgSW50ZXJmYWNl"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_INTERNAL "On"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "UFVSUE9TRQ==::MQ==::UFVSUE9TRQ=="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVBTVFJFQU1fRklGT19TSVpF::MA==::VVBTVFJFQU1fRklGT19TSVpF"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RE9XTlNUUkVBTV9GSUZPX1NJWkU=::NjQ=::RE9XTlNUUkVBTV9GSUZPX1NJWkU="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "TUdNVF9DSEFOTkVMX1dJRFRI::LTE=::TWFuYWdlbWVudCBjaGFubmVsIHdpZHRo"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RVhQT1JUX0pUQUc=::MA==::RVhQT1JUX0pUQUc="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX1BMSQ==::MA==::VXNlIFNpbXVsYXRpb24gTGluayBNb2Rl"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "VVNFX0RPV05TVFJFQU1fUkVBRFk=::MA==::VVNFX0RPV05TVFJFQU1fUkVBRFk="
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Q09NUE9ORU5UX0NMT0NL::MA==::Q09NUE9ORU5UX0NMT0NL"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_COMPONENT_PARAMETER "RkFCUklD::Mi4w::RkFCUklD"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_NAME "anRhZ19pb19pbjA="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08pIEludGVsIEZQR0EgSVA="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Y2FwdHVyZUVkZ2U=::ZmFsc2U=::U3luY2hyb25vdXNseSBjYXB0dXJl"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGlyZWN0aW9u::SW5wdXQ=::RGlyZWN0aW9u"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Z2VuZXJhdGVJUlE=::ZmFsc2U=::R2VuZXJhdGUgSVJR"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "c2ltRG9UZXN0QmVuY2hXaXJpbmc=::ZmFsc2U=::SGFyZHdpcmUgUElPIGlucHV0cyBpbiB0ZXN0IGJlbmNo"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "d2lkdGg=::MzI=::V2lkdGggKDEtMzIgYml0cyk="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::NTAwMDAwMDA=::Y2xvY2tSYXRl"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfdHJp::ZmFsc2U=::ZGVyaXZlZF9oYXNfdHJp"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfb3V0::ZmFsc2U=::ZGVyaXZlZF9oYXNfb3V0"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaW4=::dHJ1ZQ==::ZGVyaXZlZF9oYXNfaW4="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw==::ZmFsc2U=::ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw=="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9jYXB0dXJl::ZmFsc2U=::ZGVyaXZlZF9jYXB0dXJl"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lZGdlX3R5cGU=::Tk9ORQ==::ZGVyaXZlZF9lZGdlX3R5cGU="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pcnFfdHlwZQ==::Tk9ORQ==::ZGVyaXZlZF9pcnFfdHlwZQ=="
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaXJx::ZmFsc2U=::ZGVyaXZlZF9oYXNfaXJx"
|
||||
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "jtag_io.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"]
|
||||
set_global_assignment -library "jtag_io" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0_avalon_st_adapter.v"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0_rsp_mux.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_arbitrator.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0_rsp_demux.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0_cmd_mux.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0_cmd_demux.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_traffic_limiter.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_reorder_memory.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_sc_fifo.v"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_pipeline_base.v"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0_router_001.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_mm_interconnect_0_router.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_agent.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_uncompressor.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_agent.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_out0.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_master_0.v"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_master_0_p2b_adapter.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_master_0_b2p_adapter.sv"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_packets_to_master.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_packets_to_bytes.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_bytes_to_packets.v"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_master_0_timing_adt.sv"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_jtag_interface.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_jtag_dc_streaming.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_jtag_sld_node.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_jtag_streaming.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_clock_crosser.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_std_synchronizer_nocut.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_idle_remover.v"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_idle_inserter.v"]
|
||||
set_global_assignment -library "jtag_io" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_pipeline_stage.sv"]
|
||||
set_global_assignment -library "jtag_io" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_jtag_interface.sdc"]
|
||||
set_global_assignment -library "jtag_io" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/jtag_io_in0.v"]
|
||||
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_TOOL_NAME "altera_reset_controller"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_reset_controller" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_TOOL_NAME "altera_mm_interconnect"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_TOOL_NAME "altera_avalon_st_adapter"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_TOOL_NAME "error_adapter"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_multiplexer"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_mux" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_rsp_demux" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_multiplexer"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_mux" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_cmd_demux" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_traffic_limiter"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_router"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router_001" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_router"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_mm_interconnect_0_router" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_TOOL_NAME "altera_avalon_sc_fifo"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_avalon_sc_fifo" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_slave_agent"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_merlin_slave_agent" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_master_agent"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_merlin_master_agent" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_slave_translator"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_merlin_slave_translator" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_TOOL_NAME "altera_merlin_master_translator"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_merlin_master_translator" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_TOOL_NAME "altera_avalon_pio"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_out0" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_TOOL_NAME "altera_jtag_avalon_master"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_master_0" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_TOOL_NAME "channel_adapter"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_master_0_p2b_adapter" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_TOOL_NAME "channel_adapter"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_master_0_b2p_adapter" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_TOOL_NAME "altera_avalon_packets_to_master"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_avalon_packets_to_master" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_TOOL_NAME "altera_avalon_st_packets_to_bytes"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_TOOL_NAME "altera_avalon_st_bytes_to_packets"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_TOOL_NAME "timing_adapter"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_master_0_timing_adt" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_TOOL_NAME "altera_jtag_dc_streaming"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_TOOL_NAME "altera_avalon_pio"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "jtag_io_in0" -library "jtag_io" -name IP_TOOL_ENV "Qsys"
|
||||
@ -0,0 +1,478 @@
|
||||
<?xml version="1.0"?>
|
||||
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
|
||||
<name>jtag_io</name>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>jtag_io_out1_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>jtag_io_out0_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>jtag_io_in1_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>jtag_io_in0_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
</peripherals>
|
||||
</device>
|
||||
186
example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/jtag_io.v
Executable file
186
example_projects/quartus_test_prj_template_v4/ip/jtag_io/synthesis/jtag_io.v
Executable file
@ -0,0 +1,186 @@
|
||||
// jtag_io.v
|
||||
|
||||
// Generated using ACDS version 20.1 711
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module jtag_io (
|
||||
input wire clk_clk, // clk.clk
|
||||
input wire [31:0] in0_export, // in0.export
|
||||
input wire [31:0] in1_export, // in1.export
|
||||
output wire [31:0] out0_export, // out0.export
|
||||
output wire [31:0] out1_export, // out1.export
|
||||
input wire reset_reset_n // reset.reset_n
|
||||
);
|
||||
|
||||
wire [31:0] master_0_master_readdata; // mm_interconnect_0:master_0_master_readdata -> master_0:master_readdata
|
||||
wire master_0_master_waitrequest; // mm_interconnect_0:master_0_master_waitrequest -> master_0:master_waitrequest
|
||||
wire [31:0] master_0_master_address; // master_0:master_address -> mm_interconnect_0:master_0_master_address
|
||||
wire master_0_master_read; // master_0:master_read -> mm_interconnect_0:master_0_master_read
|
||||
wire [3:0] master_0_master_byteenable; // master_0:master_byteenable -> mm_interconnect_0:master_0_master_byteenable
|
||||
wire master_0_master_readdatavalid; // mm_interconnect_0:master_0_master_readdatavalid -> master_0:master_readdatavalid
|
||||
wire master_0_master_write; // master_0:master_write -> mm_interconnect_0:master_0_master_write
|
||||
wire [31:0] master_0_master_writedata; // master_0:master_writedata -> mm_interconnect_0:master_0_master_writedata
|
||||
wire mm_interconnect_0_out0_s1_chipselect; // mm_interconnect_0:out0_s1_chipselect -> out0:chipselect
|
||||
wire [31:0] mm_interconnect_0_out0_s1_readdata; // out0:readdata -> mm_interconnect_0:out0_s1_readdata
|
||||
wire [1:0] mm_interconnect_0_out0_s1_address; // mm_interconnect_0:out0_s1_address -> out0:address
|
||||
wire mm_interconnect_0_out0_s1_write; // mm_interconnect_0:out0_s1_write -> out0:write_n
|
||||
wire [31:0] mm_interconnect_0_out0_s1_writedata; // mm_interconnect_0:out0_s1_writedata -> out0:writedata
|
||||
wire mm_interconnect_0_out1_s1_chipselect; // mm_interconnect_0:out1_s1_chipselect -> out1:chipselect
|
||||
wire [31:0] mm_interconnect_0_out1_s1_readdata; // out1:readdata -> mm_interconnect_0:out1_s1_readdata
|
||||
wire [1:0] mm_interconnect_0_out1_s1_address; // mm_interconnect_0:out1_s1_address -> out1:address
|
||||
wire mm_interconnect_0_out1_s1_write; // mm_interconnect_0:out1_s1_write -> out1:write_n
|
||||
wire [31:0] mm_interconnect_0_out1_s1_writedata; // mm_interconnect_0:out1_s1_writedata -> out1:writedata
|
||||
wire [31:0] mm_interconnect_0_in0_s1_readdata; // in0:readdata -> mm_interconnect_0:in0_s1_readdata
|
||||
wire [1:0] mm_interconnect_0_in0_s1_address; // mm_interconnect_0:in0_s1_address -> in0:address
|
||||
wire [31:0] mm_interconnect_0_in1_s1_readdata; // in1:readdata -> mm_interconnect_0:in1_s1_readdata
|
||||
wire [1:0] mm_interconnect_0_in1_s1_address; // mm_interconnect_0:in1_s1_address -> in1:address
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [in0:reset_n, in1:reset_n, mm_interconnect_0:master_0_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:out0_reset_reset_bridge_in_reset_reset, out0:reset_n, out1:reset_n]
|
||||
|
||||
jtag_io_in0 in0 (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
.address (mm_interconnect_0_in0_s1_address), // s1.address
|
||||
.readdata (mm_interconnect_0_in0_s1_readdata), // .readdata
|
||||
.in_port (in0_export) // external_connection.export
|
||||
);
|
||||
|
||||
jtag_io_in0 in1 (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
.address (mm_interconnect_0_in1_s1_address), // s1.address
|
||||
.readdata (mm_interconnect_0_in1_s1_readdata), // .readdata
|
||||
.in_port (in1_export) // external_connection.export
|
||||
);
|
||||
|
||||
jtag_io_master_0 #(
|
||||
.USE_PLI (0),
|
||||
.PLI_PORT (50000),
|
||||
.FIFO_DEPTHS (2)
|
||||
) master_0 (
|
||||
.clk_clk (clk_clk), // clk.clk
|
||||
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
|
||||
.master_address (master_0_master_address), // master.address
|
||||
.master_readdata (master_0_master_readdata), // .readdata
|
||||
.master_read (master_0_master_read), // .read
|
||||
.master_write (master_0_master_write), // .write
|
||||
.master_writedata (master_0_master_writedata), // .writedata
|
||||
.master_waitrequest (master_0_master_waitrequest), // .waitrequest
|
||||
.master_readdatavalid (master_0_master_readdatavalid), // .readdatavalid
|
||||
.master_byteenable (master_0_master_byteenable), // .byteenable
|
||||
.master_reset_reset () // master_reset.reset
|
||||
);
|
||||
|
||||
jtag_io_out0 out0 (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
.address (mm_interconnect_0_out0_s1_address), // s1.address
|
||||
.write_n (~mm_interconnect_0_out0_s1_write), // .write_n
|
||||
.writedata (mm_interconnect_0_out0_s1_writedata), // .writedata
|
||||
.chipselect (mm_interconnect_0_out0_s1_chipselect), // .chipselect
|
||||
.readdata (mm_interconnect_0_out0_s1_readdata), // .readdata
|
||||
.out_port (out0_export) // external_connection.export
|
||||
);
|
||||
|
||||
jtag_io_out0 out1 (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
.address (mm_interconnect_0_out1_s1_address), // s1.address
|
||||
.write_n (~mm_interconnect_0_out1_s1_write), // .write_n
|
||||
.writedata (mm_interconnect_0_out1_s1_writedata), // .writedata
|
||||
.chipselect (mm_interconnect_0_out1_s1_chipselect), // .chipselect
|
||||
.readdata (mm_interconnect_0_out1_s1_readdata), // .readdata
|
||||
.out_port (out1_export) // external_connection.export
|
||||
);
|
||||
|
||||
jtag_io_mm_interconnect_0 mm_interconnect_0 (
|
||||
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
|
||||
.master_0_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // master_0_clk_reset_reset_bridge_in_reset.reset
|
||||
.out0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // out0_reset_reset_bridge_in_reset.reset
|
||||
.master_0_master_address (master_0_master_address), // master_0_master.address
|
||||
.master_0_master_waitrequest (master_0_master_waitrequest), // .waitrequest
|
||||
.master_0_master_byteenable (master_0_master_byteenable), // .byteenable
|
||||
.master_0_master_read (master_0_master_read), // .read
|
||||
.master_0_master_readdata (master_0_master_readdata), // .readdata
|
||||
.master_0_master_readdatavalid (master_0_master_readdatavalid), // .readdatavalid
|
||||
.master_0_master_write (master_0_master_write), // .write
|
||||
.master_0_master_writedata (master_0_master_writedata), // .writedata
|
||||
.in0_s1_address (mm_interconnect_0_in0_s1_address), // in0_s1.address
|
||||
.in0_s1_readdata (mm_interconnect_0_in0_s1_readdata), // .readdata
|
||||
.in1_s1_address (mm_interconnect_0_in1_s1_address), // in1_s1.address
|
||||
.in1_s1_readdata (mm_interconnect_0_in1_s1_readdata), // .readdata
|
||||
.out0_s1_address (mm_interconnect_0_out0_s1_address), // out0_s1.address
|
||||
.out0_s1_write (mm_interconnect_0_out0_s1_write), // .write
|
||||
.out0_s1_readdata (mm_interconnect_0_out0_s1_readdata), // .readdata
|
||||
.out0_s1_writedata (mm_interconnect_0_out0_s1_writedata), // .writedata
|
||||
.out0_s1_chipselect (mm_interconnect_0_out0_s1_chipselect), // .chipselect
|
||||
.out1_s1_address (mm_interconnect_0_out1_s1_address), // out1_s1.address
|
||||
.out1_s1_write (mm_interconnect_0_out1_s1_write), // .write
|
||||
.out1_s1_readdata (mm_interconnect_0_out1_s1_readdata), // .readdata
|
||||
.out1_s1_writedata (mm_interconnect_0_out1_s1_writedata), // .writedata
|
||||
.out1_s1_chipselect (mm_interconnect_0_out1_s1_chipselect) // .chipselect
|
||||
);
|
||||
|
||||
altera_reset_controller #(
|
||||
.NUM_RESET_INPUTS (1),
|
||||
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
||||
.SYNC_DEPTH (2),
|
||||
.RESET_REQUEST_PRESENT (0),
|
||||
.RESET_REQ_WAIT_TIME (1),
|
||||
.MIN_RST_ASSERTION_TIME (3),
|
||||
.RESET_REQ_EARLY_DSRT_TIME (1),
|
||||
.USE_RESET_REQUEST_IN0 (0),
|
||||
.USE_RESET_REQUEST_IN1 (0),
|
||||
.USE_RESET_REQUEST_IN2 (0),
|
||||
.USE_RESET_REQUEST_IN3 (0),
|
||||
.USE_RESET_REQUEST_IN4 (0),
|
||||
.USE_RESET_REQUEST_IN5 (0),
|
||||
.USE_RESET_REQUEST_IN6 (0),
|
||||
.USE_RESET_REQUEST_IN7 (0),
|
||||
.USE_RESET_REQUEST_IN8 (0),
|
||||
.USE_RESET_REQUEST_IN9 (0),
|
||||
.USE_RESET_REQUEST_IN10 (0),
|
||||
.USE_RESET_REQUEST_IN11 (0),
|
||||
.USE_RESET_REQUEST_IN12 (0),
|
||||
.USE_RESET_REQUEST_IN13 (0),
|
||||
.USE_RESET_REQUEST_IN14 (0),
|
||||
.USE_RESET_REQUEST_IN15 (0),
|
||||
.ADAPT_RESET_REQUEST (0)
|
||||
) rst_controller (
|
||||
.reset_in0 (~reset_reset_n), // reset_in0.reset
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
|
||||
.reset_req (), // (terminated)
|
||||
.reset_req_in0 (1'b0), // (terminated)
|
||||
.reset_in1 (1'b0), // (terminated)
|
||||
.reset_req_in1 (1'b0), // (terminated)
|
||||
.reset_in2 (1'b0), // (terminated)
|
||||
.reset_req_in2 (1'b0), // (terminated)
|
||||
.reset_in3 (1'b0), // (terminated)
|
||||
.reset_req_in3 (1'b0), // (terminated)
|
||||
.reset_in4 (1'b0), // (terminated)
|
||||
.reset_req_in4 (1'b0), // (terminated)
|
||||
.reset_in5 (1'b0), // (terminated)
|
||||
.reset_req_in5 (1'b0), // (terminated)
|
||||
.reset_in6 (1'b0), // (terminated)
|
||||
.reset_req_in6 (1'b0), // (terminated)
|
||||
.reset_in7 (1'b0), // (terminated)
|
||||
.reset_req_in7 (1'b0), // (terminated)
|
||||
.reset_in8 (1'b0), // (terminated)
|
||||
.reset_req_in8 (1'b0), // (terminated)
|
||||
.reset_in9 (1'b0), // (terminated)
|
||||
.reset_req_in9 (1'b0), // (terminated)
|
||||
.reset_in10 (1'b0), // (terminated)
|
||||
.reset_req_in10 (1'b0), // (terminated)
|
||||
.reset_in11 (1'b0), // (terminated)
|
||||
.reset_req_in11 (1'b0), // (terminated)
|
||||
.reset_in12 (1'b0), // (terminated)
|
||||
.reset_req_in12 (1'b0), // (terminated)
|
||||
.reset_in13 (1'b0), // (terminated)
|
||||
.reset_req_in13 (1'b0), // (terminated)
|
||||
.reset_in14 (1'b0), // (terminated)
|
||||
.reset_req_in14 (1'b0), // (terminated)
|
||||
.reset_in15 (1'b0), // (terminated)
|
||||
.reset_req_in15 (1'b0) // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,915 @@
|
||||
// -----------------------------------------------------------
|
||||
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
|
||||
// use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any
|
||||
// output files any of the foregoing (including device programming or
|
||||
// simulation files), and any associated documentation or information are
|
||||
// expressly subject to the terms and conditions of the Altera Program
|
||||
// License Subscription Agreement or other applicable license agreement,
|
||||
// including, without limitation, that your use is for the sole purpose
|
||||
// of programming logic devices manufactured by Altera and sold by Altera
|
||||
// or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
//
|
||||
// Description: Single clock Avalon-ST FIFO.
|
||||
// -----------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
|
||||
//altera message_off 10036
|
||||
module altera_avalon_sc_fifo
|
||||
#(
|
||||
// --------------------------------------------------
|
||||
// Parameters
|
||||
// --------------------------------------------------
|
||||
parameter SYMBOLS_PER_BEAT = 1,
|
||||
parameter BITS_PER_SYMBOL = 8,
|
||||
parameter FIFO_DEPTH = 16,
|
||||
parameter CHANNEL_WIDTH = 0,
|
||||
parameter ERROR_WIDTH = 0,
|
||||
parameter USE_PACKETS = 0,
|
||||
parameter USE_FILL_LEVEL = 0,
|
||||
parameter USE_STORE_FORWARD = 0,
|
||||
parameter USE_ALMOST_FULL_IF = 0,
|
||||
parameter USE_ALMOST_EMPTY_IF = 0,
|
||||
|
||||
// --------------------------------------------------
|
||||
// Empty latency is defined as the number of cycles
|
||||
// required for a write to deassert the empty flag.
|
||||
// For example, a latency of 1 means that the empty
|
||||
// flag is deasserted on the cycle after a write.
|
||||
//
|
||||
// Another way to think of it is the latency for a
|
||||
// write to propagate to the output.
|
||||
//
|
||||
// An empty latency of 0 implies lookahead, which is
|
||||
// only implemented for the register-based FIFO.
|
||||
// --------------------------------------------------
|
||||
parameter EMPTY_LATENCY = 3,
|
||||
parameter USE_MEMORY_BLOCKS = 1,
|
||||
|
||||
// --------------------------------------------------
|
||||
// Internal Parameters
|
||||
// --------------------------------------------------
|
||||
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
|
||||
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
|
||||
)
|
||||
(
|
||||
// --------------------------------------------------
|
||||
// Ports
|
||||
// --------------------------------------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [DATA_WIDTH-1: 0] in_data,
|
||||
input in_valid,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
|
||||
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
|
||||
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
|
||||
output in_ready,
|
||||
|
||||
output [DATA_WIDTH-1 : 0] out_data,
|
||||
output reg out_valid,
|
||||
output out_startofpacket,
|
||||
output out_endofpacket,
|
||||
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
|
||||
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
|
||||
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
|
||||
input out_ready,
|
||||
|
||||
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
|
||||
input csr_write,
|
||||
input csr_read,
|
||||
input [31 : 0] csr_writedata,
|
||||
output reg [31 : 0] csr_readdata,
|
||||
|
||||
output wire almost_full_data,
|
||||
output wire almost_empty_data
|
||||
);
|
||||
|
||||
// --------------------------------------------------
|
||||
// Local Parameters
|
||||
// --------------------------------------------------
|
||||
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
|
||||
localparam DEPTH = FIFO_DEPTH;
|
||||
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
|
||||
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
|
||||
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
|
||||
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
|
||||
|
||||
// --------------------------------------------------
|
||||
// Internal Signals
|
||||
// --------------------------------------------------
|
||||
genvar i;
|
||||
|
||||
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
|
||||
reg [ADDR_WIDTH-1 : 0] wr_ptr;
|
||||
reg [ADDR_WIDTH-1 : 0] rd_ptr;
|
||||
reg [DEPTH-1 : 0] mem_used;
|
||||
|
||||
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
|
||||
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
|
||||
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
|
||||
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
|
||||
|
||||
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
|
||||
|
||||
wire read;
|
||||
wire write;
|
||||
|
||||
reg empty;
|
||||
reg next_empty;
|
||||
reg full;
|
||||
reg next_full;
|
||||
|
||||
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
|
||||
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
|
||||
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
|
||||
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
|
||||
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
|
||||
|
||||
reg internal_out_valid;
|
||||
wire internal_out_ready;
|
||||
|
||||
reg [ADDR_WIDTH : 0] fifo_fill_level;
|
||||
reg [ADDR_WIDTH : 0] fill_level;
|
||||
|
||||
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
|
||||
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
|
||||
reg [23:0] almost_full_threshold;
|
||||
reg [23:0] almost_empty_threshold;
|
||||
reg [23:0] cut_through_threshold;
|
||||
reg [15:0] pkt_cnt;
|
||||
reg drop_on_error_en;
|
||||
reg error_in_pkt;
|
||||
reg pkt_has_started;
|
||||
reg sop_has_left_fifo;
|
||||
reg fifo_too_small_r;
|
||||
reg pkt_cnt_eq_zero;
|
||||
reg pkt_cnt_eq_one;
|
||||
|
||||
wire wait_for_threshold;
|
||||
reg pkt_mode;
|
||||
wire wait_for_pkt;
|
||||
wire ok_to_forward;
|
||||
wire in_pkt_eop_arrive;
|
||||
wire out_pkt_leave;
|
||||
wire in_pkt_start;
|
||||
wire in_pkt_error;
|
||||
wire drop_on_error;
|
||||
wire fifo_too_small;
|
||||
wire out_pkt_sop_leave;
|
||||
wire [31:0] max_fifo_size;
|
||||
reg fifo_fill_level_lt_cut_through_threshold;
|
||||
|
||||
// --------------------------------------------------
|
||||
// Define Payload
|
||||
//
|
||||
// Icky part where we decide which signals form the
|
||||
// payload to the FIFO with generate blocks.
|
||||
// --------------------------------------------------
|
||||
generate
|
||||
if (EMPTY_WIDTH > 0) begin : gen_blk1
|
||||
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
|
||||
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
|
||||
end
|
||||
else begin : gen_blk1_else
|
||||
assign out_empty = in_error;
|
||||
assign in_packet_signals = {in_startofpacket, in_endofpacket};
|
||||
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (USE_PACKETS) begin : gen_blk2
|
||||
if (ERROR_WIDTH > 0) begin : gen_blk3
|
||||
if (CHANNEL_WIDTH > 0) begin : gen_blk4
|
||||
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
|
||||
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
|
||||
end
|
||||
else begin : gen_blk4_else
|
||||
assign out_channel = in_channel;
|
||||
assign in_payload = {in_packet_signals, in_data, in_error};
|
||||
assign {out_packet_signals, out_data, out_error} = out_payload;
|
||||
end
|
||||
end
|
||||
else begin : gen_blk3_else
|
||||
assign out_error = in_error;
|
||||
if (CHANNEL_WIDTH > 0) begin : gen_blk5
|
||||
assign in_payload = {in_packet_signals, in_data, in_channel};
|
||||
assign {out_packet_signals, out_data, out_channel} = out_payload;
|
||||
end
|
||||
else begin : gen_blk5_else
|
||||
assign out_channel = in_channel;
|
||||
assign in_payload = {in_packet_signals, in_data};
|
||||
assign {out_packet_signals, out_data} = out_payload;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin : gen_blk2_else
|
||||
assign out_packet_signals = 0;
|
||||
if (ERROR_WIDTH > 0) begin : gen_blk6
|
||||
if (CHANNEL_WIDTH > 0) begin : gen_blk7
|
||||
assign in_payload = {in_data, in_error, in_channel};
|
||||
assign {out_data, out_error, out_channel} = out_payload;
|
||||
end
|
||||
else begin : gen_blk7_else
|
||||
assign out_channel = in_channel;
|
||||
assign in_payload = {in_data, in_error};
|
||||
assign {out_data, out_error} = out_payload;
|
||||
end
|
||||
end
|
||||
else begin : gen_blk6_else
|
||||
assign out_error = in_error;
|
||||
if (CHANNEL_WIDTH > 0) begin : gen_blk8
|
||||
assign in_payload = {in_data, in_channel};
|
||||
assign {out_data, out_channel} = out_payload;
|
||||
end
|
||||
else begin : gen_blk8_else
|
||||
assign out_channel = in_channel;
|
||||
assign in_payload = in_data;
|
||||
assign out_data = out_payload;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------
|
||||
// Memory-based FIFO storage
|
||||
//
|
||||
// To allow a ready latency of 0, the read index is
|
||||
// obtained from the next read pointer and memory
|
||||
// outputs are unregistered.
|
||||
//
|
||||
// If the empty latency is 1, we infer bypass logic
|
||||
// around the memory so writes propagate to the
|
||||
// outputs on the next cycle.
|
||||
//
|
||||
// Do not change the way this is coded: Quartus needs
|
||||
// a perfect match to the template, and any attempt to
|
||||
// refactor the two always blocks into one will break
|
||||
// memory inference.
|
||||
// --------------------------------------------------
|
||||
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
|
||||
|
||||
if (EMPTY_LATENCY == 1) begin : gen_blk10
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (in_valid && in_ready)
|
||||
mem[wr_ptr] = in_payload;
|
||||
|
||||
internal_out_payload = mem[mem_rd_ptr];
|
||||
end
|
||||
|
||||
end else begin : gen_blk10_else
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (in_valid && in_ready)
|
||||
mem[wr_ptr] <= in_payload;
|
||||
|
||||
internal_out_payload <= mem[mem_rd_ptr];
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign mem_rd_ptr = next_rd_ptr;
|
||||
|
||||
end else begin : gen_blk9_else
|
||||
|
||||
// --------------------------------------------------
|
||||
// Register-based FIFO storage
|
||||
//
|
||||
// Uses a shift register as the storage element. Each
|
||||
// shift register slot has a bit which indicates if
|
||||
// the slot is occupied (credit to Sam H for the idea).
|
||||
// The occupancy bits are contiguous and start from the
|
||||
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
|
||||
// FIFO.
|
||||
//
|
||||
// Each slot is enabled during a read or when it
|
||||
// is unoccupied. New data is always written to every
|
||||
// going-to-be-empty slot (we keep track of which ones
|
||||
// are actually useful with the occupancy bits). On a
|
||||
// read we shift occupied slots.
|
||||
//
|
||||
// The exception is the last slot, which always gets
|
||||
// new data when it is unoccupied.
|
||||
// --------------------------------------------------
|
||||
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
mem[i] <= 0;
|
||||
end
|
||||
else if (read || !mem_used[i]) begin
|
||||
if (!mem_used[i+1])
|
||||
mem[i] <= in_payload;
|
||||
else
|
||||
mem[i] <= mem[i+1];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
mem[DEPTH-1] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (DEPTH == 1) begin
|
||||
if (write)
|
||||
mem[DEPTH-1] <= in_payload;
|
||||
end
|
||||
else if (!mem_used[DEPTH-1])
|
||||
mem[DEPTH-1] <= in_payload;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
|
||||
assign write = in_ready && in_valid;
|
||||
|
||||
// --------------------------------------------------
|
||||
// Pointer Management
|
||||
// --------------------------------------------------
|
||||
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
|
||||
|
||||
assign incremented_wr_ptr = wr_ptr + 1'b1;
|
||||
assign incremented_rd_ptr = rd_ptr + 1'b1;
|
||||
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
|
||||
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
wr_ptr <= 0;
|
||||
rd_ptr <= 0;
|
||||
end
|
||||
else begin
|
||||
wr_ptr <= next_wr_ptr;
|
||||
rd_ptr <= next_rd_ptr;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin : gen_blk11_else
|
||||
|
||||
// --------------------------------------------------
|
||||
// Shift Register Occupancy Bits
|
||||
//
|
||||
// Consider a 4-deep FIFO with 2 entries: 0011
|
||||
// On a read and write, do not modify the bits.
|
||||
// On a write, left-shift the bits to get 0111.
|
||||
// On a read, right-shift the bits to get 0001.
|
||||
//
|
||||
// Also, on a write we set bit0 (the head), while
|
||||
// clearing the tail on a read.
|
||||
// --------------------------------------------------
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
mem_used[0] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (write ^ read) begin
|
||||
if (write)
|
||||
mem_used[0] <= 1;
|
||||
else if (read) begin
|
||||
if (DEPTH > 1)
|
||||
mem_used[0] <= mem_used[1];
|
||||
else
|
||||
mem_used[0] <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if (DEPTH > 1) begin : gen_blk12
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
mem_used[DEPTH-1] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (write ^ read) begin
|
||||
mem_used[DEPTH-1] <= 0;
|
||||
if (write)
|
||||
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
mem_used[i] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (write ^ read) begin
|
||||
if (write)
|
||||
mem_used[i] <= mem_used[i-1];
|
||||
else if (read)
|
||||
mem_used[i] <= mem_used[i+1];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Memory FIFO Status Management
|
||||
//
|
||||
// Generates the full and empty signals from the
|
||||
// pointers. The FIFO is full when the next write
|
||||
// pointer will be equal to the read pointer after
|
||||
// a write. Reading from a FIFO clears full.
|
||||
//
|
||||
// The FIFO is empty when the next read pointer will
|
||||
// be equal to the write pointer after a read. Writing
|
||||
// to a FIFO clears empty.
|
||||
//
|
||||
// A simultaneous read and write must not change any of
|
||||
// the empty or full flags unless there is a drop on error event.
|
||||
// --------------------------------------------------
|
||||
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
|
||||
|
||||
always @* begin
|
||||
next_full = full;
|
||||
next_empty = empty;
|
||||
|
||||
if (read && !write) begin
|
||||
next_full = 1'b0;
|
||||
|
||||
if (incremented_rd_ptr == wr_ptr)
|
||||
next_empty = 1'b1;
|
||||
end
|
||||
|
||||
if (write && !read) begin
|
||||
if (!drop_on_error)
|
||||
next_empty = 1'b0;
|
||||
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
|
||||
next_empty = 1'b1;
|
||||
|
||||
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
|
||||
next_full = 1'b1;
|
||||
end
|
||||
|
||||
if (write && read && drop_on_error) begin
|
||||
if (curr_sop_ptr == next_rd_ptr)
|
||||
next_empty = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
empty <= 1;
|
||||
full <= 0;
|
||||
end
|
||||
else begin
|
||||
empty <= next_empty;
|
||||
full <= next_full;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin : gen_blk13_else
|
||||
// --------------------------------------------------
|
||||
// Register FIFO Status Management
|
||||
//
|
||||
// Full when the tail occupancy bit is 1. Empty when
|
||||
// the head occupancy bit is 0.
|
||||
// --------------------------------------------------
|
||||
always @* begin
|
||||
full = mem_used[DEPTH-1];
|
||||
empty = !mem_used[0];
|
||||
|
||||
// ------------------------------------------
|
||||
// For a single slot FIFO, reading clears the
|
||||
// full status immediately.
|
||||
// ------------------------------------------
|
||||
if (DEPTH == 1)
|
||||
full = mem_used[0] && !read;
|
||||
|
||||
internal_out_payload = mem[0];
|
||||
|
||||
// ------------------------------------------
|
||||
// Writes clear empty immediately for lookahead modes.
|
||||
// Note that we use in_valid instead of write to avoid
|
||||
// combinational loops (in lookahead mode, qualifying
|
||||
// with in_ready is meaningless).
|
||||
//
|
||||
// In a 1-deep FIFO, a possible combinational loop runs
|
||||
// from write -> out_valid -> out_ready -> write
|
||||
// ------------------------------------------
|
||||
if (EMPTY_LATENCY == 0) begin
|
||||
empty = !mem_used[0] && !in_valid;
|
||||
|
||||
if (!mem_used[0] && in_valid)
|
||||
internal_out_payload = in_payload;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------
|
||||
// Avalon-ST Signals
|
||||
//
|
||||
// The in_ready signal is straightforward.
|
||||
//
|
||||
// To match memory latency when empty latency > 1,
|
||||
// out_valid assertions must be delayed by one clock
|
||||
// cycle.
|
||||
//
|
||||
// Note: out_valid deassertions must not be delayed or
|
||||
// the FIFO will underflow.
|
||||
// --------------------------------------------------
|
||||
assign in_ready = !full;
|
||||
assign internal_out_ready = out_ready || !out_valid;
|
||||
|
||||
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
internal_out_valid <= 0;
|
||||
else begin
|
||||
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
|
||||
|
||||
if (read) begin
|
||||
if (incremented_rd_ptr == wr_ptr)
|
||||
internal_out_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin : gen_blk14_else
|
||||
always @* begin
|
||||
internal_out_valid = !empty & ok_to_forward;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------
|
||||
// Single Output Pipeline Stage
|
||||
//
|
||||
// This output pipeline stage is enabled if the FIFO's
|
||||
// empty latency is set to 3 (default). It is disabled
|
||||
// for all other allowed latencies.
|
||||
//
|
||||
// Reason: The memory outputs are unregistered, so we have to
|
||||
// register the output or fmax will drop if combinatorial
|
||||
// logic is present on the output datapath.
|
||||
//
|
||||
// Q: The Avalon-ST spec says that I have to register my outputs
|
||||
// But isn't the memory counted as a register?
|
||||
// A: The path from the address lookup to the memory output is
|
||||
// slow. Registering the memory outputs is a good idea.
|
||||
//
|
||||
// The registers get packed into the memory by the fitter
|
||||
// which means minimal resources are consumed (the result
|
||||
// is a altsyncram with registered outputs, available on
|
||||
// all modern Altera devices).
|
||||
//
|
||||
// This output stage acts as an extra slot in the FIFO,
|
||||
// and complicates the fill level.
|
||||
// --------------------------------------------------
|
||||
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
out_valid <= 0;
|
||||
out_payload <= 0;
|
||||
end
|
||||
else begin
|
||||
if (internal_out_ready) begin
|
||||
out_valid <= internal_out_valid & ok_to_forward;
|
||||
out_payload <= internal_out_payload;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin : gen_blk15_else
|
||||
always @* begin
|
||||
out_valid = internal_out_valid;
|
||||
out_payload = internal_out_payload;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------
|
||||
// Fill Level
|
||||
//
|
||||
// The fill level is calculated from the next write
|
||||
// and read pointers to avoid unnecessary latency
|
||||
// and logic.
|
||||
//
|
||||
// However, if the store-and-forward mode of the FIFO
|
||||
// is enabled, the fill level is an up-down counter
|
||||
// for fmax optimization reasons.
|
||||
//
|
||||
// If the output pipeline is enabled, the fill level
|
||||
// must account for it, or we'll always be off by one.
|
||||
// This may, or may not be important depending on the
|
||||
// application.
|
||||
//
|
||||
// For now, we'll always calculate the exact fill level
|
||||
// at the cost of an extra adder when the output stage
|
||||
// is enabled.
|
||||
// --------------------------------------------------
|
||||
generate if (USE_FILL_LEVEL) begin : gen_blk16
|
||||
wire [31:0] depth32;
|
||||
assign depth32 = DEPTH;
|
||||
|
||||
if (USE_STORE_FORWARD) begin
|
||||
|
||||
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
|
||||
|
||||
// --------------------------------------------------
|
||||
// We only drop on endofpacket. As long as we don't add to the fill
|
||||
// level on the dropped endofpacket cycle, we can simply subtract
|
||||
// (packet length - 1) from the fill level for dropped packets.
|
||||
// --------------------------------------------------
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
curr_packet_len_less_one <= 0;
|
||||
end else begin
|
||||
if (write) begin
|
||||
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
|
||||
if (in_endofpacket)
|
||||
curr_packet_len_less_one <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
fifo_fill_level <= 0;
|
||||
end else if (drop_on_error) begin
|
||||
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
|
||||
if (read)
|
||||
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
|
||||
end else if (write && !read) begin
|
||||
fifo_fill_level <= fifo_fill_level + 1'b1;
|
||||
end else if (read && !write) begin
|
||||
fifo_fill_level <= fifo_fill_level - 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset)
|
||||
fifo_fill_level <= 0;
|
||||
else if (next_full & !drop_on_error)
|
||||
fifo_fill_level <= depth32[ADDR_WIDTH:0];
|
||||
else begin
|
||||
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
|
||||
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @* begin
|
||||
fill_level = fifo_fill_level;
|
||||
|
||||
if (EMPTY_LATENCY == 3)
|
||||
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
|
||||
end
|
||||
end
|
||||
else begin : gen_blk16_else
|
||||
always @* begin
|
||||
fill_level = 0;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
|
||||
assign almost_full_data = (fill_level >= almost_full_threshold);
|
||||
end
|
||||
else
|
||||
assign almost_full_data = 0;
|
||||
endgenerate
|
||||
|
||||
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
|
||||
assign almost_empty_data = (fill_level <= almost_empty_threshold);
|
||||
end
|
||||
else
|
||||
assign almost_empty_data = 0;
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------
|
||||
// Avalon-MM Status & Control Connection Point
|
||||
//
|
||||
// Register map:
|
||||
//
|
||||
// | Addr | RW | 31 - 0 |
|
||||
// | 0 | R | Fill level |
|
||||
//
|
||||
// The registering of this connection point means
|
||||
// that there is a cycle of latency between
|
||||
// reads/writes and the updating of the fill level.
|
||||
// --------------------------------------------------
|
||||
generate if (USE_STORE_FORWARD) begin : gen_blk19
|
||||
assign max_fifo_size = FIFO_DEPTH - 1;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
almost_full_threshold <= max_fifo_size[23 : 0];
|
||||
almost_empty_threshold <= 0;
|
||||
cut_through_threshold <= 0;
|
||||
drop_on_error_en <= 0;
|
||||
csr_readdata <= 0;
|
||||
pkt_mode <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (csr_read) begin
|
||||
csr_readdata <= 32'b0;
|
||||
if (csr_address == 5)
|
||||
csr_readdata <= {31'b0, drop_on_error_en};
|
||||
else if (csr_address == 4)
|
||||
csr_readdata <= {8'b0, cut_through_threshold};
|
||||
else if (csr_address == 3)
|
||||
csr_readdata <= {8'b0, almost_empty_threshold};
|
||||
else if (csr_address == 2)
|
||||
csr_readdata <= {8'b0, almost_full_threshold};
|
||||
else if (csr_address == 0)
|
||||
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
|
||||
end
|
||||
else if (csr_write) begin
|
||||
if(csr_address == 3'b101)
|
||||
drop_on_error_en <= csr_writedata[0];
|
||||
else if(csr_address == 3'b100) begin
|
||||
cut_through_threshold <= csr_writedata[23:0];
|
||||
pkt_mode <= (csr_writedata[23:0] == 0);
|
||||
end
|
||||
else if(csr_address == 3'b011)
|
||||
almost_empty_threshold <= csr_writedata[23:0];
|
||||
else if(csr_address == 3'b010)
|
||||
almost_full_threshold <= csr_writedata[23:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
|
||||
assign max_fifo_size = FIFO_DEPTH - 1;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
almost_full_threshold <= max_fifo_size[23 : 0];
|
||||
almost_empty_threshold <= 0;
|
||||
csr_readdata <= 0;
|
||||
end
|
||||
else begin
|
||||
if (csr_read) begin
|
||||
csr_readdata <= 32'b0;
|
||||
if (csr_address == 3)
|
||||
csr_readdata <= {8'b0, almost_empty_threshold};
|
||||
else if (csr_address == 2)
|
||||
csr_readdata <= {8'b0, almost_full_threshold};
|
||||
else if (csr_address == 0)
|
||||
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
|
||||
end
|
||||
else if (csr_write) begin
|
||||
if(csr_address == 3'b011)
|
||||
almost_empty_threshold <= csr_writedata[23:0];
|
||||
else if(csr_address == 3'b010)
|
||||
almost_full_threshold <= csr_writedata[23:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin : gen_blk19_else2
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
csr_readdata <= 0;
|
||||
end
|
||||
else if (csr_read) begin
|
||||
csr_readdata <= 0;
|
||||
|
||||
if (csr_address == 0)
|
||||
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------
|
||||
// Store and forward logic
|
||||
// --------------------------------------------------
|
||||
// if the fifo gets full before the entire packet or the
|
||||
// cut-threshold condition is met then start sending out
|
||||
// data in order to avoid dead-lock situation
|
||||
|
||||
generate if (USE_STORE_FORWARD) begin : gen_blk20
|
||||
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
|
||||
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
|
||||
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
|
||||
~wait_for_threshold) | fifo_too_small_r;
|
||||
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
|
||||
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
|
||||
assign in_pkt_error = in_valid & in_ready & |in_error;
|
||||
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
|
||||
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
|
||||
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
|
||||
|
||||
// count packets coming and going into the fifo
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
pkt_cnt <= 0;
|
||||
pkt_has_started <= 0;
|
||||
sop_has_left_fifo <= 0;
|
||||
fifo_too_small_r <= 0;
|
||||
pkt_cnt_eq_zero <= 1'b1;
|
||||
pkt_cnt_eq_one <= 1'b0;
|
||||
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
|
||||
fifo_too_small_r <= fifo_too_small;
|
||||
|
||||
if( in_pkt_eop_arrive )
|
||||
sop_has_left_fifo <= 1'b0;
|
||||
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
|
||||
sop_has_left_fifo <= 1'b1;
|
||||
|
||||
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
|
||||
pkt_cnt <= pkt_cnt + 1'b1;
|
||||
pkt_cnt_eq_zero <= 0;
|
||||
if (pkt_cnt == 0)
|
||||
pkt_cnt_eq_one <= 1'b1;
|
||||
else
|
||||
pkt_cnt_eq_one <= 1'b0;
|
||||
end
|
||||
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
|
||||
pkt_cnt <= pkt_cnt - 1'b1;
|
||||
if (pkt_cnt == 1)
|
||||
pkt_cnt_eq_zero <= 1'b1;
|
||||
else
|
||||
pkt_cnt_eq_zero <= 1'b0;
|
||||
if (pkt_cnt == 2)
|
||||
pkt_cnt_eq_one <= 1'b1;
|
||||
else
|
||||
pkt_cnt_eq_one <= 1'b0;
|
||||
end
|
||||
|
||||
if (in_pkt_start)
|
||||
pkt_has_started <= 1'b1;
|
||||
else if (in_pkt_eop_arrive)
|
||||
pkt_has_started <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// drop on error logic
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
sop_ptr <= 0;
|
||||
error_in_pkt <= 0;
|
||||
end
|
||||
else begin
|
||||
// save the location of the SOP
|
||||
if ( in_pkt_start )
|
||||
sop_ptr <= wr_ptr;
|
||||
|
||||
// remember if error in pkt
|
||||
// log error only if packet has already started
|
||||
if (in_pkt_eop_arrive)
|
||||
error_in_pkt <= 1'b0;
|
||||
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
|
||||
error_in_pkt <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
|
||||
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
|
||||
|
||||
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
|
||||
|
||||
end
|
||||
else begin : gen_blk20_else
|
||||
assign ok_to_forward = 1'b1;
|
||||
assign drop_on_error = 1'b0;
|
||||
if (ADDR_WIDTH <= 1)
|
||||
assign curr_sop_ptr = 1'b0;
|
||||
else
|
||||
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Calculates the log2ceil of the input value
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input integer val;
|
||||
reg[31:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i[30:0] << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,210 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Bytes to Packet
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_bytes_to_packets
|
||||
//if ENCODING ==0, CHANNEL_WIDTH must be 8
|
||||
//else CHANNEL_WIDTH can be from 0 to 127
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0 )
|
||||
(
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST out with packets
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data,
|
||||
output reg [CHANNEL_WIDTH-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc, received_channel, received_varchannel;
|
||||
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
|
||||
|
||||
// data out mux.
|
||||
// we need it twice (data & channel out), so use a wire here
|
||||
wire [7:0] data_out;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign sop_char = (in_data == 8'h7a);
|
||||
assign eop_char = (in_data == 8'h7b);
|
||||
assign channel_char = (in_data == 8'h7c);
|
||||
assign escape_char = (in_data == 8'h7d);
|
||||
|
||||
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
// Synchorous block -- reset and registers
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
// we take data when in_valid and in_ready
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
//if we got esc char, after next byte is consumed, quit esc mode
|
||||
if (out_ready) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Combinational block for in_ready and out_valid
|
||||
always @* begin
|
||||
//we choose not to pipeline here. We can process special characters when
|
||||
//in_ready, but in a chain of microcores, backpressure path is usually
|
||||
//time critical, so we keep it simple here.
|
||||
in_ready = out_ready;
|
||||
|
||||
//out_valid when in_valid, except when we are processing the special
|
||||
//characters. However, if we are in escape received mode, then we are
|
||||
//valid
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
|
||||
end else begin
|
||||
assign varchannelesc_char = in_data[7];
|
||||
// Synchorous block -- reset and registers
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
received_channel <= 0;
|
||||
received_varchannel <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
// we take data when in_valid and in_ready
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
//if we got esc char, after next byte is consumed, quit esc mode
|
||||
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
if (channel_char & ENCODING ) received_varchannel <= 1;
|
||||
if (channel_char & ~ENCODING) received_channel <= 1;
|
||||
end
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
|
||||
received_channel <= 0;
|
||||
end
|
||||
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
received_varchannel <= 0;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Combinational block for in_ready and out_valid
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (received_esc) begin
|
||||
if (received_channel | received_varchannel) out_valid = 0;
|
||||
end else begin
|
||||
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
|
||||
end
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
// Channel block
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
always @(posedge clk) begin
|
||||
out_channel <= 'h0;
|
||||
end
|
||||
|
||||
end else if (CHANNEL_WIDTH < 8) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
// Shifting out only the required bits
|
||||
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
out_channel <= data_out;
|
||||
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
// Shifting out the lower 7 bits
|
||||
out_channel <= out_channel <<7;
|
||||
out_channel[6:0] <= data_out[6:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,141 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/20.1std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_clock_crosser(
|
||||
in_clk,
|
||||
in_reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_clk,
|
||||
out_reset,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter FORWARD_SYNC_DEPTH = 2;
|
||||
parameter BACKWARD_SYNC_DEPTH = 2;
|
||||
parameter USE_OUTPUT_PIPELINE = 1;
|
||||
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input in_clk;
|
||||
input in_reset;
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_clk;
|
||||
input out_reset;
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
// Data is guaranteed valid by control signal clock crossing. Cut data
|
||||
// buffer false path.
|
||||
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
|
||||
reg [DATA_WIDTH-1:0] out_data_buffer;
|
||||
|
||||
reg in_data_toggle;
|
||||
wire in_data_toggle_returned;
|
||||
wire out_data_toggle;
|
||||
reg out_data_toggle_flopped;
|
||||
|
||||
wire take_in_data;
|
||||
wire out_data_taken;
|
||||
|
||||
wire out_valid_internal;
|
||||
wire out_ready_internal;
|
||||
|
||||
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
|
||||
assign take_in_data = in_valid & in_ready;
|
||||
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
|
||||
assign out_data_taken = out_ready_internal & out_valid_internal;
|
||||
|
||||
always @(posedge in_clk or posedge in_reset) begin
|
||||
if (in_reset) begin
|
||||
in_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
in_data_toggle <= 1'b0;
|
||||
end else begin
|
||||
if (take_in_data) begin
|
||||
in_data_toggle <= ~in_data_toggle;
|
||||
in_data_buffer <= in_data;
|
||||
end
|
||||
end //in_reset
|
||||
end //in_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset) begin
|
||||
if (out_reset) begin
|
||||
out_data_toggle_flopped <= 1'b0;
|
||||
out_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
end else begin
|
||||
out_data_buffer <= in_data_buffer;
|
||||
if (out_data_taken) begin
|
||||
out_data_toggle_flopped <= out_data_toggle;
|
||||
end
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
|
||||
.clk(out_clk),
|
||||
.reset_n(~out_reset),
|
||||
.din(in_data_toggle),
|
||||
.dout(out_data_toggle)
|
||||
);
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
|
||||
.clk(in_clk),
|
||||
.reset_n(~in_reset),
|
||||
.din(out_data_toggle_flopped),
|
||||
.dout(in_data_toggle_returned)
|
||||
);
|
||||
|
||||
generate if (USE_OUTPUT_PIPELINE == 1) begin
|
||||
|
||||
altera_avalon_st_pipeline_base
|
||||
#(
|
||||
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
|
||||
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
|
||||
) output_stage (
|
||||
.clk(out_clk),
|
||||
.reset(out_reset),
|
||||
.in_ready(out_ready_internal),
|
||||
.in_valid(out_valid_internal),
|
||||
.in_data(out_data_buffer),
|
||||
.out_ready(out_ready),
|
||||
.out_valid(out_valid),
|
||||
.out_data(out_data)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign out_valid = out_valid_internal;
|
||||
assign out_ready_internal = out_ready;
|
||||
assign out_data = out_data_buffer;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,72 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Idle Inserter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_idle_inserter (
|
||||
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc;
|
||||
wire escape_char, idle_char;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign idle_char = (in_data == 8'h4a);
|
||||
assign escape_char = (in_data == 8'h4d);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
end else begin
|
||||
if (in_valid & out_ready) begin
|
||||
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
|
||||
received_esc <= 1;
|
||||
end else begin
|
||||
received_esc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
//we are always valid
|
||||
out_valid = 1'b1;
|
||||
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
|
||||
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
|
||||
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
|
||||
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
|
||||
in_data; //send data
|
||||
end
|
||||
endmodule
|
||||
@ -0,0 +1,70 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Idle Remover
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_idle_remover (
|
||||
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc;
|
||||
wire escape_char, idle_char;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign idle_char = (in_data == 8'h4a);
|
||||
assign escape_char = (in_data == 8'h4d);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
end else begin
|
||||
if (in_valid & in_ready) begin
|
||||
if (escape_char & ~received_esc) begin
|
||||
received_esc <= 1;
|
||||
end else if (out_valid) begin
|
||||
received_esc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
//out valid when in_valid. Except when we get idle or escape
|
||||
//however, if we have received an escape character, then we are valid
|
||||
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
|
||||
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
end
|
||||
endmodule
|
||||
@ -0,0 +1,14 @@
|
||||
# (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License Subscription
|
||||
# Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
# Intel or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
set_false_path -from [get_registers *altera_jtag_src_crosser:*|sink_data_buffer*] -to [get_registers *altera_jtag_src_crosser:*|src_data*]
|
||||
@ -0,0 +1,224 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// This top level module chooses between the original Altera-ST JTAG Interface
|
||||
// component in ACDS version 8.1 and before, and the new one with the PLI
|
||||
// Simulation mode turned on, which adds a wrapper over the original component.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_avalon_st_jtag_interface #(
|
||||
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
|
||||
// for JTAG Phy, 1 for Packets to Master
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = -1,
|
||||
parameter EXPORT_JTAG = 0,
|
||||
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
|
||||
parameter PLI_PORT = 50000 // PLI Simulation Port
|
||||
) (
|
||||
input wire jtag_tck,
|
||||
input wire jtag_tms,
|
||||
input wire jtag_tdi,
|
||||
output wire jtag_tdo,
|
||||
input wire jtag_ena,
|
||||
input wire jtag_usr1,
|
||||
input wire jtag_clr,
|
||||
input wire jtag_clrn,
|
||||
input wire jtag_state_tlr,
|
||||
input wire jtag_state_rti,
|
||||
input wire jtag_state_sdrs,
|
||||
input wire jtag_state_cdr,
|
||||
input wire jtag_state_sdr,
|
||||
input wire jtag_state_e1dr,
|
||||
input wire jtag_state_pdr,
|
||||
input wire jtag_state_e2dr,
|
||||
input wire jtag_state_udr,
|
||||
input wire jtag_state_sirs,
|
||||
input wire jtag_state_cir,
|
||||
input wire jtag_state_sir,
|
||||
input wire jtag_state_e1ir,
|
||||
input wire jtag_state_pir,
|
||||
input wire jtag_state_e2ir,
|
||||
input wire jtag_state_uir,
|
||||
input wire [2:0] jtag_ir_in,
|
||||
output wire jtag_irq,
|
||||
output wire [2:0] jtag_ir_out,
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
input wire source_ready,
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
output wire resetrequest,
|
||||
output wire debug_reset,
|
||||
output wire mgmt_valid,
|
||||
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output wire mgmt_data
|
||||
);
|
||||
|
||||
// Signals in the JTAG clock domain
|
||||
wire tck;
|
||||
wire tdi;
|
||||
wire tdo;
|
||||
wire [2:0] ir_in;
|
||||
wire virtual_state_cdr;
|
||||
wire virtual_state_sdr;
|
||||
wire virtual_state_udr;
|
||||
|
||||
assign jtag_irq = 1'b0;
|
||||
assign jtag_ir_out = 3'b000;
|
||||
|
||||
generate
|
||||
if (EXPORT_JTAG == 0) begin
|
||||
// SLD node instantiation
|
||||
altera_jtag_sld_node node (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_out (1'b0),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr (virtual_state_cdr),
|
||||
.virtual_state_cir (),
|
||||
.virtual_state_e1dr (),
|
||||
.virtual_state_e2dr (),
|
||||
.virtual_state_pdr (),
|
||||
.virtual_state_sdr (virtual_state_sdr),
|
||||
.virtual_state_udr (virtual_state_udr),
|
||||
.virtual_state_uir ()
|
||||
);
|
||||
|
||||
assign jtag_tdo = 1'b0;
|
||||
end else begin
|
||||
assign tck = jtag_tck;
|
||||
assign tdi = jtag_tdi;
|
||||
assign jtag_tdo = tdo;
|
||||
assign ir_in = jtag_ir_in;
|
||||
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
|
||||
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
|
||||
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (USE_PLI == 0)
|
||||
begin : normal
|
||||
altera_jtag_dc_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_dc_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.source_data(source_data),
|
||||
.source_valid(source_valid),
|
||||
.sink_data(sink_data),
|
||||
.sink_valid(sink_valid),
|
||||
.sink_ready(sink_ready),
|
||||
.resetrequest(resetrequest),
|
||||
.debug_reset(debug_reset),
|
||||
.mgmt_valid(mgmt_valid),
|
||||
.mgmt_channel(mgmt_channel),
|
||||
.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
end
|
||||
else
|
||||
begin : pli_mode
|
||||
|
||||
//synthesis translate_off
|
||||
reg pli_out_valid;
|
||||
reg pli_in_ready;
|
||||
reg [7 : 0] pli_out_data;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
pli_out_valid <= 0;
|
||||
pli_out_data <= 'b0;
|
||||
pli_in_ready <= 0;
|
||||
end
|
||||
else begin
|
||||
`ifdef MODEL_TECH
|
||||
$do_transaction(
|
||||
PLI_PORT,
|
||||
pli_out_valid,
|
||||
source_ready,
|
||||
pli_out_data,
|
||||
sink_valid,
|
||||
pli_in_ready,
|
||||
sink_data
|
||||
);
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
//synthesis translate_on
|
||||
wire [7:0] jtag_source_data;
|
||||
wire jtag_source_valid;
|
||||
wire jtag_sink_ready;
|
||||
wire jtag_resetrequest;
|
||||
|
||||
altera_jtag_dc_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_dc_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.source_data(jtag_source_data),
|
||||
.source_valid(jtag_source_valid),
|
||||
.sink_data(sink_data),
|
||||
.sink_valid(sink_valid),
|
||||
.sink_ready(jtag_sink_ready),
|
||||
.resetrequest(jtag_resetrequest)//,
|
||||
//.debug_reset(debug_reset),
|
||||
//.mgmt_valid(mgmt_valid),
|
||||
//.mgmt_channel(mgmt_channel),
|
||||
//.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
// synthesis read_comments_as_HDL on
|
||||
// assign source_valid = jtag_source_valid;
|
||||
// assign source_data = jtag_source_data;
|
||||
// assign sink_ready = jtag_sink_ready;
|
||||
// assign resetrequest = jtag_resetrequest;
|
||||
// synthesis read_comments_as_HDL off
|
||||
|
||||
//synthesis translate_off
|
||||
assign source_valid = pli_out_valid;
|
||||
assign source_data = pli_out_data;
|
||||
assign sink_ready = pli_in_ready;
|
||||
assign resetrequest = 1'b0;
|
||||
//synthesis translate_on
|
||||
assign jtag_tdo = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
@ -0,0 +1,253 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Packets to Bytes Component
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_packets_to_bytes
|
||||
//if ENCODING ==0, CHANNEL_WIDTH must be 8
|
||||
//else CHANNEL_WIDTH can be from 0 to 127
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0)
|
||||
(
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in with packets
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
input [CHANNEL_WIDTH-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
|
||||
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
|
||||
reg sent_esc, sent_sop, sent_eop;
|
||||
reg sent_channel_char, channel_escaped, sent_channel;
|
||||
reg [CHANNEL_WIDTH:0] stored_channel;
|
||||
reg [4:0] channel_count;
|
||||
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
|
||||
reg channel_needs_esc;
|
||||
|
||||
|
||||
|
||||
wire need_sop, need_eop, need_esc, need_channel;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign need_esc = (in_data === 8'h7a |
|
||||
in_data === 8'h7b |
|
||||
in_data === 8'h7c |
|
||||
in_data === 8'h7d );
|
||||
assign need_eop = (in_endofpacket);
|
||||
assign need_sop = (in_startofpacket);
|
||||
|
||||
|
||||
generate
|
||||
if( CHANNEL_WIDTH > 0) begin
|
||||
wire channel_changed;
|
||||
assign channel_changed = (in_channel != stored_channel);
|
||||
assign need_channel = (need_sop | channel_changed);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
channel_count <= 0;
|
||||
channel_needs_esc <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
channel_count <= CHN_COUNT[4:0];
|
||||
stored_varchannel <= in_channel;
|
||||
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
|
||||
channel_needs_esc <= (in_channel == 8'h7a |
|
||||
in_channel == 8'h7b |
|
||||
in_channel == 8'h7c |
|
||||
in_channel == 8'h7d );
|
||||
end
|
||||
end else if (channel_needs_esc & ~channel_escaped) begin
|
||||
out_data <= 8'h7d;
|
||||
channel_escaped <= 1;
|
||||
end else if (~sent_channel) begin
|
||||
if (ENCODING) begin
|
||||
// Sending out MSB=1, while not last 7 bits of Channel
|
||||
if (channel_count > 0) begin
|
||||
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
stored_varchannel <= stored_varchannel<<7;
|
||||
|
||||
channel_count <= channel_count - 1'b1;
|
||||
// check whether the last 7 bits need escape or not
|
||||
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
|
||||
channel_needs_esc <=
|
||||
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
|
||||
end
|
||||
end else begin
|
||||
// Sending out MSB=0, last 7 bits of Channel
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else begin
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= in_channel ^ 8'h20;
|
||||
end else out_data <= in_channel;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//channel related signals
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
//extra bit in stored_channel to force reset
|
||||
stored_channel <= {CHANNEL_WIDTH{1'b1}};
|
||||
end else begin
|
||||
//update stored_channel only when it is sent out
|
||||
if (sent_channel) stored_channel <= in_channel;
|
||||
end
|
||||
end
|
||||
always @* begin
|
||||
|
||||
// in_ready. Low when:
|
||||
// back pressured, or when
|
||||
// we are outputting a control character, which means that one of
|
||||
// {escape_char, start of packet, end of packet, channel}
|
||||
// needs to be, but has not yet, been handled.
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
assign need_channel = (need_sop);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
sent_channel <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
end else if (~sent_channel) begin
|
||||
out_data <= 'h0;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,139 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/20.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_base (
|
||||
clk,
|
||||
reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter PIPELINE_READY = 1;
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input clk;
|
||||
input reset;
|
||||
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
reg full0;
|
||||
reg full1;
|
||||
reg [DATA_WIDTH-1:0] data0;
|
||||
reg [DATA_WIDTH-1:0] data1;
|
||||
|
||||
assign out_valid = full1;
|
||||
assign out_data = data1;
|
||||
|
||||
generate if (PIPELINE_READY == 1)
|
||||
begin : REGISTERED_READY_PLINE
|
||||
|
||||
assign in_ready = !full0;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
data0 <= {DATA_WIDTH{1'b0}};
|
||||
data1 <= {DATA_WIDTH{1'b0}};
|
||||
end else begin
|
||||
// ----------------------------
|
||||
// always load the second slot if we can
|
||||
// ----------------------------
|
||||
if (~full0)
|
||||
data0 <= in_data;
|
||||
// ----------------------------
|
||||
// first slot is loaded either from the second,
|
||||
// or with new data
|
||||
// ----------------------------
|
||||
if (~full1 || (out_ready && out_valid)) begin
|
||||
if (full0)
|
||||
data1 <= data0;
|
||||
else
|
||||
data1 <= in_data;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
full0 <= 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
// no data in pipeline
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end // ~f1 & ~f0
|
||||
|
||||
// one datum in pipeline
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
// back to empty
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end // f1 & ~f0
|
||||
|
||||
// two data in pipeline
|
||||
if (full1 & full0) begin
|
||||
// go back to one datum state
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end // end go back to one datum stage
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
else
|
||||
begin : UNREGISTERED_READY_PLINE
|
||||
|
||||
// in_ready will be a pass through of the out_ready signal as it is not registered
|
||||
assign in_ready = (~full1) | out_ready;
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
@ -0,0 +1,166 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/20.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage.sv $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_stage #(
|
||||
parameter
|
||||
SYMBOLS_PER_BEAT = 1,
|
||||
BITS_PER_SYMBOL = 8,
|
||||
USE_PACKETS = 0,
|
||||
USE_EMPTY = 0,
|
||||
PIPELINE_READY = 1,
|
||||
|
||||
// Optional ST signal widths. Value "0" means no such port.
|
||||
CHANNEL_WIDTH = 0,
|
||||
ERROR_WIDTH = 0,
|
||||
|
||||
// Derived parameters
|
||||
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
|
||||
PACKET_WIDTH = 0,
|
||||
EMPTY_WIDTH = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
output in_ready,
|
||||
input in_valid,
|
||||
input [DATA_WIDTH - 1 : 0] in_data,
|
||||
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
|
||||
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
|
||||
|
||||
input out_ready,
|
||||
output out_valid,
|
||||
output [DATA_WIDTH - 1 : 0] out_data,
|
||||
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
|
||||
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
|
||||
output out_startofpacket,
|
||||
output out_endofpacket,
|
||||
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
|
||||
);
|
||||
localparam
|
||||
PAYLOAD_WIDTH =
|
||||
DATA_WIDTH +
|
||||
PACKET_WIDTH +
|
||||
CHANNEL_WIDTH +
|
||||
EMPTY_WIDTH +
|
||||
ERROR_WIDTH;
|
||||
|
||||
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
|
||||
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
|
||||
|
||||
// Assign in_data and other optional in_* interface signals to in_payload.
|
||||
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
|
||||
generate
|
||||
// optional packet inputs
|
||||
if (PACKET_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH - 1 :
|
||||
DATA_WIDTH
|
||||
] = {in_startofpacket, in_endofpacket};
|
||||
end
|
||||
// optional channel input
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
] = in_channel;
|
||||
end
|
||||
// optional empty input
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
] = in_empty;
|
||||
end
|
||||
// optional error input
|
||||
if (ERROR_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
] = in_error;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (PAYLOAD_WIDTH),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (in_ready),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (out_valid),
|
||||
.out_data (out_payload)
|
||||
);
|
||||
|
||||
// Assign out_data and other optional out_* interface signals from out_payload.
|
||||
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
|
||||
generate
|
||||
// optional packet outputs
|
||||
if (PACKET_WIDTH) begin
|
||||
assign {out_startofpacket, out_endofpacket} =
|
||||
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign {out_startofpacket, out_endofpacket} = 2'b0;
|
||||
end
|
||||
|
||||
// optional channel output
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign out_channel = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_channel = 1'b0;
|
||||
end
|
||||
// optional empty output
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign out_empty = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_empty = 1'b0;
|
||||
end
|
||||
// optional error output
|
||||
if (ERROR_WIDTH) begin
|
||||
assign out_error = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_error = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -0,0 +1,261 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// This module is a simple clock crosser for control signals. It will take
|
||||
// the asynchronous control signal and synchronize it to the clk domain
|
||||
// attached to the clk input. It does so by passing the control signal
|
||||
// through a pair of registers and then sensing the level transition from
|
||||
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
|
||||
// that the control signal will always transition every time is asserted.
|
||||
// i.e.:
|
||||
// ____ ___________________
|
||||
// -> ___| |___ and ___| |_____
|
||||
//
|
||||
// on the control signal will be seen as only one assertion of the control
|
||||
// signal. In short, if your control could be asserted back-to-back, then
|
||||
// don't use this module. You'll be losing data.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_jtag_control_signal_crosser (
|
||||
clk,
|
||||
reset_n,
|
||||
async_control_signal,
|
||||
sense_pos_edge,
|
||||
sync_control_signal
|
||||
);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input async_control_signal;
|
||||
input sense_pos_edge;
|
||||
output sync_control_signal;
|
||||
|
||||
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
|
||||
|
||||
reg sync_control_signal;
|
||||
|
||||
wire synchronized_raw_signal;
|
||||
reg edge_detector_register;
|
||||
|
||||
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.din(async_control_signal),
|
||||
.dout(synchronized_raw_signal)
|
||||
);
|
||||
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
if (~reset_n)
|
||||
edge_detector_register <= 1'b0;
|
||||
else
|
||||
edge_detector_register <= synchronized_raw_signal;
|
||||
|
||||
always @* begin
|
||||
if (sense_pos_edge)
|
||||
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
|
||||
else
|
||||
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
|
||||
end
|
||||
endmodule
|
||||
|
||||
// This module crosses the clock domain for a given source
|
||||
module altera_jtag_src_crosser (
|
||||
sink_clk,
|
||||
sink_reset_n,
|
||||
sink_valid,
|
||||
sink_data,
|
||||
src_clk,
|
||||
src_reset_n,
|
||||
src_valid,
|
||||
src_data
|
||||
);
|
||||
parameter WIDTH = 8;
|
||||
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
|
||||
|
||||
input sink_clk;
|
||||
input sink_reset_n;
|
||||
input sink_valid;
|
||||
input [WIDTH-1:0] sink_data;
|
||||
input src_clk;
|
||||
input src_reset_n;
|
||||
output src_valid;
|
||||
output [WIDTH-1:0] src_data;
|
||||
|
||||
reg sink_valid_buffer;
|
||||
reg [WIDTH-1:0] sink_data_buffer;
|
||||
|
||||
reg src_valid;
|
||||
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
|
||||
|
||||
wire synchronized_valid;
|
||||
|
||||
altera_jtag_control_signal_crosser #(
|
||||
.SYNC_DEPTH(SYNC_DEPTH)
|
||||
) crosser (
|
||||
.clk(src_clk),
|
||||
.reset_n(src_reset_n),
|
||||
.async_control_signal(sink_valid_buffer),
|
||||
.sense_pos_edge(1'b1),
|
||||
.sync_control_signal(synchronized_valid)
|
||||
);
|
||||
always @ (posedge sink_clk or negedge sink_reset_n) begin
|
||||
if (~sink_reset_n) begin
|
||||
sink_valid_buffer <= 1'b0;
|
||||
sink_data_buffer <= 'b0;
|
||||
end else begin
|
||||
sink_valid_buffer <= sink_valid;
|
||||
if (sink_valid) begin
|
||||
sink_data_buffer <= sink_data;
|
||||
end
|
||||
end //end if
|
||||
end //always sink_clk
|
||||
|
||||
always @ (posedge src_clk or negedge src_reset_n) begin
|
||||
if (~src_reset_n) begin
|
||||
src_valid <= 1'b0;
|
||||
src_data <= {WIDTH{1'b0}};
|
||||
end else begin
|
||||
src_valid <= synchronized_valid;
|
||||
src_data <= synchronized_valid ? sink_data_buffer : src_data;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module altera_jtag_dc_streaming #(
|
||||
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
|
||||
// for JTAG Phy, 1 for Packets to Master
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = -1
|
||||
) (
|
||||
// Signals in the JTAG clock domain
|
||||
input wire tck,
|
||||
input wire tdi,
|
||||
output wire tdo,
|
||||
input wire [2:0] ir_in,
|
||||
input wire virtual_state_cdr,
|
||||
input wire virtual_state_sdr,
|
||||
input wire virtual_state_udr,
|
||||
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
output wire resetrequest,
|
||||
output wire debug_reset,
|
||||
output wire mgmt_valid,
|
||||
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output wire mgmt_data
|
||||
);
|
||||
|
||||
// the tck to sysclk sync depth is fixed at 8
|
||||
// 8 is the worst case scenario from our metastability analysis, and since
|
||||
// using TCK serially is so slow we should have plenty of clock cycles.
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
|
||||
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
|
||||
// Since the tck clock is so slow, no parameter is exposed.
|
||||
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
|
||||
|
||||
wire jtag_clock_reset_n; // system reset is synchronized with tck
|
||||
wire [7:0] jtag_source_data;
|
||||
wire jtag_source_valid;
|
||||
wire [7:0] jtag_sink_data;
|
||||
wire jtag_sink_valid;
|
||||
wire jtag_sink_ready;
|
||||
|
||||
/* Reset Synchronizer module.
|
||||
*
|
||||
* The SLD Node does not provide a reset for the TCK clock domain.
|
||||
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
|
||||
* internal states need to be reset to 0 in order to guarantee proper
|
||||
* functionality throughout resets.
|
||||
*
|
||||
* This reset block will asynchronously assert reset, and synchronously
|
||||
* deassert reset for the tck clock domain.
|
||||
*/
|
||||
altera_std_synchronizer #(
|
||||
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
|
||||
) synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(reset_n),
|
||||
.din(1'b1),
|
||||
.dout(jtag_clock_reset_n)
|
||||
);
|
||||
|
||||
altera_jtag_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
|
||||
.reset_n(jtag_clock_reset_n),
|
||||
.source_data(jtag_source_data),
|
||||
.source_valid(jtag_source_valid),
|
||||
.sink_data(jtag_sink_data),
|
||||
.sink_valid(jtag_sink_valid),
|
||||
.sink_ready(jtag_sink_ready),
|
||||
.clock_to_sample(clk),
|
||||
.reset_to_sample(reset_n),
|
||||
.resetrequest(resetrequest),
|
||||
.debug_reset(debug_reset),
|
||||
.mgmt_valid(mgmt_valid),
|
||||
.mgmt_channel(mgmt_channel),
|
||||
.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
|
||||
|
||||
altera_avalon_st_clock_crosser #(
|
||||
.SYMBOLS_PER_BEAT(1),
|
||||
.BITS_PER_SYMBOL(8),
|
||||
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
|
||||
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
|
||||
) sink_crosser (
|
||||
.in_clk(clk),
|
||||
.in_reset(~reset_n),
|
||||
.in_data(sink_data),
|
||||
.in_ready(sink_ready),
|
||||
.in_valid(sink_valid),
|
||||
.out_clk(tck),
|
||||
.out_reset(~jtag_clock_reset_n),
|
||||
.out_data(jtag_sink_data),
|
||||
.out_ready(jtag_sink_ready),
|
||||
.out_valid(jtag_sink_valid)
|
||||
);
|
||||
|
||||
altera_jtag_src_crosser #(
|
||||
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
|
||||
) source_crosser (
|
||||
.sink_clk(tck),
|
||||
.sink_reset_n(jtag_clock_reset_n),
|
||||
.sink_valid(jtag_source_valid),
|
||||
.sink_data(jtag_source_data),
|
||||
.src_clk(clk),
|
||||
.src_reset_n(reset_n),
|
||||
.src_valid(source_valid),
|
||||
.src_data(source_data)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,261 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ns / 1 ns
|
||||
// synopsys translate_on
|
||||
module altera_jtag_sld_node (
|
||||
ir_out,
|
||||
tdo,
|
||||
ir_in,
|
||||
tck,
|
||||
tdi,
|
||||
virtual_state_cdr,
|
||||
virtual_state_cir,
|
||||
virtual_state_e1dr,
|
||||
virtual_state_e2dr,
|
||||
virtual_state_pdr,
|
||||
virtual_state_sdr,
|
||||
virtual_state_udr,
|
||||
virtual_state_uir
|
||||
);
|
||||
|
||||
parameter TCK_FREQ_MHZ = 20;
|
||||
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
|
||||
localparam IRWIDTH = 3;
|
||||
|
||||
input [IRWIDTH - 1:0] ir_out;
|
||||
input tdo;
|
||||
output reg [IRWIDTH - 1:0] ir_in;
|
||||
output tck;
|
||||
output reg tdi = 1'b0;
|
||||
output virtual_state_cdr;
|
||||
output virtual_state_cir;
|
||||
output virtual_state_e1dr;
|
||||
output virtual_state_e2dr;
|
||||
output virtual_state_pdr;
|
||||
output virtual_state_sdr;
|
||||
output virtual_state_udr;
|
||||
output virtual_state_uir;
|
||||
|
||||
// PHY Simulation signals
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
reg simulation_clock;
|
||||
reg sdrs;
|
||||
reg cdr;
|
||||
reg sdr;
|
||||
reg e1dr;
|
||||
reg udr;
|
||||
reg [7:0] bit_index;
|
||||
`endif
|
||||
|
||||
|
||||
// PHY Instantiation
|
||||
`ifdef ALTERA_RESERVED_QIS
|
||||
wire tdi_port;
|
||||
wire [IRWIDTH - 1:0] ir_in_port;
|
||||
always @(tdi_port)
|
||||
tdi = tdi_port;
|
||||
always @(ir_in_port)
|
||||
ir_in = ir_in_port;
|
||||
sld_virtual_jtag_basic sld_virtual_jtag_component (
|
||||
.ir_out (ir_out),
|
||||
.tdo (tdo),
|
||||
.tdi (tdi_port),
|
||||
.tck (tck),
|
||||
.ir_in (ir_in_port),
|
||||
.virtual_state_cir (virtual_state_cir),
|
||||
.virtual_state_pdr (virtual_state_pdr),
|
||||
.virtual_state_uir (virtual_state_uir),
|
||||
.virtual_state_sdr (virtual_state_sdr),
|
||||
.virtual_state_cdr (virtual_state_cdr),
|
||||
.virtual_state_udr (virtual_state_udr),
|
||||
.virtual_state_e1dr (virtual_state_e1dr),
|
||||
.virtual_state_e2dr (virtual_state_e2dr)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.jtag_state_cdr (),
|
||||
.jtag_state_cir (),
|
||||
.jtag_state_e1dr (),
|
||||
.jtag_state_e1ir (),
|
||||
.jtag_state_e2dr (),
|
||||
.jtag_state_e2ir (),
|
||||
.jtag_state_pdr (),
|
||||
.jtag_state_pir (),
|
||||
.jtag_state_rti (),
|
||||
.jtag_state_sdr (),
|
||||
.jtag_state_sdrs (),
|
||||
.jtag_state_sir (),
|
||||
.jtag_state_sirs (),
|
||||
.jtag_state_tlr (),
|
||||
.jtag_state_udr (),
|
||||
.jtag_state_uir (),
|
||||
.tms ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
sld_virtual_jtag_component.sld_mfg_id = 110,
|
||||
sld_virtual_jtag_component.sld_type_id = 132,
|
||||
sld_virtual_jtag_component.sld_version = 1,
|
||||
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
|
||||
sld_virtual_jtag_component.sld_instance_index = 0,
|
||||
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
|
||||
sld_virtual_jtag_component.sld_sim_action = "",
|
||||
sld_virtual_jtag_component.sld_sim_n_scan = 0,
|
||||
sld_virtual_jtag_component.sld_sim_total_length = 0;
|
||||
`endif
|
||||
|
||||
// PHY Simulation
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
|
||||
localparam DATA = 0;
|
||||
localparam LOOPBACK = 1;
|
||||
localparam DEBUG = 2;
|
||||
localparam INFO = 3;
|
||||
localparam CONTROL = 4;
|
||||
localparam MGMT = 5;
|
||||
|
||||
always
|
||||
//#TCK_HALF_PERIOD_US simulation_clock = $random;
|
||||
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
|
||||
|
||||
assign tck = simulation_clock;
|
||||
assign virtual_state_cdr = cdr;
|
||||
assign virtual_state_sdr = sdr;
|
||||
assign virtual_state_e1dr = e1dr;
|
||||
assign virtual_state_udr = udr;
|
||||
|
||||
task reset_jtag_state;
|
||||
begin
|
||||
simulation_clock = 0;
|
||||
enter_data_mode;
|
||||
clear_states_async;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_data_mode;
|
||||
begin
|
||||
ir_in = DATA;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_loopback_mode;
|
||||
begin
|
||||
ir_in = LOOPBACK;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_debug_mode;
|
||||
begin
|
||||
ir_in = DEBUG;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_info_mode;
|
||||
begin
|
||||
ir_in = INFO;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_control_mode;
|
||||
begin
|
||||
ir_in = CONTROL;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_mgmt_mode;
|
||||
begin
|
||||
ir_in = MGMT;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_sdrs_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_cdr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_e1dr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_udr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_states;
|
||||
begin
|
||||
clear_states_async;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_states_async;
|
||||
begin
|
||||
{cdr, sdr, e1dr, udr} = 4'b0000;
|
||||
end
|
||||
endtask
|
||||
|
||||
task shift_one_bit;
|
||||
input bit_to_send;
|
||||
output reg bit_received;
|
||||
begin
|
||||
{cdr, sdr, e1dr, udr} = 4'b0100;
|
||||
tdi = bit_to_send;
|
||||
@(posedge tck);
|
||||
bit_received = tdo;
|
||||
end
|
||||
endtask
|
||||
|
||||
task shift_one_byte;
|
||||
input [7:0] byte_to_send;
|
||||
output reg [7:0] byte_received;
|
||||
integer i;
|
||||
reg bit_received;
|
||||
begin
|
||||
for (i=0; i<8; i=i+1)
|
||||
begin
|
||||
bit_index = i;
|
||||
shift_one_bit(byte_to_send[i], bit_received);
|
||||
byte_received[i] = bit_received;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,634 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ns / 1 ns
|
||||
// synopsys translate_on
|
||||
|
||||
module altera_jtag_streaming #(
|
||||
parameter PURPOSE = 0,
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = -1
|
||||
) (
|
||||
// JTAG Signals
|
||||
input wire tck,
|
||||
input wire tdi,
|
||||
output reg tdo,
|
||||
input wire [2:0] ir_in,
|
||||
input wire virtual_state_cdr,
|
||||
input wire virtual_state_sdr,
|
||||
input wire virtual_state_udr,
|
||||
|
||||
input wire reset_n,
|
||||
// Source Signals
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
// Sink Signals
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
// Clock Debug Signals
|
||||
input wire clock_to_sample,
|
||||
input wire reset_to_sample,
|
||||
// Resetrequest signal
|
||||
output reg resetrequest,
|
||||
// Debug reset and management channel
|
||||
output wire debug_reset,
|
||||
output reg mgmt_valid,
|
||||
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output reg mgmt_data
|
||||
);
|
||||
|
||||
// function to calculate log2, floored.
|
||||
function integer flog2;
|
||||
input [31:0] Depth;
|
||||
integer i;
|
||||
begin
|
||||
i = Depth;
|
||||
if ( i <= 0 ) flog2 = 0;
|
||||
else begin
|
||||
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
end
|
||||
endfunction // flog2
|
||||
|
||||
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
|
||||
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
|
||||
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
|
||||
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
|
||||
|
||||
// IR values determine the operating modes
|
||||
localparam DATA = 0;
|
||||
localparam LOOPBACK = 1;
|
||||
localparam DEBUG = 2;
|
||||
localparam INFO = 3;
|
||||
localparam CONTROL = 4;
|
||||
localparam MGMT = 5;
|
||||
|
||||
// Operating Modes:
|
||||
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
|
||||
// Loopback - To become a JTAG loopback with a bypass register
|
||||
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
|
||||
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
|
||||
// Control - To set the offset of bit-padding and to do a reset request
|
||||
// Mgmt - Send management commands (resets mostly) to agents
|
||||
|
||||
localparam IRWIDTH = 3;
|
||||
|
||||
// State machine encoding for write_state
|
||||
localparam ST_BYPASS = 'h0;
|
||||
localparam ST_HEADER_1 = 'h1;
|
||||
localparam ST_HEADER_2 = 'h2;
|
||||
localparam ST_WRITE_DATA = 'h3;
|
||||
|
||||
// State machine encoding for read_state
|
||||
localparam ST_HEADER = 'h0;
|
||||
localparam ST_PADDED = 'h1;
|
||||
localparam ST_READ_DATA = 'h2;
|
||||
|
||||
reg [1:0] write_state = ST_BYPASS;
|
||||
reg [1:0] read_state = ST_HEADER;
|
||||
|
||||
reg [ 7:0] dr_data_in = 'b0;
|
||||
reg [ 7:0] dr_data_out = 'b0;
|
||||
reg dr_loopback = 'b0;
|
||||
reg [ 2:0] dr_debug = 'b0;
|
||||
reg [10:0] dr_info = 'b0;
|
||||
reg [ 8:0] dr_control = 'b0;
|
||||
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
|
||||
|
||||
reg [ 8:0] padded_bit_counter = 'b0;
|
||||
reg [ 7:0] bypass_bit_counter = 'b0;
|
||||
reg [ 2:0] write_data_bit_counter = 'b0;
|
||||
reg [ 2:0] read_data_bit_counter = 'b0;
|
||||
reg [ 3:0] header_in_bit_counter = 'b0;
|
||||
reg [ 3:0] header_out_bit_counter = 'b0;
|
||||
reg [18:0] scan_length_byte_counter = 'b0;
|
||||
reg [18:0] valid_write_data_length_byte_counter = 'b0;
|
||||
|
||||
reg write_data_valid = 'b0;
|
||||
reg read_data_valid = 'b0;
|
||||
reg read_data_all_valid = 'b0;
|
||||
|
||||
reg decode_header_1 = 'b0;
|
||||
reg decode_header_2 = 'b0;
|
||||
|
||||
wire write_data_byte_aligned;
|
||||
wire read_data_byte_aligned;
|
||||
wire padded_bit_byte_aligned;
|
||||
wire bytestream_end;
|
||||
|
||||
assign write_data_byte_aligned = (write_data_bit_counter == 1);
|
||||
assign read_data_byte_aligned = (read_data_bit_counter == 1);
|
||||
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
|
||||
assign bytestream_end = (scan_length_byte_counter == 'b0);
|
||||
|
||||
reg [ 7:0] offset = 'b0;
|
||||
reg [15:0] header_in = 'b0;
|
||||
|
||||
reg [9:0] scan_length = 'b0;
|
||||
reg [2:0] read_data_length = 'b0;
|
||||
reg [2:0] write_data_length = 'b0;
|
||||
|
||||
wire [7:0] idle_inserter_sink_data;
|
||||
wire idle_inserter_sink_valid;
|
||||
wire idle_inserter_sink_ready;
|
||||
wire [7:0] idle_inserter_source_data;
|
||||
reg idle_inserter_source_ready = 'b0;
|
||||
reg [7:0] idle_remover_sink_data = 'b0;
|
||||
reg idle_remover_sink_valid = 'b0;
|
||||
wire [7:0] idle_remover_source_data;
|
||||
wire idle_remover_source_valid;
|
||||
|
||||
assign source_data = idle_remover_source_data;
|
||||
assign source_valid = idle_remover_source_valid;
|
||||
assign sink_ready = idle_inserter_sink_ready;
|
||||
assign idle_inserter_sink_data = sink_data;
|
||||
assign idle_inserter_sink_valid = sink_valid;
|
||||
|
||||
reg clock_sensor = 'b0;
|
||||
reg clock_to_sample_div2 = 'b0;
|
||||
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
|
||||
|
||||
wire data_available;
|
||||
|
||||
assign data_available = sink_valid;
|
||||
|
||||
wire [18:0] decoded_scan_length;
|
||||
wire [18:0] decoded_write_data_length;
|
||||
wire [18:0] decoded_read_data_length;
|
||||
|
||||
assign decoded_scan_length = { scan_length, {8{1'b1}} };
|
||||
// +-------------------+----------------+---------------------+
|
||||
// | scan_length | Length (bytes) | decoded_scan_length |
|
||||
// +-------------------+----------------+---------------------+
|
||||
// | 0x0 | 256 | 0x0ff (255) |
|
||||
// | 0x1 | 512 | 0x1ff (511) |
|
||||
// | 0x2 | 768 | 0x2ff (767) |
|
||||
// | . | . | . |
|
||||
// | 0x3ff | 256k | 0x3ff (256k-1) |
|
||||
// +-------------------+----------------+---------------------+
|
||||
|
||||
// TODO: use look up table to save LEs?
|
||||
// Decoded value is correct except for 0x7
|
||||
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
|
||||
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
|
||||
// +-------------------+---------------+---------------------------+
|
||||
// | read_data_length | Length | decoded_read_data_length |
|
||||
// | write_data_length | (bytes) | decoded_write_data_length |
|
||||
// +-------------------+---------------+---------------------------+
|
||||
// | 0x0 | 0 | 0x0000 (0) |
|
||||
// | 0x1 | 256 | 0x0100 (256) |
|
||||
// | 0x2 | 512 | 0x0200 (512) |
|
||||
// | 0x3 | 1k | 0x0400 (1024) |
|
||||
// | 0x4 | 2k | 0x0800 (2048) |
|
||||
// | 0x5 | 4k | 0x1000 (4096) |
|
||||
// | 0x6 | 8k | 0x2000 (8192) |
|
||||
// | 0x7 | scan_length | invalid |
|
||||
// +-------------------+---------------+---------------------------+
|
||||
|
||||
wire clock_sensor_sync;
|
||||
wire reset_to_sample_sync;
|
||||
wire clock_to_sample_div2_sync;
|
||||
wire clock_sense_reset_n_sync;
|
||||
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(clock_sensor),
|
||||
.dout(clock_sensor_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(reset_to_sample),
|
||||
.dout(reset_to_sample_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(clock_to_sample_div2),
|
||||
.dout(clock_to_sample_div2_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(clock_sense_reset_n),
|
||||
.din(1'b1),
|
||||
.dout(clock_sense_reset_n_sync));
|
||||
|
||||
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
|
||||
if (~clock_sense_reset_n_sync) begin
|
||||
clock_sensor <= 1'b0;
|
||||
end else begin
|
||||
clock_sensor <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clock_to_sample) begin
|
||||
clock_to_sample_div2 <= ~clock_to_sample_div2;
|
||||
end
|
||||
|
||||
always @ (posedge tck) begin
|
||||
|
||||
idle_remover_sink_valid <= 1'b0;
|
||||
idle_inserter_source_ready <= 1'b0;
|
||||
|
||||
// Data mode sourcing (write)
|
||||
|
||||
// offset(rounded 8) m-i i 16 offset
|
||||
// +------------+-----------+------------------+--------+------------+
|
||||
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
|
||||
// +------------+-----------+------------------+--------+------------+
|
||||
// Data mode DR data stream write format (as seen by hardware)
|
||||
//
|
||||
if (ir_in == DATA) begin
|
||||
|
||||
|
||||
if (virtual_state_cdr) begin
|
||||
if (offset == 'b0) begin
|
||||
write_state <= ST_HEADER_1;
|
||||
end else begin
|
||||
write_state <= ST_BYPASS;
|
||||
end
|
||||
// 8-bit bypass_bit_counter
|
||||
bypass_bit_counter <= offset;
|
||||
// 4-bit header_in_bit_counter
|
||||
header_in_bit_counter <= 15;
|
||||
// 3-bit write_data_bit_counter
|
||||
write_data_bit_counter <= 0;
|
||||
// Reset the registers
|
||||
// TODO: not necessarily all, reduce LE
|
||||
decode_header_1 <= 1'b0;
|
||||
decode_header_2 <= 1'b0;
|
||||
read_data_all_valid <= 1'b0;
|
||||
valid_write_data_length_byte_counter <= 0;
|
||||
end
|
||||
|
||||
if (virtual_state_sdr) begin
|
||||
// Discard bypass bits, then decode the 16-bit header
|
||||
// 3 3 10
|
||||
// +-------------------+------------------+-------------+
|
||||
// | write_data_length | read_data_length | scan_length |
|
||||
// +-------------------+------------------+-------------+
|
||||
// Header format
|
||||
|
||||
case (write_state)
|
||||
ST_BYPASS: begin
|
||||
// Discard the bypass bit
|
||||
bypass_bit_counter <= bypass_bit_counter - 1'b1;
|
||||
if (bypass_bit_counter == 1) begin
|
||||
write_state <= ST_HEADER_1;
|
||||
end
|
||||
end
|
||||
// Shift the scan_length and read_data_length
|
||||
ST_HEADER_1: begin
|
||||
// TODO: header_in can be shorter
|
||||
// Shift into header_in
|
||||
header_in <= {tdi, header_in[15:1]};
|
||||
header_in_bit_counter <= header_in_bit_counter - 1'b1;
|
||||
if (header_in_bit_counter == 3) begin
|
||||
read_data_length <= {tdi, header_in[15:14]};
|
||||
scan_length <= header_in[13:4];
|
||||
write_state <= ST_HEADER_2;
|
||||
decode_header_1 <= 1'b1;
|
||||
end
|
||||
end
|
||||
// Shift the write_data_length
|
||||
ST_HEADER_2: begin
|
||||
// Shift into header_in
|
||||
header_in <= {tdi, header_in[15:1]};
|
||||
header_in_bit_counter <= header_in_bit_counter - 1'b1;
|
||||
// Decode read_data_length and scan_length
|
||||
if (decode_header_1) begin
|
||||
decode_header_1 <= 1'b0;
|
||||
// Set read_data_all_valid
|
||||
if (read_data_length == 3'b111) begin
|
||||
read_data_all_valid <= 1'b1;
|
||||
end
|
||||
// Load scan_length_byte_counter
|
||||
scan_length_byte_counter <= decoded_scan_length;
|
||||
end
|
||||
if (header_in_bit_counter == 0) begin
|
||||
write_data_length <= {tdi, header_in[15:14]};
|
||||
write_state <= ST_WRITE_DATA;
|
||||
decode_header_2 <= 1'b1;
|
||||
end
|
||||
end
|
||||
// Shift the valid_write_data
|
||||
ST_WRITE_DATA: begin
|
||||
// Shift into dr_data_in
|
||||
dr_data_in <= {tdi, dr_data_in[7:1]};
|
||||
// Decode write_data_length
|
||||
if (decode_header_2) begin
|
||||
decode_header_2 <= 1'b0;
|
||||
// Load valid_write_data_length_byte_counter
|
||||
case (write_data_length)
|
||||
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
|
||||
3'b000: valid_write_data_length_byte_counter <= 'b0;
|
||||
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
|
||||
endcase
|
||||
end
|
||||
write_data_bit_counter <= write_data_bit_counter - 1'b1;
|
||||
write_data_valid <= (valid_write_data_length_byte_counter != 0);
|
||||
// Feed the data to the idle remover
|
||||
if (write_data_byte_aligned && write_data_valid) begin
|
||||
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
|
||||
idle_remover_sink_valid <= 1'b1;
|
||||
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Data mode sinking (read)
|
||||
|
||||
// i m-i offset(rounded 8) 16
|
||||
// +-----------------+-----------+------------+--------+
|
||||
// | valid_read_data | undefined | padded_bit | header | -> tdo
|
||||
// +-----------------+-----------+------------+--------+
|
||||
// Data mode DR data stream read format (as seen by hardware)
|
||||
//
|
||||
if (ir_in == DATA) begin
|
||||
|
||||
if (virtual_state_cdr) begin
|
||||
|
||||
read_state <= ST_HEADER;
|
||||
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
|
||||
// 9-bit padded_bit_counter
|
||||
if (|offset[2:0]) begin
|
||||
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
|
||||
padded_bit_counter[2:0] <= 3'b0;
|
||||
end else begin
|
||||
padded_bit_counter <= {1'b0, offset};
|
||||
end
|
||||
// 4-bit header_out_bit_counter
|
||||
header_out_bit_counter <= 0;
|
||||
// 3-bit read_data_bit_counter
|
||||
read_data_bit_counter <= 0;
|
||||
// Load the data_available bit into header
|
||||
dr_data_out <= {{7{1'b0}}, data_available};
|
||||
read_data_valid <= 0;
|
||||
|
||||
end
|
||||
|
||||
if (virtual_state_sdr) begin
|
||||
// 10 1
|
||||
// +-----------------------------------+----------------+
|
||||
// | reserved | data_available |
|
||||
// +-----------------------------------+----------------+
|
||||
// Header format
|
||||
|
||||
dr_data_out <= {1'b0, dr_data_out[7:1]};
|
||||
case (read_state)
|
||||
// Shift the scan_length and read_data_length
|
||||
ST_HEADER: begin
|
||||
header_out_bit_counter <= header_out_bit_counter - 1'b1;
|
||||
// Retrieve data from idle inserter for the next shift if no paddded bits
|
||||
if (header_out_bit_counter == 2) begin
|
||||
if (padded_bit_counter == 0) begin
|
||||
idle_inserter_source_ready <= read_data_all_valid;
|
||||
end
|
||||
end
|
||||
if (header_out_bit_counter == 1) begin
|
||||
if (padded_bit_counter == 0) begin
|
||||
read_state <= ST_READ_DATA;
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
|
||||
end else begin
|
||||
read_state <= ST_PADDED;
|
||||
padded_bit_counter <= padded_bit_counter - 1'b1;
|
||||
idle_inserter_source_ready <= 1'b0;
|
||||
dr_data_out <= 8'h4a;
|
||||
end
|
||||
end
|
||||
end
|
||||
ST_PADDED: begin
|
||||
padded_bit_counter <= padded_bit_counter - 1'b1;
|
||||
if (padded_bit_byte_aligned) begin
|
||||
// Load idle character into data register
|
||||
dr_data_out <= 8'h4a;
|
||||
end
|
||||
// Retrieve data from idle inserter for the next shift when padded bits finish
|
||||
if (padded_bit_counter == 1) begin
|
||||
idle_inserter_source_ready <= read_data_all_valid;
|
||||
end
|
||||
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
|
||||
read_state <= ST_READ_DATA;
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
|
||||
end
|
||||
end
|
||||
ST_READ_DATA: begin
|
||||
read_data_bit_counter <= read_data_bit_counter - 1'b1;
|
||||
// Retrieve data from idle inserter just before read_data_byte_aligned
|
||||
if (read_data_bit_counter == 2) begin
|
||||
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
|
||||
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
|
||||
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
|
||||
end
|
||||
if (read_data_byte_aligned) begin
|
||||
// Note that bytestream_end is driven by scan_length_byte_counter
|
||||
if (~bytestream_end) begin
|
||||
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
|
||||
end
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
// Load idle character if bytestream has ended, else get data from the idle inserter
|
||||
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Loopback mode
|
||||
if (ir_in == LOOPBACK) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_loopback <= 1'b0; // capture 0
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_loopback
|
||||
dr_loopback <= tdi;
|
||||
end
|
||||
end
|
||||
|
||||
// Debug mode
|
||||
if (ir_in == DEBUG) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_debug
|
||||
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
clock_sense_reset_n <= 1'b0;
|
||||
end else begin
|
||||
clock_sense_reset_n <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Info mode
|
||||
if (ir_in == INFO) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_info
|
||||
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
|
||||
end
|
||||
end
|
||||
|
||||
// Control mode
|
||||
if (ir_in == CONTROL) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_control <= 'b0; // capture 0
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_control
|
||||
dr_control <= {tdi, dr_control[8:1]};
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
// Update resetrequest and offset
|
||||
{resetrequest, offset} <= dr_control;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @ * begin
|
||||
if (virtual_state_sdr) begin
|
||||
case (ir_in)
|
||||
DATA: tdo <= dr_data_out[0];
|
||||
LOOPBACK: tdo <= dr_loopback;
|
||||
DEBUG: tdo <= dr_debug[0];
|
||||
INFO: tdo <= dr_info[0];
|
||||
CONTROL: tdo <= dr_control[0];
|
||||
MGMT: tdo <= dr_mgmt[0];
|
||||
default: tdo <= 1'b0;
|
||||
endcase
|
||||
end else begin
|
||||
tdo <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Idle Remover
|
||||
altera_avalon_st_idle_remover idle_remover (
|
||||
// Interface: clk
|
||||
.clk (tck),
|
||||
.reset_n (reset_n),
|
||||
|
||||
// Interface: ST in
|
||||
.in_ready (), // left disconnected
|
||||
.in_valid (idle_remover_sink_valid),
|
||||
.in_data (idle_remover_sink_data),
|
||||
|
||||
// Interface: ST out
|
||||
.out_ready (1'b1), // downstream is expected to be always ready
|
||||
.out_valid (idle_remover_source_valid),
|
||||
.out_data (idle_remover_source_data)
|
||||
);
|
||||
|
||||
// Idle Inserter
|
||||
altera_avalon_st_idle_inserter idle_inserter (
|
||||
// Interface: clk
|
||||
.clk (tck),
|
||||
.reset_n (reset_n),
|
||||
|
||||
// Interface: ST in
|
||||
.in_ready (idle_inserter_sink_ready),
|
||||
.in_valid (idle_inserter_sink_valid),
|
||||
.in_data (idle_inserter_sink_data),
|
||||
|
||||
// Interface: ST out
|
||||
.out_ready (idle_inserter_source_ready),
|
||||
.out_valid (),
|
||||
.out_data (idle_inserter_source_data)
|
||||
);
|
||||
|
||||
generate
|
||||
if (MGMT_CHANNEL_WIDTH > 0)
|
||||
begin : has_mgmt
|
||||
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
|
||||
reg mgmt_toggle = 1'b0;
|
||||
wire mgmt_toggle_sync;
|
||||
reg mgmt_toggle_prev;
|
||||
always @ (posedge tck) begin
|
||||
// Debug mode
|
||||
if (ir_in == MGMT) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_mgmt <= 'b0;
|
||||
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_debug
|
||||
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
mgmt_out <= dr_mgmt;
|
||||
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
|
||||
.dout(debug_reset));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_toggle_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_toggle),
|
||||
.dout(mgmt_toggle_sync));
|
||||
|
||||
always @ (posedge clock_to_sample or posedge debug_reset) begin
|
||||
if (debug_reset) begin
|
||||
mgmt_valid <= 1'b0;
|
||||
mgmt_toggle_prev <= 1'b0;
|
||||
end else begin
|
||||
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out[MGMT_CHANNEL_WIDTH+1]) begin
|
||||
mgmt_valid <= 1'b1;
|
||||
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
|
||||
mgmt_data <= mgmt_out[0];
|
||||
end else begin
|
||||
mgmt_valid <= 1'b0;
|
||||
end
|
||||
mgmt_toggle_prev <= mgmt_toggle_sync;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
else
|
||||
begin : no_mgmt
|
||||
always @ (posedge tck) begin
|
||||
dr_mgmt[0] <= 1'b0;
|
||||
end
|
||||
assign debug_reset = 1'b0;
|
||||
always @ (posedge clock_to_sample) begin
|
||||
mgmt_valid <= 1'b0;
|
||||
mgmt_data <= 'b0;
|
||||
mgmt_channel <= 'b0;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,272 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2010 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
|
||||
// $Revision: #3 $
|
||||
// $Date: 2010/07/07 $
|
||||
// $Author: jyeap $
|
||||
|
||||
/* -----------------------------------------------------------------------
|
||||
Round-robin/fixed arbitration implementation.
|
||||
|
||||
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
|
||||
|
||||
A: M = X & (~X + 1)
|
||||
|
||||
Example: X = 101000100
|
||||
101000100 &
|
||||
010111011 + 1 =
|
||||
|
||||
101000100 &
|
||||
010111100 =
|
||||
-----------
|
||||
000000100
|
||||
|
||||
The method can be generalized to find the first set-bit
|
||||
at a bit index no lower than bit-index N, simply by adding
|
||||
2**N rather than 1.
|
||||
|
||||
|
||||
Q: how does this relate to round-robin arbitration?
|
||||
A:
|
||||
Let X be the concatenation of all request signals.
|
||||
Let the number to be added to X (hereafter called the
|
||||
top_priority) initialize to 1, and be assigned from the
|
||||
concatenation of the previous saved-grant, left-rotated
|
||||
by one position, each time arbitration occurs. The
|
||||
concatenation of grants is then M.
|
||||
|
||||
Problem: consider this case:
|
||||
|
||||
top_priority = 010000
|
||||
request = 001001
|
||||
~request + top_priority = 000110
|
||||
next_grant = 000000 <- no one is granted!
|
||||
|
||||
There was no "set bit at a bit index no lower than bit-index 4", so
|
||||
the result was 0.
|
||||
|
||||
We need to propagate the carry out from (~request + top_priority) to the LSB, so
|
||||
that the sum becomes 000111, and next_grant is 000001. This operation could be
|
||||
called a "circular add".
|
||||
|
||||
A bit of experimentation on the circular add reveals a significant amount of
|
||||
delay in exiting and re-entering the carry chain - this will vary with device
|
||||
family. Quartus also reports a combinational loop warning. Finally,
|
||||
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
|
||||
Modelsim _doesn't_ report a combinational loop!)
|
||||
|
||||
An alternate solution: concatenate the request vector with itself, and OR
|
||||
corresponding bits from the top and bottom halves to determine next_grant.
|
||||
|
||||
Example:
|
||||
|
||||
top_priority = 010000
|
||||
{request, request} = 001001 001001
|
||||
{~request, ~request} + top_priority = 110111 000110
|
||||
result of & operation = 000001 000000
|
||||
next_grant = 000001
|
||||
|
||||
Notice that if request = 0, the sum operation will overflow, but we can ignore
|
||||
this; the next_grant result is 0 (no one granted), as you might expect.
|
||||
In the implementation, the last-granted value must be maintained as
|
||||
a non-zero value - best probably simply not to update it when no requests
|
||||
occur.
|
||||
|
||||
----------------------------------------------------------------------- */
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_arbitrator
|
||||
#(
|
||||
parameter NUM_REQUESTERS = 8,
|
||||
// --------------------------------------
|
||||
// Implemented schemes
|
||||
// "round-robin"
|
||||
// "fixed-priority"
|
||||
// "no-arb"
|
||||
// --------------------------------------
|
||||
parameter SCHEME = "round-robin",
|
||||
parameter PIPELINE = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// --------------------------------------
|
||||
// Requests
|
||||
// --------------------------------------
|
||||
input [NUM_REQUESTERS-1:0] request,
|
||||
|
||||
// --------------------------------------
|
||||
// Grants
|
||||
// --------------------------------------
|
||||
output [NUM_REQUESTERS-1:0] grant,
|
||||
|
||||
// --------------------------------------
|
||||
// Control Signals
|
||||
// --------------------------------------
|
||||
input increment_top_priority,
|
||||
input save_top_priority
|
||||
);
|
||||
|
||||
// --------------------------------------
|
||||
// Signals
|
||||
// --------------------------------------
|
||||
wire [NUM_REQUESTERS-1:0] top_priority;
|
||||
reg [NUM_REQUESTERS-1:0] top_priority_reg;
|
||||
reg [NUM_REQUESTERS-1:0] last_grant;
|
||||
wire [2*NUM_REQUESTERS-1:0] result;
|
||||
|
||||
// --------------------------------------
|
||||
// Scheme Selection
|
||||
// --------------------------------------
|
||||
generate
|
||||
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
|
||||
assign top_priority = top_priority_reg;
|
||||
end
|
||||
else begin
|
||||
// Fixed arbitration (or single-requester corner case)
|
||||
assign top_priority = 1'b1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Decision Logic
|
||||
// --------------------------------------
|
||||
altera_merlin_arb_adder
|
||||
#(
|
||||
.WIDTH (2 * NUM_REQUESTERS)
|
||||
)
|
||||
adder
|
||||
(
|
||||
.a ({ ~request, ~request }),
|
||||
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
|
||||
.sum (result)
|
||||
);
|
||||
|
||||
|
||||
generate if (SCHEME == "no-arb") begin
|
||||
|
||||
// --------------------------------------
|
||||
// No arbitration: just wire request directly to grant
|
||||
// --------------------------------------
|
||||
assign grant = request;
|
||||
|
||||
end else begin
|
||||
// Do the math in double-vector domain
|
||||
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
|
||||
assign grant_double_vector = {request, request} & result;
|
||||
|
||||
// --------------------------------------
|
||||
// Extract grant from the top and bottom halves
|
||||
// of the double vector.
|
||||
// --------------------------------------
|
||||
assign grant =
|
||||
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
|
||||
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Left-rotate the last grant vector to create top_priority.
|
||||
// --------------------------------------
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
top_priority_reg <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (PIPELINE) begin
|
||||
if (increment_top_priority) begin
|
||||
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1]} : top_priority_reg;
|
||||
end
|
||||
end else begin
|
||||
if (increment_top_priority) begin
|
||||
if (|request)
|
||||
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1] };
|
||||
else
|
||||
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
|
||||
end
|
||||
else if (save_top_priority) begin
|
||||
top_priority_reg <= grant;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ----------------------------------------------
|
||||
// Adder for the standard arbitrator
|
||||
// ----------------------------------------------
|
||||
module altera_merlin_arb_adder
|
||||
#(
|
||||
parameter WIDTH = 8
|
||||
)
|
||||
(
|
||||
input [WIDTH-1:0] a,
|
||||
input [WIDTH-1:0] b,
|
||||
|
||||
output [WIDTH-1:0] sum
|
||||
);
|
||||
|
||||
wire [WIDTH:0] sum_lint;
|
||||
// ----------------------------------------------
|
||||
// Benchmarks indicate that for small widths, the full
|
||||
// adder has higher fmax because synthesis can merge
|
||||
// it with the mux, allowing partial decisions to be
|
||||
// made early.
|
||||
//
|
||||
// The magic number is 4 requesters, which means an
|
||||
// 8 bit adder.
|
||||
// ----------------------------------------------
|
||||
genvar i;
|
||||
generate if (WIDTH <= 8) begin : full_adder
|
||||
|
||||
wire cout[WIDTH-1:0];
|
||||
|
||||
assign sum[0] = (a[0] ^ b[0]);
|
||||
assign cout[0] = (a[0] & b[0]);
|
||||
|
||||
for (i = 1; i < WIDTH; i = i+1) begin : arb
|
||||
|
||||
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
|
||||
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
|
||||
|
||||
end
|
||||
|
||||
end else begin : carry_chain
|
||||
|
||||
assign sum_lint = a + b;
|
||||
assign sum = sum_lint[WIDTH-1:0];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,296 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2012 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// ------------------------------------------
|
||||
// Merlin Burst Uncompressor
|
||||
//
|
||||
// Compressed read bursts -> uncompressed
|
||||
// ------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_burst_uncompressor
|
||||
#(
|
||||
parameter ADDR_W = 16,
|
||||
parameter BURSTWRAP_W = 3,
|
||||
parameter BYTE_CNT_W = 4,
|
||||
parameter PKT_SYMBOLS = 4,
|
||||
parameter BURST_SIZE_W = 3
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// sink ST signals
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
input sink_valid,
|
||||
output sink_ready,
|
||||
|
||||
// sink ST "data"
|
||||
input [ADDR_W - 1: 0] sink_addr,
|
||||
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
|
||||
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
|
||||
input sink_is_compressed,
|
||||
input [BURST_SIZE_W-1 : 0] sink_burstsize,
|
||||
|
||||
// source ST signals
|
||||
output source_startofpacket,
|
||||
output source_endofpacket,
|
||||
output source_valid,
|
||||
input source_ready,
|
||||
|
||||
// source ST "data"
|
||||
output [ADDR_W - 1: 0] source_addr,
|
||||
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
|
||||
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
|
||||
|
||||
// Note: in the slave agent, the output should always be uncompressed. In
|
||||
// other applications, it may be required to leave-compressed or not. How to
|
||||
// control? Seems like a simple mux - pass-through if no uncompression is
|
||||
// required.
|
||||
output source_is_compressed,
|
||||
output [BURST_SIZE_W-1 : 0] source_burstsize
|
||||
);
|
||||
|
||||
//----------------------------------------------------
|
||||
// AXSIZE decoding
|
||||
//
|
||||
// Turns the axsize value into the actual number of bytes
|
||||
// being transferred.
|
||||
// ---------------------------------------------------
|
||||
function reg[63:0] bytes_in_transfer;
|
||||
input [BURST_SIZE_W-1:0] axsize;
|
||||
case (axsize)
|
||||
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
|
||||
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
|
||||
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
|
||||
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
|
||||
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
|
||||
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
|
||||
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
|
||||
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
|
||||
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
|
||||
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
|
||||
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
|
||||
endcase
|
||||
|
||||
endfunction
|
||||
|
||||
// num_symbols is PKT_SYMBOLS, appropriately sized.
|
||||
wire [31:0] int_num_symbols = PKT_SYMBOLS;
|
||||
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
|
||||
|
||||
// def: Burst Compression. In a merlin network, a compressed burst is one
|
||||
// which is transmitted in a single beat. Example: read burst. In
|
||||
// constrast, an uncompressed burst (example: write burst) is transmitted in
|
||||
// one beat per writedata item.
|
||||
//
|
||||
// For compressed bursts which require response packets, burst
|
||||
// uncompression is required. Concrete example: a read burst of size 8
|
||||
// occupies one response-fifo position. When that fifo position reaches the
|
||||
// front of the FIFO, the slave starts providing the required 8 readdatavalid
|
||||
// pulses. The 8 return response beats must be provided in a single packet,
|
||||
// with incrementing address and decrementing byte_cnt fields. Upon receipt
|
||||
// of the final readdata item of the burst, the response FIFO item is
|
||||
// retired.
|
||||
// Burst uncompression logic provides:
|
||||
// a) 2-state FSM (idle, busy)
|
||||
// reset to idle state
|
||||
// transition to busy state for 2nd and subsequent rdv pulses
|
||||
// - a single-cycle burst (aka non-burst read) causes no transition to
|
||||
// busy state.
|
||||
// b) response startofpacket/endofpacket logic. The response FIFO item
|
||||
// will have sop asserted, and may have eop asserted. (In the case of
|
||||
// multiple read bursts transmit in the command fabric in a single packet,
|
||||
// the eop assertion will come in a later FIFO item.) To support packet
|
||||
// conservation, and emit a well-formed packet on the response fabric,
|
||||
// i) response fabric startofpacket is asserted only for the first resp.
|
||||
// beat;
|
||||
// ii) response fabric endofpacket is asserted only for the last resp.
|
||||
// beat.
|
||||
// c) response address field. The response address field contains an
|
||||
// incrementing sequence, such that each readdata item is associated with
|
||||
// its slave-map location. N.b. a) computing the address correctly requires
|
||||
// knowledge of burstwrap behavior b) there may be no clients of the address
|
||||
// field, which makes this field a good target for optimization. See
|
||||
// burst_uncompress_address_counter below.
|
||||
// d) response byte_cnt field. The response byte_cnt field contains a
|
||||
// decrementing sequence, such that each beat of the response contains the
|
||||
// count of bytes to follow. In the case of sub-bursts in a single packet,
|
||||
// the byte_cnt field may decrement down to num_symbols, then back up to
|
||||
// some value, multiple times in the packet.
|
||||
|
||||
reg burst_uncompress_busy;
|
||||
reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
|
||||
wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
|
||||
wire first_packet_beat;
|
||||
wire last_packet_beat;
|
||||
|
||||
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
|
||||
assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
|
||||
|
||||
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
|
||||
// the output.
|
||||
assign source_byte_cnt =
|
||||
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
|
||||
assign source_valid = sink_valid;
|
||||
|
||||
// Last packet beat is set throughout receipt of an uncompressed read burst
|
||||
// from the response FIFO - this forces all the burst uncompression machinery
|
||||
// idle.
|
||||
assign last_packet_beat = ~sink_is_compressed |
|
||||
(
|
||||
burst_uncompress_busy ?
|
||||
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
|
||||
sink_valid & (sink_byte_cnt == num_symbols)
|
||||
);
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
burst_uncompress_byte_counter <= '0;
|
||||
end
|
||||
else begin
|
||||
if (source_valid & source_ready & sink_valid) begin
|
||||
// No matter what the current state, last_packet_beat leads to
|
||||
// idle.
|
||||
if (last_packet_beat) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
burst_uncompress_byte_counter <= '0;
|
||||
end
|
||||
else begin
|
||||
if (burst_uncompress_busy) begin
|
||||
burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ?
|
||||
(burst_uncompress_byte_counter_lint - num_symbols) :
|
||||
(sink_byte_cnt - num_symbols);
|
||||
end
|
||||
else begin // not busy, at least one more beat to go
|
||||
burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
|
||||
// To do: should busy go true for numsymbols-size compressed
|
||||
// bursts?
|
||||
burst_uncompress_busy <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
|
||||
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
|
||||
|
||||
wire [63:0] decoded_burstsize_wire;
|
||||
wire [ADDR_W-1:0] decoded_burstsize;
|
||||
|
||||
|
||||
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
|
||||
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
|
||||
// The input burstwrap value can be used as a mask against address values,
|
||||
// but with one caveat: the address width may be (probably is) wider than
|
||||
// the burstwrap width. The spec says: extend the msb of the burstwrap
|
||||
// value out over the entire address width (but only if the address width
|
||||
// actually is wider than the burstwrap width; otherwise it's a 0-width or
|
||||
// negative range and concatenation multiplier).
|
||||
generate
|
||||
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
|
||||
// Sign-extend, just wires:
|
||||
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
|
||||
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
|
||||
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
|
||||
end
|
||||
else begin
|
||||
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_address_base <= '0;
|
||||
end
|
||||
else if (first_packet_beat & source_ready) begin
|
||||
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
|
||||
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
|
||||
|
||||
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
|
||||
(
|
||||
(first_packet_beat ?
|
||||
sink_addr :
|
||||
burst_uncompress_address_offset) + decoded_burstsize
|
||||
) &
|
||||
addr_width_burstwrap[ADDR_W-1:0];
|
||||
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_address_offset <= '0;
|
||||
end
|
||||
else begin
|
||||
if (source_ready & source_valid) begin
|
||||
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
|
||||
// if (first_packet_beat) begin
|
||||
// burst_uncompress_address_offset <=
|
||||
// (sink_addr + num_symbols) & addr_width_burstwrap;
|
||||
// end
|
||||
// else begin
|
||||
// burst_uncompress_address_offset <=
|
||||
// (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
|
||||
// end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// On the first packet beat, send the input address out unchanged,
|
||||
// while values are computed/registered for 2nd and subsequent beats.
|
||||
assign source_addr = first_packet_beat ? sink_addr :
|
||||
burst_uncompress_address_base | burst_uncompress_address_offset;
|
||||
assign source_burstwrap = sink_burstwrap;
|
||||
assign source_burstsize = sink_burstsize;
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
// A single (compressed) read burst will have sop/eop in the same beat.
|
||||
// A sequence of read sub-bursts emitted by a burst adapter in response to a
|
||||
// single read burst will have sop on the first sub-burst, eop on the last.
|
||||
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
|
||||
// packet conservation.
|
||||
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
|
||||
assign source_endofpacket = sink_endofpacket & last_packet_beat;
|
||||
assign sink_ready = source_valid & source_ready & last_packet_beat;
|
||||
|
||||
// This is correct for the slave agent usage, but won't always be true in the
|
||||
// width adapter. To do: add an "please uncompress" input, and use it to
|
||||
// pass-through or modify, and set source_is_compressed accordingly.
|
||||
assign source_is_compressed = 1'b0;
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,303 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// --------------------------------------
|
||||
// Merlin Master Agent
|
||||
//
|
||||
// Converts Avalon-MM transactions into
|
||||
// Merlin network packets.
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_master_agent
|
||||
#(
|
||||
// -------------------
|
||||
// Packet Format Parameters
|
||||
// -------------------
|
||||
parameter
|
||||
PKT_QOS_H = 109,
|
||||
PKT_QOS_L = 106,
|
||||
PKT_DATA_SIDEBAND_H = 105,
|
||||
PKT_DATA_SIDEBAND_L = 98,
|
||||
PKT_ADDR_SIDEBAND_H = 97,
|
||||
PKT_ADDR_SIDEBAND_L = 93,
|
||||
PKT_CACHE_H = 92,
|
||||
PKT_CACHE_L = 89,
|
||||
PKT_THREAD_ID_H = 88,
|
||||
PKT_THREAD_ID_L = 87,
|
||||
PKT_BEGIN_BURST = 81,
|
||||
PKT_PROTECTION_H = 80,
|
||||
PKT_PROTECTION_L = 80,
|
||||
PKT_BURSTWRAP_H = 79,
|
||||
PKT_BURSTWRAP_L = 77,
|
||||
PKT_BYTE_CNT_H = 76,
|
||||
PKT_BYTE_CNT_L = 74,
|
||||
PKT_ADDR_H = 73,
|
||||
PKT_ADDR_L = 42,
|
||||
PKT_BURST_SIZE_H = 86,
|
||||
PKT_BURST_SIZE_L = 84,
|
||||
PKT_BURST_TYPE_H = 94,
|
||||
PKT_BURST_TYPE_L = 93,
|
||||
PKT_TRANS_EXCLUSIVE = 83,
|
||||
PKT_TRANS_LOCK = 82,
|
||||
PKT_TRANS_COMPRESSED_READ = 41,
|
||||
PKT_TRANS_POSTED = 40,
|
||||
PKT_TRANS_WRITE = 39,
|
||||
PKT_TRANS_READ = 38,
|
||||
PKT_DATA_H = 37,
|
||||
PKT_DATA_L = 6,
|
||||
PKT_BYTEEN_H = 5,
|
||||
PKT_BYTEEN_L = 2,
|
||||
PKT_SRC_ID_H = 1,
|
||||
PKT_SRC_ID_L = 1,
|
||||
PKT_DEST_ID_H = 0,
|
||||
PKT_DEST_ID_L = 0,
|
||||
PKT_RESPONSE_STATUS_L = 110,
|
||||
PKT_RESPONSE_STATUS_H = 111,
|
||||
PKT_ORI_BURST_SIZE_L = 112,
|
||||
PKT_ORI_BURST_SIZE_H = 114,
|
||||
ST_DATA_W = 115,
|
||||
ST_CHANNEL_W = 1,
|
||||
|
||||
// -------------------
|
||||
// Agent Parameters
|
||||
// -------------------
|
||||
AV_BURSTCOUNT_W = 3,
|
||||
ID = 1,
|
||||
SUPPRESS_0_BYTEEN_RSP = 1,
|
||||
BURSTWRAP_VALUE = 4,
|
||||
CACHE_VALUE = 0,
|
||||
SECURE_ACCESS_BIT = 1,
|
||||
USE_READRESPONSE = 0,
|
||||
USE_WRITERESPONSE = 0,
|
||||
|
||||
// -------------------
|
||||
// Derived Parameters
|
||||
// -------------------
|
||||
PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
|
||||
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
|
||||
PKT_PROTECTION_W = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
|
||||
PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
|
||||
PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
|
||||
PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
|
||||
PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
|
||||
PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
|
||||
PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
|
||||
) (
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Avalon-MM Anti-Master
|
||||
// -------------------
|
||||
input [PKT_ADDR_W-1 : 0] av_address,
|
||||
input av_write,
|
||||
input av_read,
|
||||
input [PKT_DATA_W-1 : 0] av_writedata,
|
||||
output reg [PKT_DATA_W-1 : 0] av_readdata,
|
||||
output reg av_waitrequest,
|
||||
output reg av_readdatavalid,
|
||||
input [PKT_BYTEEN_W-1 : 0] av_byteenable,
|
||||
input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
|
||||
input av_debugaccess,
|
||||
input av_lock,
|
||||
output reg [1 : 0] av_response,
|
||||
output reg av_writeresponsevalid,
|
||||
|
||||
// -------------------
|
||||
// Command Source
|
||||
// -------------------
|
||||
output reg cp_valid,
|
||||
output reg [ST_DATA_W-1 : 0] cp_data,
|
||||
output wire cp_startofpacket,
|
||||
output wire cp_endofpacket,
|
||||
input cp_ready,
|
||||
|
||||
// -------------------
|
||||
// Response Sink
|
||||
// -------------------
|
||||
input rp_valid,
|
||||
input [ST_DATA_W-1 : 0] rp_data,
|
||||
input [ST_CHANNEL_W-1 : 0] rp_channel,
|
||||
input rp_startofpacket,
|
||||
input rp_endofpacket,
|
||||
output reg rp_ready
|
||||
);
|
||||
// ------------------------------------------------------------
|
||||
// Utility Functions
|
||||
// ------------------------------------------------------------
|
||||
function integer clogb2;
|
||||
input [31 : 0] value;
|
||||
begin
|
||||
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
|
||||
value = value >> 1;
|
||||
clogb2 = clogb2 - 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1);
|
||||
localparam NUMSYMBOLS = PKT_BYTEEN_W;
|
||||
localparam BURSTING = (MAX_BURST > NUMSYMBOLS);
|
||||
localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
|
||||
localparam BURST_SIZE = clogb2(NUMSYMBOLS);
|
||||
|
||||
typedef enum bit [1 : 0]
|
||||
{
|
||||
FIXED = 2'b00,
|
||||
INCR = 2'b01,
|
||||
WRAP = 2'b10,
|
||||
OTHER_WRAP = 2'b11
|
||||
} MerlinBurstType;
|
||||
|
||||
// --------------------------------------
|
||||
// Potential optimization: compare in words to save bits?
|
||||
// --------------------------------------
|
||||
wire is_burst;
|
||||
assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
|
||||
|
||||
wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
|
||||
wire [31 : 0] id_int = ID;
|
||||
wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
|
||||
wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
|
||||
|
||||
// --------------------------------------
|
||||
// Address alignment
|
||||
//
|
||||
// The packet format requires that addresses be aligned to
|
||||
// the transaction size.
|
||||
// --------------------------------------
|
||||
wire [PKT_ADDR_W-1 : 0] av_address_aligned;
|
||||
generate
|
||||
if (NUMSYMBOLS > 1) begin
|
||||
assign av_address_aligned =
|
||||
{av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
|
||||
end
|
||||
else begin
|
||||
assign av_address_aligned = av_address;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Command & Response Construction
|
||||
// --------------------------------------
|
||||
always_comb begin
|
||||
cp_data = '0;
|
||||
|
||||
cp_data[PKT_PROTECTION_L] = av_debugaccess;
|
||||
cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // secure cache bit
|
||||
cp_data[PKT_PROTECTION_L+2] = 1'b0; // instruction/data cache bit
|
||||
cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
|
||||
cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = av_burstcount;
|
||||
cp_data[PKT_ADDR_H : PKT_ADDR_L] = av_address_aligned;
|
||||
cp_data[PKT_TRANS_EXCLUSIVE] = 1'b0;
|
||||
cp_data[PKT_TRANS_LOCK] = av_lock;
|
||||
cp_data[PKT_TRANS_COMPRESSED_READ] = av_read & is_burst;
|
||||
cp_data[PKT_TRANS_READ] = av_read;
|
||||
cp_data[PKT_TRANS_WRITE] = av_write;
|
||||
cp_data[PKT_TRANS_POSTED] = av_write & !USE_WRITERESPONSE;
|
||||
cp_data[PKT_DATA_H : PKT_DATA_L] = av_writedata;
|
||||
cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] = av_byteenable;
|
||||
cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] = burstsize_sig;
|
||||
cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
|
||||
cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = bursttype_value;
|
||||
cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L] = id_int[PKT_SRC_ID_W-1 : 0];
|
||||
cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L] = '0;
|
||||
cp_data[PKT_CACHE_H : PKT_CACHE_L] = CACHE_VALUE[3 : 0];
|
||||
cp_data[PKT_QOS_H : PKT_QOS_L] = '0;
|
||||
cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L] = '0;
|
||||
cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L] = '0;
|
||||
|
||||
av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L];
|
||||
if (USE_WRITERESPONSE || USE_READRESPONSE)
|
||||
av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
|
||||
else
|
||||
av_response = '0;
|
||||
end
|
||||
|
||||
// --------------------------------------
|
||||
// Command Control
|
||||
// --------------------------------------
|
||||
reg hold_waitrequest;
|
||||
|
||||
always @ (posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
hold_waitrequest <= 1'b1;
|
||||
else
|
||||
hold_waitrequest <= 1'b0;
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
cp_valid = 0;
|
||||
|
||||
if ((av_write || av_read) && ~hold_waitrequest)
|
||||
cp_valid = 1;
|
||||
end
|
||||
|
||||
generate if (BURSTING) begin
|
||||
reg sop_enable;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
sop_enable <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (cp_valid && cp_ready) begin
|
||||
sop_enable <= 1'b0;
|
||||
if (cp_endofpacket)
|
||||
sop_enable <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cp_startofpacket = sop_enable;
|
||||
assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS);
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
assign cp_startofpacket = 1'b1;
|
||||
assign cp_endofpacket = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------
|
||||
// Backpressure & Readdatavalid
|
||||
// --------------------------------------
|
||||
always_comb begin
|
||||
rp_ready = 1;
|
||||
av_readdatavalid = 0;
|
||||
av_writeresponsevalid = 0;
|
||||
av_waitrequest = hold_waitrequest | !cp_ready;
|
||||
|
||||
if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
|
||||
av_writeresponsevalid = rp_valid;
|
||||
else
|
||||
av_readdatavalid = rp_valid;
|
||||
|
||||
if (SUPPRESS_0_BYTEEN_RSP) begin
|
||||
if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
|
||||
av_readdatavalid = 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,556 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// --------------------------------------
|
||||
// Merlin Master Translator
|
||||
//
|
||||
// Converts an Avalon-MM master interface into an
|
||||
// Avalon-MM "universal" master interface.
|
||||
//
|
||||
// The universal interface is defined as the superset of ports
|
||||
// and parameters that can represent any legal Avalon
|
||||
// interface.
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_master_translator #(
|
||||
parameter
|
||||
// widths
|
||||
AV_ADDRESS_W = 32,
|
||||
AV_DATA_W = 32,
|
||||
AV_BURSTCOUNT_W = 4,
|
||||
AV_BYTEENABLE_W = 4,
|
||||
|
||||
UAV_ADDRESS_W = 38,
|
||||
UAV_BURSTCOUNT_W = 10,
|
||||
|
||||
// optional ports
|
||||
USE_BURSTCOUNT = 1,
|
||||
USE_BEGINBURSTTRANSFER = 0,
|
||||
USE_BEGINTRANSFER = 0,
|
||||
USE_CHIPSELECT = 0,
|
||||
USE_READ = 1,
|
||||
USE_READDATAVALID = 1,
|
||||
USE_WRITE = 1,
|
||||
USE_WAITREQUEST = 1,
|
||||
USE_WRITERESPONSE = 0,
|
||||
USE_READRESPONSE = 0,
|
||||
|
||||
AV_REGISTERINCOMINGSIGNALS = 0,
|
||||
AV_SYMBOLS_PER_WORD = 4,
|
||||
AV_ADDRESS_SYMBOLS = 0,
|
||||
// must be enabled for a bursting master
|
||||
AV_CONSTANT_BURST_BEHAVIOR = 1,
|
||||
UAV_CONSTANT_BURST_BEHAVIOR = 0,
|
||||
AV_BURSTCOUNT_SYMBOLS = 0,
|
||||
AV_LINEWRAPBURSTS = 0
|
||||
)(
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// Universal Avalon Master
|
||||
output reg uav_write,
|
||||
output reg uav_read,
|
||||
output reg [UAV_ADDRESS_W -1 : 0] uav_address,
|
||||
output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
|
||||
output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
|
||||
output wire [AV_DATA_W -1 : 0] uav_writedata,
|
||||
output wire uav_lock,
|
||||
output wire uav_debugaccess,
|
||||
output wire uav_clken,
|
||||
|
||||
input wire [AV_DATA_W -1 : 0] uav_readdata,
|
||||
input wire uav_readdatavalid,
|
||||
input wire uav_waitrequest,
|
||||
input wire [1 : 0] uav_response,
|
||||
input wire uav_writeresponsevalid,
|
||||
|
||||
// Avalon-MM Anti-master (slave)
|
||||
input reg av_write,
|
||||
input reg av_read,
|
||||
input wire [AV_ADDRESS_W -1 : 0] av_address,
|
||||
input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable,
|
||||
input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount,
|
||||
input wire [AV_DATA_W -1 : 0] av_writedata,
|
||||
input wire av_begintransfer,
|
||||
input wire av_beginbursttransfer,
|
||||
input wire av_lock,
|
||||
input wire av_chipselect,
|
||||
input wire av_debugaccess,
|
||||
input wire av_clken,
|
||||
|
||||
output wire [AV_DATA_W -1 : 0] av_readdata,
|
||||
output wire av_readdatavalid,
|
||||
output reg av_waitrequest,
|
||||
output reg [1 : 0] av_response,
|
||||
output reg av_writeresponsevalid
|
||||
);
|
||||
|
||||
localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
|
||||
localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
|
||||
localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
|
||||
localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
|
||||
localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
|
||||
|
||||
localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
|
||||
localparam BITS_PER_WORD_ADDRESS = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
|
||||
|
||||
localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
|
||||
localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
|
||||
|
||||
localparam ADDRESS_HIGH = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
|
||||
localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
|
||||
|
||||
function integer flog2;
|
||||
input [31:0] depth;
|
||||
integer i;
|
||||
begin
|
||||
i = depth;
|
||||
if ( i <= 0 ) flog2 = 0;
|
||||
else begin
|
||||
for (flog2 = -1; i > 0; flog2 = flog2 + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
end
|
||||
endfunction // flog2
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Calculates the ceil(log2()) of the input val.
|
||||
//
|
||||
// Limited to a positive 32-bit input value.
|
||||
// ------------------------------------------------------------
|
||||
function integer clog2;
|
||||
input[31:0] val;
|
||||
reg[31:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
clog2 = 0;
|
||||
|
||||
while (i < val) begin
|
||||
clog2 = clog2 + 1;
|
||||
i = i[30:0] << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer pow2;
|
||||
input [31:0] toShift;
|
||||
begin
|
||||
pow2 = 1;
|
||||
pow2 = pow2 << toShift;
|
||||
end
|
||||
endfunction // pow2
|
||||
|
||||
// -------------------------------------------------
|
||||
// Assign some constants to appropriately-sized signals to
|
||||
// avoid synthesis warnings. This also helps some simulators
|
||||
// with their inferred sensitivity lists.
|
||||
//
|
||||
// The symbols per word calculation here rounds non-power of two
|
||||
// symbols to the next highest power of two, which is what we want
|
||||
// when calculating the decrementing byte count.
|
||||
// -------------------------------------------------
|
||||
wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
|
||||
wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
|
||||
|
||||
reg internal_beginbursttransfer;
|
||||
reg internal_begintransfer;
|
||||
reg [UAV_ADDRESS_W -1 : 0] uav_address_pre;
|
||||
reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount_pre;
|
||||
|
||||
reg uav_read_pre;
|
||||
reg uav_write_pre;
|
||||
reg read_accepted;
|
||||
|
||||
// -------------------------------------------------
|
||||
// Pass through signals that we don't touch
|
||||
// -------------------------------------------------
|
||||
assign uav_writedata = av_writedata;
|
||||
assign uav_byteenable = av_byteenable;
|
||||
assign uav_lock = av_lock;
|
||||
assign uav_debugaccess = av_debugaccess;
|
||||
assign uav_clken = av_clken;
|
||||
|
||||
assign av_readdata = uav_readdata;
|
||||
assign av_readdatavalid = uav_readdatavalid;
|
||||
|
||||
// -------------------------------------------------
|
||||
// Response signals
|
||||
// -------------------------------------------------
|
||||
always_comb begin
|
||||
if (!USE_READRESPONSE && !USE_WRITERESPONSE)
|
||||
av_response = '0;
|
||||
else
|
||||
av_response = uav_response;
|
||||
|
||||
if (USE_WRITERESPONSE) begin
|
||||
av_writeresponsevalid = uav_writeresponsevalid;
|
||||
end else begin
|
||||
av_writeresponsevalid = '0;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------
|
||||
// Convert byte and word addresses into byte addresses
|
||||
// -------------------------------------------------
|
||||
always_comb begin
|
||||
uav_address_pre = {UAV_ADDRESS_W{1'b0}};
|
||||
|
||||
if (AV_ADDRESS_SYMBOLS)
|
||||
uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
|
||||
else begin
|
||||
uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------
|
||||
// Convert burstcount into symbol units
|
||||
// -------------------------------------------------
|
||||
always_comb begin
|
||||
uav_burstcount_pre = symbols_per_word; // default to a single transfer
|
||||
|
||||
if (USE_BURSTCOUNT) begin
|
||||
uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
|
||||
if (AV_BURSTCOUNT_SYMBOLS)
|
||||
uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
|
||||
else begin
|
||||
uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------
|
||||
// This is where we perform the per-transfer address and burstcount
|
||||
// calculations that are required by downstream modules.
|
||||
// -------------------------------------------------
|
||||
reg [UAV_ADDRESS_W -1 : 0] address_register;
|
||||
wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
|
||||
reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
|
||||
|
||||
assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
|
||||
|
||||
always_comb begin
|
||||
uav_address = uav_address_pre;
|
||||
uav_burstcount = uav_burstcount_pre;
|
||||
|
||||
if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
|
||||
uav_address = address_register;
|
||||
uav_burstcount = burstcount_register;
|
||||
end
|
||||
end
|
||||
|
||||
reg first_burst_stalled;
|
||||
reg burst_stalled;
|
||||
|
||||
wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
|
||||
wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
|
||||
|
||||
generate
|
||||
if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
|
||||
if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
|
||||
assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
|
||||
assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
|
||||
end
|
||||
else begin
|
||||
assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
|
||||
assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
|
||||
end
|
||||
end
|
||||
else begin
|
||||
assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
|
||||
assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
address_register <= '0;
|
||||
burstcount_register_lint <= '0;
|
||||
end else begin
|
||||
address_register <= address_register;
|
||||
burstcount_register_lint <= burstcount_register_lint;
|
||||
|
||||
if (internal_beginbursttransfer || first_burst_stalled) begin
|
||||
if (av_waitrequest) begin
|
||||
address_register <= uav_address_pre;
|
||||
burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
|
||||
end else begin
|
||||
address_register <= combi_burst_addr_reg;
|
||||
burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
|
||||
end
|
||||
end else if (internal_begintransfer || burst_stalled) begin
|
||||
if (~av_waitrequest) begin
|
||||
address_register <= combi_addr_reg;
|
||||
burstcount_register_lint <= burstcount_register - symbols_per_word;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
first_burst_stalled <= 1'b0;
|
||||
burst_stalled <= 1'b0;
|
||||
end else begin
|
||||
if (internal_beginbursttransfer || first_burst_stalled) begin
|
||||
if (av_waitrequest) begin
|
||||
first_burst_stalled <= 1'b1;
|
||||
end else begin
|
||||
first_burst_stalled <= 1'b0;
|
||||
end
|
||||
end else if (internal_begintransfer || burst_stalled) begin
|
||||
if (~av_waitrequest) begin
|
||||
burst_stalled <= 1'b0;
|
||||
end else begin
|
||||
burst_stalled <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------
|
||||
// Waitrequest translation
|
||||
// -------------------------------------------------
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
read_accepted <= 1'b0;
|
||||
else begin
|
||||
read_accepted <= read_accepted;
|
||||
if (read_accepted == 0)
|
||||
read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
|
||||
else if (read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives
|
||||
read_accepted <= 1'b0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
reg write_accepted = 0;
|
||||
generate if (AV_REGISTERINCOMINGSIGNALS) begin
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
write_accepted <= 1'b0;
|
||||
else begin
|
||||
write_accepted <=
|
||||
~av_waitrequest ? 1'b0 :
|
||||
uav_write & ~uav_waitrequest? 1'b1 :
|
||||
write_accepted;
|
||||
end
|
||||
end
|
||||
end endgenerate
|
||||
|
||||
always_comb begin
|
||||
av_waitrequest = uav_waitrequest;
|
||||
|
||||
if (USE_READDATAVALID == 0) begin
|
||||
av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
|
||||
end
|
||||
|
||||
if (AV_REGISTERINCOMINGSIGNALS) begin
|
||||
av_waitrequest =
|
||||
uav_read_pre ? ~uav_readdatavalid :
|
||||
uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
|
||||
1'b1;
|
||||
end
|
||||
|
||||
if (USE_WAITREQUEST == 0) begin
|
||||
av_waitrequest = 0;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------
|
||||
// Determine the output read and write signals from
|
||||
// the read/write/chipselect input signals.
|
||||
// -------------------------------------------------
|
||||
always_comb begin
|
||||
uav_write = 1'b0;
|
||||
uav_write_pre = 1'b0;
|
||||
uav_read = 1'b0;
|
||||
uav_read_pre = 1'b0;
|
||||
|
||||
if (!USE_CHIPSELECT) begin
|
||||
if (USE_READ) begin
|
||||
uav_read_pre = av_read;
|
||||
end
|
||||
|
||||
if (USE_WRITE) begin
|
||||
uav_write_pre = av_write;
|
||||
end
|
||||
end else begin
|
||||
if (!USE_WRITE && USE_READ) begin
|
||||
uav_write_pre = av_chipselect & ~av_read;
|
||||
uav_read_pre = av_read;
|
||||
end else if (!USE_READ && USE_WRITE) begin
|
||||
uav_write_pre = av_write;
|
||||
uav_read_pre = av_chipselect & ~av_write;
|
||||
end else if (USE_READ && USE_WRITE) begin
|
||||
uav_write_pre = av_write;
|
||||
uav_read_pre = av_read;
|
||||
end
|
||||
end
|
||||
|
||||
if (USE_READDATAVALID == 0)
|
||||
uav_read = uav_read_pre & ~read_accepted;
|
||||
else
|
||||
uav_read = uav_read_pre;
|
||||
|
||||
if (AV_REGISTERINCOMINGSIGNALS == 0)
|
||||
uav_write = uav_write_pre;
|
||||
else
|
||||
uav_write = uav_write_pre & ~write_accepted;
|
||||
end
|
||||
|
||||
// -------------------------------------------------
|
||||
// Begintransfer assignment
|
||||
// -------------------------------------------------
|
||||
reg end_begintransfer;
|
||||
|
||||
always_comb begin
|
||||
if (USE_BEGINTRANSFER) begin
|
||||
internal_begintransfer = av_begintransfer;
|
||||
end else begin
|
||||
internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
end_begintransfer <= 1'b0;
|
||||
end else begin
|
||||
if (internal_begintransfer == 1 && uav_waitrequest)
|
||||
end_begintransfer <= 1'b1;
|
||||
else if (uav_waitrequest)
|
||||
end_begintransfer <= end_begintransfer;
|
||||
else
|
||||
end_begintransfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------
|
||||
// Beginbursttransfer assignment
|
||||
// -------------------------------------------------
|
||||
reg end_beginbursttransfer;
|
||||
wire last_burst_transfer_pre;
|
||||
wire last_burst_transfer_reg;
|
||||
wire last_burst_transfer;
|
||||
|
||||
// compare values before the mux to shorten critical path; benchmark before changing
|
||||
assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
|
||||
assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
|
||||
assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
|
||||
|
||||
always_comb begin
|
||||
if (USE_BEGINBURSTTRANSFER) begin
|
||||
internal_beginbursttransfer = av_beginbursttransfer;
|
||||
end else begin
|
||||
internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
end_beginbursttransfer <= 1'b0;
|
||||
end else begin
|
||||
end_beginbursttransfer <= end_beginbursttransfer;
|
||||
if (last_burst_transfer && internal_begintransfer || uav_read) begin
|
||||
end_beginbursttransfer <= 1'b0;
|
||||
end
|
||||
else if (uav_write && internal_begintransfer) begin
|
||||
end_beginbursttransfer <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
// ------------------------------------------------
|
||||
// check_1 : for waitrequest signal violation
|
||||
// Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
|
||||
// Exception : begintransfer / beginbursttransfer
|
||||
// : previously not in any transaction (idle)
|
||||
// Note : Not checking clken which is not exactly part of Avalon controls/inputs
|
||||
// : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
|
||||
// ------------------------------------------------
|
||||
|
||||
reg av_waitrequest_r;
|
||||
reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
|
||||
reg [AV_ADDRESS_W-1:0] av_address_r;
|
||||
reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
|
||||
reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
|
||||
reg [AV_DATA_W-1:0] av_writedata_r;
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
av_waitrequest_r <= '0;
|
||||
av_write_r <= '0;
|
||||
av_read_r <= '0;
|
||||
av_lock_r <= '0;
|
||||
av_chipselect_r <= '0;
|
||||
av_debugaccess_r <= '0;
|
||||
av_address_r <= '0;
|
||||
av_byteenable_r <= '0;
|
||||
av_burstcount_r <= '0;
|
||||
av_writedata_r <= '0;
|
||||
end else begin
|
||||
av_waitrequest_r <= av_waitrequest;
|
||||
av_write_r <= av_write;
|
||||
av_read_r <= av_read;
|
||||
av_lock_r <= av_lock;
|
||||
av_chipselect_r <= av_chipselect;
|
||||
av_debugaccess_r <= av_debugaccess;
|
||||
av_address_r <= av_address;
|
||||
av_byteenable_r <= av_byteenable;
|
||||
av_burstcount_r <= av_burstcount;
|
||||
av_writedata_r <= av_writedata;
|
||||
|
||||
if (
|
||||
av_waitrequest_r && // When waitrequest is asserted
|
||||
(
|
||||
(av_write != av_write_r) || // Checks that : Input controls/data does not change
|
||||
(av_read != av_read_r) ||
|
||||
(av_lock != av_lock_r) ||
|
||||
(av_debugaccess != av_debugaccess_r) ||
|
||||
(av_address != av_address_r) ||
|
||||
(av_byteenable != av_byteenable_r) ||
|
||||
(av_burstcount != av_burstcount_r)
|
||||
) &&
|
||||
(av_write_r | av_read_r) && // Check only when : previously initiated a write/read
|
||||
(!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused)
|
||||
) begin
|
||||
$display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
|
||||
$display("av_address %x --> %x", av_address_r , av_address );
|
||||
$display("av_byteenable %x --> %x", av_byteenable_r , av_byteenable );
|
||||
$display("av_burstcount %x --> %x", av_burstcount_r , av_burstcount );
|
||||
$display("av_writedata %x --> %x", av_writedata_r , av_writedata );
|
||||
$display("av_write %x --> %x", av_write_r , av_write );
|
||||
$display("av_read %x --> %x", av_read_r , av_read );
|
||||
$display("av_lock %x --> %x", av_lock_r , av_lock );
|
||||
$display("av_chipselect %x --> %x", av_chipselect_r , av_chipselect );
|
||||
$display("av_debugaccess %x --> %x", av_debugaccess_r , av_debugaccess );
|
||||
end
|
||||
end
|
||||
|
||||
// end check_1
|
||||
|
||||
end
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,297 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_reorder_memory.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Merlin Order Memory: this stores responses from slave
|
||||
// and do reorder. The memory structure is normal memory
|
||||
// with many segments for different responses that master
|
||||
// can handle.
|
||||
// The number of segment is the number of MAX_OUTSTANDING_RESPONSE
|
||||
// ------------------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
module altera_merlin_reorder_memory
|
||||
#(
|
||||
parameter DATA_W = 32,
|
||||
ADDR_H_W = 4, // width to represent how many segments
|
||||
ADDR_L_W = 4,
|
||||
VALID_W = 4,
|
||||
NUM_SEGMENT = 4,
|
||||
DEPTH = 16
|
||||
|
||||
)
|
||||
|
||||
(
|
||||
// -------------------
|
||||
// Clock
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
// -------------------
|
||||
// Signals
|
||||
// -------------------
|
||||
input [DATA_W - 1 : 0] in_data,
|
||||
input in_valid,
|
||||
output in_ready,
|
||||
|
||||
output reg [DATA_W - 1 : 0] out_data,
|
||||
output reg out_valid,
|
||||
input out_ready,
|
||||
// --------------------------------------------
|
||||
// wr_segment: select write portion of memory
|
||||
// rd_segment: select read portion of memory
|
||||
// --------------------------------------------
|
||||
input [ADDR_H_W - 1 : 0] wr_segment,
|
||||
input [ADDR_H_W - 1 : 0] rd_segment
|
||||
|
||||
);
|
||||
|
||||
// -------------------------------------
|
||||
// Local parameter
|
||||
// -------------------------------------
|
||||
localparam SEGMENT_W = ADDR_H_W;
|
||||
|
||||
wire [ADDR_H_W + ADDR_L_W - 1 : 0] mem_wr_addr;
|
||||
reg [ADDR_H_W + ADDR_L_W - 1 : 0] mem_rd_addr;
|
||||
wire [ADDR_L_W - 1 : 0] mem_wr_ptr;
|
||||
wire [ADDR_L_W - 1 : 0] mem_rd_ptr;
|
||||
reg [ADDR_L_W - 1 : 0] mem_next_rd_ptr;
|
||||
reg [DATA_W - 1 : 0] out_payload;
|
||||
|
||||
wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_ready;
|
||||
wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_valid;
|
||||
wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_valid;
|
||||
wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_ready;
|
||||
wire [ADDR_L_W - 1 : 0] pointer_ctrl_wr_ptr [NUM_SEGMENT];
|
||||
wire [ADDR_L_W - 1 : 0] pointer_ctrl_rd_ptr [NUM_SEGMENT];
|
||||
wire [ADDR_L_W - 1 : 0] pointer_ctrl_next_rd_ptr [NUM_SEGMENT];
|
||||
|
||||
// ---------------------------------
|
||||
// Memory storage
|
||||
// ---------------------------------
|
||||
(* ramstyle="no_rw_check" *) reg [DATA_W - 1 : 0] mem [DEPTH - 1 : 0];
|
||||
always @(posedge clk) begin
|
||||
if (in_valid && in_ready)
|
||||
mem[mem_wr_addr] = in_data;
|
||||
out_payload = mem[mem_rd_addr];
|
||||
end
|
||||
//assign mem_rd_addr = {rd_segment, mem_next_rd_ptr};
|
||||
|
||||
always_comb
|
||||
begin
|
||||
out_data = out_payload;
|
||||
out_valid = pointer_ctrl_out_valid[rd_segment];
|
||||
end
|
||||
// ---------------------------------
|
||||
// Memory addresses
|
||||
// ---------------------------------
|
||||
assign mem_wr_ptr = pointer_ctrl_wr_ptr[wr_segment];
|
||||
//assign mem_rd_ptr = pointer_ctrl_rd_ptr[rd_segment];
|
||||
//assign mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment];
|
||||
|
||||
assign mem_wr_addr = {wr_segment, mem_wr_ptr};
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Bcos want, empty latency, mean assert read the data will appear on out_data.
|
||||
// And need to jump around different segment of the memory.
|
||||
// So when seeing endofpacket for this current segment, the read address
|
||||
// will jump to next segment at first read address, so that the data will be ready
|
||||
// it is okay to jump to next segment as this is the sequence of all transaction
|
||||
// and they just increment. (standing at segment 0, then for sure next segment 1)
|
||||
// ----------------------------------------------------------------------------
|
||||
wire endofpacket;
|
||||
assign endofpacket = out_payload[0];
|
||||
wire [ADDR_H_W - 1: 0] next_rd_segment;
|
||||
assign next_rd_segment = ((rd_segment + 1'b1) == NUM_SEGMENT) ? '0 : rd_segment + 1'b1;
|
||||
|
||||
always_comb
|
||||
begin
|
||||
if (out_valid && out_ready && endofpacket)
|
||||
begin
|
||||
mem_next_rd_ptr = pointer_ctrl_rd_ptr[next_rd_segment];
|
||||
//mem_rd_addr = {rd_segment + 1'b1, mem_next_rd_ptr};
|
||||
mem_rd_addr = {next_rd_segment, mem_next_rd_ptr};
|
||||
|
||||
end
|
||||
else
|
||||
begin
|
||||
mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment];
|
||||
mem_rd_addr = {rd_segment, mem_next_rd_ptr};
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ---------------------------------
|
||||
// Output signals
|
||||
// ---------------------------------
|
||||
assign in_ready = pointer_ctrl_in_ready[wr_segment];
|
||||
|
||||
// ---------------------------------
|
||||
// Control signals for each segment
|
||||
// ---------------------------------
|
||||
genvar j;
|
||||
generate
|
||||
for (j = 0; j < NUM_SEGMENT; j = j + 1)
|
||||
begin : pointer_signal
|
||||
assign pointer_ctrl_in_valid[j] = (wr_segment == j) && in_valid;
|
||||
assign pointer_ctrl_out_ready[j] = (rd_segment == j) && out_ready;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ---------------------------------
|
||||
// Seperate write and read pointer
|
||||
// for each segment in memory
|
||||
// ---------------------------------
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < NUM_SEGMENT; i = i + 1)
|
||||
begin : each_segment_pointer_controller
|
||||
memory_pointer_controller
|
||||
#(
|
||||
.ADDR_W (ADDR_L_W)
|
||||
) reorder_memory_pointer_controller
|
||||
(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (pointer_ctrl_in_ready[i]),
|
||||
.in_valid (pointer_ctrl_in_valid[i]),
|
||||
.out_ready (pointer_ctrl_out_ready[i]),
|
||||
.out_valid (pointer_ctrl_out_valid[i]),
|
||||
.wr_pointer (pointer_ctrl_wr_ptr[i]),
|
||||
.rd_pointer (pointer_ctrl_rd_ptr[i]),
|
||||
.next_rd_pointer (pointer_ctrl_next_rd_ptr[i])
|
||||
);
|
||||
end // block: each_segment_pointer_controller
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
|
||||
module memory_pointer_controller
|
||||
#(
|
||||
parameter ADDR_W = 4
|
||||
)
|
||||
(
|
||||
// -------------------
|
||||
// Clock
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
// -------------------
|
||||
// Signals
|
||||
// -------------------
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
// -------------------------------
|
||||
// Output write and read pointer
|
||||
// -------------------------------
|
||||
output [ADDR_W - 1 : 0] wr_pointer,
|
||||
output [ADDR_W - 1 : 0] rd_pointer,
|
||||
output [ADDR_W - 1 : 0] next_rd_pointer
|
||||
);
|
||||
|
||||
reg [ADDR_W - 1 : 0] incremented_wr_ptr;
|
||||
reg [ADDR_W - 1 : 0] incremented_rd_ptr;
|
||||
reg [ADDR_W - 1 : 0] wr_ptr;
|
||||
reg [ADDR_W - 1 : 0] rd_ptr;
|
||||
reg [ADDR_W - 1 : 0] next_wr_ptr;
|
||||
reg [ADDR_W - 1 : 0] next_rd_ptr;
|
||||
reg full, empty, next_full, next_empty;
|
||||
reg read, write, internal_out_ready, internal_out_valid;
|
||||
|
||||
assign incremented_wr_ptr = wr_ptr + 1'b1;
|
||||
assign incremented_rd_ptr = rd_ptr + 1'b1;
|
||||
assign next_wr_ptr = write ? incremented_wr_ptr : wr_ptr;
|
||||
assign next_rd_ptr = read ? incremented_rd_ptr : rd_ptr;
|
||||
assign wr_pointer = wr_ptr;
|
||||
assign rd_pointer = rd_ptr;
|
||||
assign next_rd_pointer = next_rd_ptr;
|
||||
|
||||
// -------------------------------
|
||||
// Define write and read signals
|
||||
// --------------------------------
|
||||
// internal read, if it has any valid data
|
||||
// and output are ready to accepts data then a read will be performed.
|
||||
// -------------------------------
|
||||
//assign read = internal_out_ready && internal_out_valid;
|
||||
assign read = internal_out_ready && !empty;
|
||||
assign write = in_ready && in_valid;
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
wr_ptr <= 0;
|
||||
rd_ptr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
wr_ptr <= next_wr_ptr;
|
||||
rd_ptr <= next_rd_ptr;
|
||||
end
|
||||
end
|
||||
// ---------------------------------------------------------------------------
|
||||
// Generate full/empty signal for memory
|
||||
// if read and next read pointer same as write, set empty, write will clear empty
|
||||
// if write and next write pointer same as read, set full, read will clear full
|
||||
// -----------------------------------------------------------------------------
|
||||
always_comb
|
||||
begin
|
||||
next_full = full;
|
||||
next_empty = empty;
|
||||
if (read && !write)
|
||||
begin
|
||||
next_full = 1'b0;
|
||||
if (incremented_rd_ptr == wr_ptr)
|
||||
next_empty = 1'b1;
|
||||
end
|
||||
if (write && !read)
|
||||
begin
|
||||
next_empty = 1'b0;
|
||||
if (incremented_wr_ptr == rd_ptr)
|
||||
next_full = 1'b1;
|
||||
end
|
||||
end // always_comb
|
||||
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
empty <= 1;
|
||||
full <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
empty <= next_empty;
|
||||
full <= next_full;
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------
|
||||
// Control signals
|
||||
// --------------------
|
||||
always_comb
|
||||
begin
|
||||
in_ready = !full;
|
||||
out_valid = !empty;
|
||||
internal_out_ready = out_ready;
|
||||
end // always_comb
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,622 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2011 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_slave_agent
|
||||
#(
|
||||
// Packet parameters
|
||||
parameter PKT_BEGIN_BURST = 81,
|
||||
parameter PKT_DATA_H = 31,
|
||||
parameter PKT_DATA_L = 0,
|
||||
parameter PKT_SYMBOL_W = 8,
|
||||
parameter PKT_BYTEEN_H = 71,
|
||||
parameter PKT_BYTEEN_L = 68,
|
||||
parameter PKT_ADDR_H = 63,
|
||||
parameter PKT_ADDR_L = 32,
|
||||
parameter PKT_TRANS_LOCK = 87,
|
||||
parameter PKT_TRANS_COMPRESSED_READ = 67,
|
||||
parameter PKT_TRANS_POSTED = 66,
|
||||
parameter PKT_TRANS_WRITE = 65,
|
||||
parameter PKT_TRANS_READ = 64,
|
||||
parameter PKT_SRC_ID_H = 74,
|
||||
parameter PKT_SRC_ID_L = 72,
|
||||
parameter PKT_DEST_ID_H = 77,
|
||||
parameter PKT_DEST_ID_L = 75,
|
||||
parameter PKT_BURSTWRAP_H = 85,
|
||||
parameter PKT_BURSTWRAP_L = 82,
|
||||
parameter PKT_BYTE_CNT_H = 81,
|
||||
parameter PKT_BYTE_CNT_L = 78,
|
||||
parameter PKT_PROTECTION_H = 86,
|
||||
parameter PKT_PROTECTION_L = 86,
|
||||
parameter PKT_RESPONSE_STATUS_H = 89,
|
||||
parameter PKT_RESPONSE_STATUS_L = 88,
|
||||
parameter PKT_BURST_SIZE_H = 92,
|
||||
parameter PKT_BURST_SIZE_L = 90,
|
||||
parameter PKT_ORI_BURST_SIZE_L = 93,
|
||||
parameter PKT_ORI_BURST_SIZE_H = 95,
|
||||
parameter ST_DATA_W = 96,
|
||||
parameter ST_CHANNEL_W = 32,
|
||||
|
||||
// Slave parameters
|
||||
parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
|
||||
parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
|
||||
parameter AVS_BURSTCOUNT_W = 4,
|
||||
parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W,
|
||||
|
||||
// Slave agent parameters
|
||||
parameter PREVENT_FIFO_OVERFLOW = 0,
|
||||
parameter SUPPRESS_0_BYTEEN_CMD = 1,
|
||||
parameter USE_READRESPONSE = 0,
|
||||
parameter USE_WRITERESPONSE = 0,
|
||||
|
||||
// Derived slave parameters
|
||||
parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
|
||||
parameter BURST_SIZE_W = 3,
|
||||
|
||||
// Derived FIFO width
|
||||
parameter FIFO_DATA_W = ST_DATA_W + 1,
|
||||
|
||||
// ECC parameter
|
||||
parameter ECC_ENABLE = 0
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// Universal-Avalon anti-slave
|
||||
output [ADDR_W-1:0] m0_address,
|
||||
output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
|
||||
output [AVS_BE_W-1:0] m0_byteenable,
|
||||
output m0_read,
|
||||
input [AVS_DATA_W-1:0] m0_readdata,
|
||||
input m0_waitrequest,
|
||||
output m0_write,
|
||||
output [AVS_DATA_W-1:0] m0_writedata,
|
||||
input m0_readdatavalid,
|
||||
output m0_debugaccess,
|
||||
output m0_lock,
|
||||
input [1:0] m0_response,
|
||||
input m0_writeresponsevalid,
|
||||
|
||||
// Avalon-ST FIFO interfaces.
|
||||
// Note: there's no need to include the "data" field here, at least for
|
||||
// reads, since readdata is filled in from slave info. To keep life
|
||||
// simple, have a data field, but fill it with 0s.
|
||||
// Av-st response fifo source interface
|
||||
output reg [FIFO_DATA_W-1:0] rf_source_data,
|
||||
output rf_source_valid,
|
||||
output rf_source_startofpacket,
|
||||
output rf_source_endofpacket,
|
||||
input rf_source_ready,
|
||||
|
||||
// Av-st response fifo sink interface
|
||||
input [FIFO_DATA_W-1:0] rf_sink_data,
|
||||
input rf_sink_valid,
|
||||
input rf_sink_startofpacket,
|
||||
input rf_sink_endofpacket,
|
||||
output rf_sink_ready,
|
||||
|
||||
// Av-st readdata fifo src interface, data and response
|
||||
// extra 2 bits for storing RESPONSE STATUS
|
||||
output [AVS_DATA_W+1:0] rdata_fifo_src_data,
|
||||
output rdata_fifo_src_valid,
|
||||
input rdata_fifo_src_ready,
|
||||
|
||||
// Av-st readdata fifo sink interface
|
||||
input [AVS_DATA_W+1:0] rdata_fifo_sink_data,
|
||||
input rdata_fifo_sink_valid,
|
||||
output rdata_fifo_sink_ready,
|
||||
input rdata_fifo_sink_error,
|
||||
|
||||
// Av-st sink command packet interface
|
||||
output cp_ready,
|
||||
input cp_valid,
|
||||
input [ST_DATA_W-1:0] cp_data,
|
||||
input [ST_CHANNEL_W-1:0] cp_channel,
|
||||
input cp_startofpacket,
|
||||
input cp_endofpacket,
|
||||
|
||||
// Av-st source response packet interface
|
||||
input rp_ready,
|
||||
output reg rp_valid,
|
||||
output reg [ST_DATA_W-1:0] rp_data,
|
||||
output rp_startofpacket,
|
||||
output rp_endofpacket
|
||||
);
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function log2ceil of 4 = 2
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[63:0] val;
|
||||
reg [63:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
// ------------------------------------------------
|
||||
// Local Parameters
|
||||
// ------------------------------------------------
|
||||
localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1;
|
||||
localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
|
||||
localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
|
||||
localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
|
||||
localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
|
||||
localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
|
||||
localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
|
||||
localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
|
||||
localparam MAX_BURST = 1 << (AVS_BURSTCOUNT_W - 1);
|
||||
localparam BURSTING = (MAX_BURST > PKT_SYMBOLS);
|
||||
|
||||
// ------------------------------------------------
|
||||
// Signals
|
||||
// ------------------------------------------------
|
||||
wire [DATA_W-1:0] cmd_data;
|
||||
wire [BE_W-1:0] cmd_byteen;
|
||||
wire [ADDR_W-1:0] cmd_addr;
|
||||
wire [MID_W-1:0] cmd_mid;
|
||||
wire [SID_W-1:0] cmd_sid;
|
||||
wire cmd_read;
|
||||
wire cmd_write;
|
||||
wire cmd_compressed;
|
||||
wire cmd_posted;
|
||||
wire [BYTE_CNT_W-1:0] cmd_byte_cnt;
|
||||
wire [BURSTWRAP_W-1:0] cmd_burstwrap;
|
||||
wire [BURSTSIZE_W-1:0] cmd_burstsize;
|
||||
wire cmd_debugaccess;
|
||||
|
||||
wire suppress_cmd;
|
||||
wire byteen_asserted;
|
||||
wire suppress_read;
|
||||
wire suppress_write;
|
||||
wire needs_response_synthesis;
|
||||
wire generate_response;
|
||||
|
||||
// Assign command fields
|
||||
assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ];
|
||||
assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
|
||||
assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ];
|
||||
assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ];
|
||||
assign cmd_posted = cp_data[PKT_TRANS_POSTED];
|
||||
assign cmd_write = cp_data[PKT_TRANS_WRITE];
|
||||
assign cmd_read = cp_data[PKT_TRANS_READ];
|
||||
assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
|
||||
assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
|
||||
assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
|
||||
assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
|
||||
assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
|
||||
assign cmd_debugaccess = cp_data[PKT_PROTECTION_L];
|
||||
|
||||
// Local "ready_for_command" signal: deasserted when the agent is unable to accept
|
||||
// another command, e.g. rdv FIFO is full, (local readdata storage is full &&
|
||||
// ~rp_ready), ...
|
||||
// Say, this could depend on the type of command, for example, even if the
|
||||
// rdv FIFO is full, a write request can be accepted. For later.
|
||||
wire ready_for_command;
|
||||
|
||||
wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK];
|
||||
wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
|
||||
wire local_read = cp_valid & cp_data[PKT_TRANS_READ];
|
||||
wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
|
||||
wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
|
||||
|
||||
// num_symbols is PKT_SYMBOLS, appropriately sized.
|
||||
wire [31:0] int_num_symbols = PKT_SYMBOLS;
|
||||
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
|
||||
|
||||
generate
|
||||
if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
|
||||
// ---------------------------------------------------
|
||||
// Backpressure if the slave says to, or if FIFO overflow may occur.
|
||||
//
|
||||
// All commands are backpressured once the FIFO is full
|
||||
// even if they don't need storage. This breaks a long
|
||||
// combinatorial path from the master read/write through
|
||||
// this logic and back to the master via the backpressure
|
||||
// path.
|
||||
//
|
||||
// To avoid a loss of throughput the FIFO will be parameterized
|
||||
// one slot deeper. The extra slot should never be used in normal
|
||||
// operation, but should a slave misbehave and accept one more
|
||||
// read than it should then backpressure will kick in.
|
||||
//
|
||||
// An example: assume a slave with MPRT = 2. It can accept a
|
||||
// command sequence RRWW without backpressuring. If the FIFO is
|
||||
// only 2 deep, we'd backpressure the writes leading to loss of
|
||||
// throughput. If the FIFO is 3 deep, we'll only backpressure when
|
||||
// RRR... which is an illegal condition anyway.
|
||||
// ---------------------------------------------------
|
||||
|
||||
assign ready_for_command = rf_source_ready;
|
||||
assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
|
||||
|
||||
end else begin : no_prevent_fifo_overflow_block
|
||||
|
||||
// Do not suppress the command or the slave will
|
||||
// not be able to waitrequest
|
||||
assign ready_for_command = 1'b1;
|
||||
// Backpressure only if the slave says to.
|
||||
assign cp_ready = ~m0_waitrequest | suppress_cmd;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
|
||||
assign byteen_asserted = |cmd_byteen;
|
||||
assign suppress_read = ~byteen_asserted;
|
||||
assign suppress_write = ~byteen_asserted;
|
||||
assign suppress_cmd = ~byteen_asserted;
|
||||
end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
|
||||
assign byteen_asserted = |cmd_byteen;
|
||||
assign suppress_read = ~byteen_asserted;
|
||||
assign suppress_write = 1'b0;
|
||||
assign suppress_cmd = ~byteen_asserted && cmd_read;
|
||||
end else begin : no_suppress_0_byteen_cmd
|
||||
assign suppress_read = 1'b0;
|
||||
assign suppress_write = 1'b0;
|
||||
assign suppress_cmd = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// -------------------------------------------------------------------
|
||||
// Extract avalon signals from command packet.
|
||||
// -------------------------------------------------------------------
|
||||
// Mask off the lower bits of address.
|
||||
// The burst adapter before this component will break narrow sized packets
|
||||
// into sub-bursts of length 1. However, the packet addresses are preserved,
|
||||
// which means this component may see size-aligned addresses.
|
||||
//
|
||||
// Masking ensures that the addresses seen by an Avalon slave are aligned to
|
||||
// the full data width instead of the size.
|
||||
//
|
||||
// Example:
|
||||
// output from burst adapter (datawidth=4, size=2 bytes):
|
||||
// subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
|
||||
// expected output from slave agent:
|
||||
// subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
|
||||
generate
|
||||
if (BITS_TO_MASK > 0) begin : mask_address
|
||||
|
||||
assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
|
||||
|
||||
end else begin : no_mask_address
|
||||
|
||||
assign m0_address = cmd_addr;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign m0_byteenable = cmd_byteen;
|
||||
assign m0_writedata = cmd_data;
|
||||
|
||||
// Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
|
||||
// this sort of burst exists only in merlin fabric ST packets. What to do
|
||||
// if we see such a burst? All beats in that burst need to be transmitted
|
||||
// to the slave so we have enough space-time for byteenable expression.
|
||||
//
|
||||
// There can be multiple bursts in a packet, but only one beat per burst
|
||||
// in <most> cases. The exception is when we've decided not to insert a
|
||||
// burst adapter for efficiency reasons, in which case this agent is also
|
||||
// responsible for driving burstcount to 1 on each beat of an uncompressed
|
||||
// read burst.
|
||||
|
||||
assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
|
||||
|
||||
generate
|
||||
// AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount
|
||||
// from a sub-range, or 0-pad, as appropriate.
|
||||
if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
|
||||
wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
|
||||
assign m0_burstcount = (local_read & ~local_compressed_read) ?
|
||||
{zero_pad, num_symbols} :
|
||||
{zero_pad, cmd_byte_cnt};
|
||||
end
|
||||
else begin : m0_burstcount_no_pad
|
||||
assign m0_burstcount = (local_read & ~local_compressed_read) ?
|
||||
num_symbols[AVS_BURSTCOUNT_W-1:0] :
|
||||
cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign m0_write = ready_for_command & local_write & !suppress_write;
|
||||
assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write);
|
||||
assign m0_debugaccess = cmd_debugaccess;
|
||||
|
||||
// -------------------------------------------------------------------
|
||||
// Indirection layer for response packet values. Some may always wire
|
||||
// directly from the slave translator; others will no doubt emerge from
|
||||
// various FIFOs.
|
||||
// What to put in resp_data when a write occured? Answer: it does not
|
||||
// matter, because only response status is needed for non-posted writes,
|
||||
// and the packet already has a field for that.
|
||||
//
|
||||
// We use the rdata_fifo to store write responses as well. This allows us
|
||||
// to handle backpressure on the response path, and allows write response
|
||||
// merging.
|
||||
assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid;
|
||||
assign rdata_fifo_src_data = {m0_response, m0_readdata};
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Generate a token when read commands are suppressed. The token
|
||||
// is stored in the response FIFO, and will be used to synthesize
|
||||
// a read response. The same token is used for non-posted write
|
||||
// response synthesis.
|
||||
//
|
||||
// Note: this token is not generated for suppressed uncompressed read cycles;
|
||||
// the burst uncompression logic at the read side of the response FIFO
|
||||
// generates the correct number of responses.
|
||||
//
|
||||
// When the slave can return the response, let it do its job. Don't
|
||||
// synthesize a response in that case, unless we've suppressed the
|
||||
// the last transfer in a write sub-burst.
|
||||
// ------------------------------------------------------------------
|
||||
wire write_end_of_subburst;
|
||||
assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) ||
|
||||
(!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
|
||||
(USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
|
||||
|
||||
// Avalon-ST interfaces to external response FIFO.
|
||||
//
|
||||
// For efficiency, when synthesizing a write response we only store a non-posted write
|
||||
// transaction at its endofpacket, even if it was split into multiple sub-bursts.
|
||||
//
|
||||
// When not synthesizing write responses, we store each sub-burst in the FIFO.
|
||||
// Each sub-burst to the slave will return a response, which corresponds to one
|
||||
// entry in the FIFO. We merge all the sub-burst responses on the final
|
||||
// sub-burst and send it on the response channel.
|
||||
|
||||
wire internal_cp_endofburst;
|
||||
wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
|
||||
wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
|
||||
|
||||
assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
|
||||
assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
|
||||
assign write_end_of_subburst = local_write & internal_cp_endofburst;
|
||||
|
||||
assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
|
||||
& ready_for_command & cp_ready;
|
||||
assign rf_source_startofpacket = cp_startofpacket;
|
||||
assign rf_source_endofpacket = cp_endofpacket;
|
||||
always @* begin
|
||||
// default: assign every command packet field to the response FIFO...
|
||||
rf_source_data = {1'b0, cp_data};
|
||||
|
||||
// ... and override select fields as needed.
|
||||
rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis;
|
||||
rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}};
|
||||
rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen;
|
||||
rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr;
|
||||
rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed;
|
||||
rf_source_data[PKT_TRANS_POSTED] = cmd_posted;
|
||||
rf_source_data[PKT_TRANS_WRITE] = cmd_write;
|
||||
rf_source_data[PKT_TRANS_READ] = cmd_read;
|
||||
rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid;
|
||||
rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid;
|
||||
rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt;
|
||||
rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap;
|
||||
rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize;
|
||||
rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0;
|
||||
rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess;
|
||||
end
|
||||
|
||||
wire uncompressor_source_valid;
|
||||
wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
|
||||
wire last_write_response;
|
||||
|
||||
// last_write_response indicates the last response of the broken-up write burst (sub-bursts).
|
||||
// At this time, the final merged response is sent, and rp_valid is only asserted
|
||||
// once for the whole burst.
|
||||
generate
|
||||
if (USE_WRITERESPONSE) begin
|
||||
assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
|
||||
always @* begin
|
||||
if (rf_sink_data[PKT_TRANS_WRITE] == 1)
|
||||
rp_valid = (rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED];
|
||||
else
|
||||
rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
|
||||
end
|
||||
end else begin
|
||||
assign last_write_response = 1'b0;
|
||||
always @* begin
|
||||
rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Response merging
|
||||
// ------------------------------------------------------------------
|
||||
reg [1:0] current_response;
|
||||
reg [1:0] response_merged;
|
||||
generate
|
||||
if (USE_WRITERESPONSE) begin : response_merging_all
|
||||
reg first_write_response;
|
||||
reg reset_merged_output;
|
||||
reg [1:0] previous_response_in;
|
||||
reg [1:0] previous_response;
|
||||
|
||||
always_ff @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
first_write_response <= 1'b1;
|
||||
end
|
||||
else begin // Merging work for write response, for read: previous_response_in = current_response
|
||||
if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
|
||||
first_write_response <= 1'b0;
|
||||
if (rf_sink_endofpacket)
|
||||
first_write_response <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
|
||||
reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
|
||||
previous_response_in = reset_merged_output ? current_response : previous_response;
|
||||
response_merged = current_response >= previous_response ? current_response: previous_response_in;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
previous_response <= 2'b00;
|
||||
end
|
||||
else begin
|
||||
if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
|
||||
previous_response <= response_merged;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin : response_merging_read_only
|
||||
always @* begin
|
||||
current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] |
|
||||
{2{rdata_fifo_sink_error}};
|
||||
response_merged = current_response;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign generate_response = rf_sink_data[FIFO_DATA_W-1];
|
||||
|
||||
wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
|
||||
wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
|
||||
wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
|
||||
wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
|
||||
wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
|
||||
// a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
|
||||
wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;
|
||||
|
||||
wire [BYTE_CNT_W-1:0] burst_byte_cnt;
|
||||
wire [BURSTWRAP_W-1:0] rp_burstwrap;
|
||||
wire [ADDR_W-1:0] rp_address;
|
||||
wire rp_is_compressed;
|
||||
wire ready_for_response;
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// We're typically ready for a response if the network is ready. There
|
||||
// is one exception:
|
||||
//
|
||||
// If the slave issues write responses, we only issue a merged response on
|
||||
// the final sub-burst. As a result, we only care about response channel
|
||||
// availability on the final burst when we send out the merged response.
|
||||
// ------------------------------------------------------------------
|
||||
assign ready_for_response = (USE_WRITERESPONSE) ?
|
||||
rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]:
|
||||
rp_ready;
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Backpressure the readdata fifo if we're supposed to synthesize a response.
|
||||
// This may be a read response (for suppressed reads) or a write response
|
||||
// (for non-posted writes).
|
||||
// ------------------------------------------------------------------
|
||||
assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
|
||||
|
||||
always @* begin
|
||||
// By default, return all fields...
|
||||
rp_data = rf_sink_data[ST_DATA_W - 1 : 0];
|
||||
|
||||
// ... and override specific fields.
|
||||
rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0];
|
||||
// Assignments directly from the response fifo.
|
||||
rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED];
|
||||
rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE];
|
||||
rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
|
||||
rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
|
||||
rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
|
||||
rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
|
||||
|
||||
// Burst uncompressor assignments
|
||||
rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address;
|
||||
rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap;
|
||||
rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt;
|
||||
rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
|
||||
rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed;
|
||||
|
||||
rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged;
|
||||
rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize;
|
||||
// bounce the original size back to the master untouched
|
||||
rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L] = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
|
||||
end
|
||||
|
||||
// ------------------------------------------------------------------
|
||||
// Note: the burst uncompressor may be asked to generate responses for
|
||||
// write packets; these are treated the same as single-cycle uncompressed
|
||||
// reads.
|
||||
// ------------------------------------------------------------------
|
||||
altera_merlin_burst_uncompressor #(
|
||||
.ADDR_W (ADDR_W),
|
||||
.BURSTWRAP_W (BURSTWRAP_W),
|
||||
.BYTE_CNT_W (BYTE_CNT_W),
|
||||
.PKT_SYMBOLS (PKT_SYMBOLS),
|
||||
.BURST_SIZE_W (BURSTSIZE_W)
|
||||
) uncompressor (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.sink_startofpacket (rf_sink_startofpacket_wire),
|
||||
.sink_endofpacket (rf_sink_endofpacket),
|
||||
.sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)),
|
||||
.sink_ready (rf_sink_ready),
|
||||
.sink_addr (rf_sink_addr),
|
||||
.sink_burstwrap (rf_sink_burstwrap),
|
||||
.sink_byte_cnt (rf_sink_byte_cnt),
|
||||
.sink_is_compressed (rf_sink_compressed),
|
||||
.sink_burstsize (rf_sink_burstsize),
|
||||
|
||||
.source_startofpacket (rp_startofpacket),
|
||||
.source_endofpacket (rp_endofpacket),
|
||||
.source_valid (uncompressor_source_valid),
|
||||
.source_ready (ready_for_response),
|
||||
.source_addr (rp_address),
|
||||
.source_burstwrap (rp_burstwrap),
|
||||
.source_byte_cnt (burst_byte_cnt),
|
||||
.source_is_compressed (rp_is_compressed),
|
||||
.source_burstsize (uncompressor_burstsize)
|
||||
);
|
||||
|
||||
//--------------------------------------
|
||||
// Assertion: In case slave support response. The slave needs return response in order
|
||||
// Ex: non-posted write followed by a read: write response must complete before read data
|
||||
//--------------------------------------
|
||||
// synthesis translate_off
|
||||
ERROR_write_response_and_read_response_cannot_happen_same_time:
|
||||
assert property ( @(posedge clk)
|
||||
disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid)
|
||||
);
|
||||
|
||||
// synthesis translate_on
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,482 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------
|
||||
// Merlin Slave Translator
|
||||
//
|
||||
// Translates Universal Avalon MM Slave
|
||||
// to any Avalon MM Slave
|
||||
// -------------------------------------
|
||||
//
|
||||
//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
|
||||
//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
|
||||
//The key feature here is that no same cycle turnaround data is processed through the fabric.
|
||||
|
||||
//import avalon_utilities_pkg::*;
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_slave_translator #(
|
||||
parameter
|
||||
//Widths
|
||||
AV_ADDRESS_W = 32,
|
||||
AV_DATA_W = 32,
|
||||
AV_BURSTCOUNT_W = 4,
|
||||
AV_BYTEENABLE_W = 4,
|
||||
UAV_BYTEENABLE_W = 4,
|
||||
|
||||
//Read Latency
|
||||
AV_READLATENCY = 1,
|
||||
|
||||
//Timing
|
||||
AV_READ_WAIT_CYCLES = 0,
|
||||
AV_WRITE_WAIT_CYCLES = 0,
|
||||
AV_SETUP_WAIT_CYCLES = 0,
|
||||
AV_DATA_HOLD_CYCLES = 0,
|
||||
|
||||
//Optional Port Declarations
|
||||
USE_READDATAVALID = 1,
|
||||
USE_WAITREQUEST = 1,
|
||||
USE_READRESPONSE = 0,
|
||||
USE_WRITERESPONSE = 0,
|
||||
|
||||
//Variable Addressing
|
||||
AV_SYMBOLS_PER_WORD = 4,
|
||||
AV_ADDRESS_SYMBOLS = 0,
|
||||
AV_BURSTCOUNT_SYMBOLS = 0,
|
||||
BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
|
||||
UAV_ADDRESS_W = 38,
|
||||
UAV_BURSTCOUNT_W = 10,
|
||||
UAV_DATA_W = 32,
|
||||
|
||||
AV_CONSTANT_BURST_BEHAVIOR = 0,
|
||||
UAV_CONSTANT_BURST_BEHAVIOR = 0,
|
||||
CHIPSELECT_THROUGH_READLATENCY = 0,
|
||||
|
||||
// Tightly-Coupled Options
|
||||
USE_UAV_CLKEN = 0,
|
||||
AV_REQUIRE_UNALIGNED_ADDRESSES = 0
|
||||
) (
|
||||
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// -------------------
|
||||
// Universal Avalon Slave
|
||||
// -------------------
|
||||
|
||||
input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
|
||||
input wire [UAV_DATA_W - 1 : 0] uav_writedata,
|
||||
input wire uav_write,
|
||||
input wire uav_read,
|
||||
input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
|
||||
input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
|
||||
input wire uav_lock,
|
||||
input wire uav_debugaccess,
|
||||
input wire uav_clken,
|
||||
|
||||
output logic uav_readdatavalid,
|
||||
output logic uav_waitrequest,
|
||||
output logic [UAV_DATA_W - 1 : 0] uav_readdata,
|
||||
output logic [1:0] uav_response,
|
||||
// input wire uav_writeresponserequest,
|
||||
output logic uav_writeresponsevalid,
|
||||
|
||||
// -------------------
|
||||
// Customizable Avalon Master
|
||||
// -------------------
|
||||
output logic [AV_ADDRESS_W - 1 : 0] av_address,
|
||||
output logic [AV_DATA_W - 1 : 0] av_writedata,
|
||||
output logic av_write,
|
||||
output logic av_read,
|
||||
output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
|
||||
output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
|
||||
output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
|
||||
output logic av_begintransfer,
|
||||
output wire av_chipselect,
|
||||
output logic av_beginbursttransfer,
|
||||
output logic av_lock,
|
||||
output wire av_clken,
|
||||
output wire av_debugaccess,
|
||||
output wire av_outputenable,
|
||||
|
||||
input logic [AV_DATA_W - 1 : 0] av_readdata,
|
||||
input logic av_readdatavalid,
|
||||
input logic av_waitrequest,
|
||||
|
||||
input logic [1:0] av_response,
|
||||
// output logic av_writeresponserequest,
|
||||
input wire av_writeresponsevalid
|
||||
|
||||
);
|
||||
|
||||
function integer clog2_plusone;
|
||||
input [31:0] Depth;
|
||||
integer i;
|
||||
begin
|
||||
i = Depth;
|
||||
for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer max;
|
||||
//returns the larger of two passed arguments
|
||||
input [31:0] one;
|
||||
input [31:0] two;
|
||||
if(one > two)
|
||||
max=one;
|
||||
else
|
||||
max=two;
|
||||
endfunction // int
|
||||
|
||||
localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
|
||||
localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
|
||||
localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
|
||||
localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
|
||||
localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
|
||||
localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
|
||||
localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
|
||||
AV_ADDRESS_W :
|
||||
UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
|
||||
localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
|
||||
AV_BURSTCOUNT_W :
|
||||
UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
|
||||
localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
|
||||
|
||||
|
||||
// Calculate the symbols per word as the power of 2 extended symbols per word
|
||||
wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
|
||||
wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
|
||||
|
||||
// +--------------------------------
|
||||
// |Backwards Compatibility Signals
|
||||
// +--------------------------------
|
||||
assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
|
||||
assign av_debugaccess = uav_debugaccess;
|
||||
|
||||
// +-------------------
|
||||
// |Passthru Signals
|
||||
// +-------------------
|
||||
|
||||
reg [1 : 0] av_response_delayed;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
av_response_delayed <= 2'b0;
|
||||
end else begin
|
||||
av_response_delayed <= av_response;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb
|
||||
begin
|
||||
if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
|
||||
uav_response = '0;
|
||||
end else begin
|
||||
if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
|
||||
uav_response = av_response;
|
||||
end else begin
|
||||
uav_response = av_response_delayed;
|
||||
end
|
||||
end
|
||||
end
|
||||
// assign av_writeresponserequest = uav_writeresponserequest;
|
||||
assign uav_writeresponsevalid = av_writeresponsevalid;
|
||||
|
||||
//-------------------------
|
||||
//Writedata and Byteenable
|
||||
//-------------------------
|
||||
|
||||
always@* begin
|
||||
av_byteenable = '0;
|
||||
av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_writedata = '0;
|
||||
av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
|
||||
end
|
||||
|
||||
// +-------------------
|
||||
// |Calculated Signals
|
||||
// +-------------------
|
||||
|
||||
logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
|
||||
|
||||
function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
|
||||
input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
|
||||
|
||||
for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
|
||||
if(byteenable[i] == 1) begin
|
||||
return i;
|
||||
end
|
||||
end
|
||||
|
||||
return '0;
|
||||
|
||||
endfunction
|
||||
|
||||
reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
|
||||
reg [AV_ADDRESS_W - 1 : 0] address_reg;
|
||||
always@(posedge clk, posedge reset) begin
|
||||
if(reset) begin
|
||||
burstcount_reg <= '0;
|
||||
address_reg <= '0;
|
||||
end else begin
|
||||
burstcount_reg <= burstcount_reg;
|
||||
address_reg <= address_reg;
|
||||
if(av_beginbursttransfer) begin
|
||||
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
|
||||
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
|
||||
|
||||
always@* begin
|
||||
if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
|
||||
temp_wire = decode_byteenable(uav_byteenable);
|
||||
real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
|
||||
end else begin
|
||||
real_uav_address = uav_address;
|
||||
end
|
||||
|
||||
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
|
||||
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
|
||||
av_address = address_reg;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
|
||||
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
|
||||
av_burstcount = burstcount_reg;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
av_lock = uav_lock;
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Writebyteenable Assignment
|
||||
// -------------------
|
||||
always@* begin
|
||||
av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Waitrequest Assignment
|
||||
// -------------------
|
||||
|
||||
reg av_waitrequest_generated;
|
||||
reg av_waitrequest_generated_read;
|
||||
reg av_waitrequest_generated_write;
|
||||
reg waitrequest_reset_override;
|
||||
reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset) begin
|
||||
wait_latency_counter <= '0;
|
||||
waitrequest_reset_override <= 1'h1;
|
||||
end else begin
|
||||
waitrequest_reset_override <= 1'h0;
|
||||
wait_latency_counter <= '0;
|
||||
if( ~uav_waitrequest | waitrequest_reset_override )
|
||||
wait_latency_counter <= '0;
|
||||
else if( uav_read | uav_write )
|
||||
wait_latency_counter <= wait_latency_counter + 1'h1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @* begin
|
||||
|
||||
av_read = uav_read;
|
||||
av_write = uav_write;
|
||||
av_waitrequest_generated = 1'h1;
|
||||
av_waitrequest_generated_read = 1'h1;
|
||||
av_waitrequest_generated_write = 1'h1;
|
||||
|
||||
if(LOG2_OF_LATENCY_SUM == 1)
|
||||
av_waitrequest_generated = 0;
|
||||
|
||||
if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
|
||||
av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
|
||||
av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
|
||||
av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
|
||||
av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
|
||||
|
||||
if(uav_write)
|
||||
av_waitrequest_generated = av_waitrequest_generated_write;
|
||||
else
|
||||
av_waitrequest_generated = av_waitrequest_generated_read;
|
||||
|
||||
end
|
||||
|
||||
if(USE_WAITREQUEST) begin
|
||||
uav_waitrequest = av_waitrequest;
|
||||
end else begin
|
||||
uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// --------------
|
||||
// Readdata Assignment
|
||||
// --------------
|
||||
|
||||
reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
|
||||
|
||||
always@(posedge clk, posedge reset) begin
|
||||
if(reset)
|
||||
av_readdata_pre <= 'b0;
|
||||
else
|
||||
av_readdata_pre <= av_readdata;
|
||||
end
|
||||
|
||||
always@* begin
|
||||
uav_readdata = {UAV_DATA_W{1'b0}};
|
||||
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
|
||||
uav_readdata[AV_DATA_W-1:0] = av_readdata;
|
||||
end else begin
|
||||
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Readdatavalid Assigment
|
||||
// -------------------
|
||||
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
|
||||
reg top_read_latency_shift_reg;
|
||||
|
||||
always@* begin
|
||||
uav_readdatavalid=top_read_latency_shift_reg;
|
||||
if(USE_READDATAVALID) begin
|
||||
uav_readdatavalid = av_readdatavalid;
|
||||
end
|
||||
end
|
||||
|
||||
always@* begin
|
||||
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
|
||||
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
|
||||
top_read_latency_shift_reg=read_latency_shift_reg;
|
||||
end
|
||||
if (AV_READLATENCY > 1) begin
|
||||
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if (reset) begin
|
||||
read_latency_shift_reg <= '0;
|
||||
end else if (av_clken) begin
|
||||
read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
|
||||
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
|
||||
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ------------
|
||||
// Chipselect and OutputEnable
|
||||
// ------------
|
||||
reg av_chipselect_pre;
|
||||
wire cs_extension;
|
||||
reg av_outputenable_pre;
|
||||
|
||||
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
|
||||
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
|
||||
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset)
|
||||
av_outputenable_pre <= 1'b0;
|
||||
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
|
||||
av_outputenable_pre <= 0;
|
||||
else
|
||||
av_outputenable_pre <= cs_extension | uav_read;
|
||||
end
|
||||
|
||||
always@(posedge reset, posedge clk) begin
|
||||
if(reset) begin
|
||||
av_chipselect_pre <= 1'b0;
|
||||
end else begin
|
||||
av_chipselect_pre <= 1'b0;
|
||||
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
|
||||
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
|
||||
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
|
||||
if(uav_read) begin
|
||||
av_chipselect_pre <= 1'b1;
|
||||
end else if(cs_extension == 1) begin
|
||||
av_chipselect_pre <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Begintransfer Assigment
|
||||
// -------------------
|
||||
reg end_begintransfer;
|
||||
|
||||
always@* begin
|
||||
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
|
||||
end
|
||||
|
||||
always@ ( posedge clk or posedge reset ) begin
|
||||
if(reset) begin
|
||||
end_begintransfer <= 1'b0;
|
||||
end else begin
|
||||
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
|
||||
end_begintransfer <= 1'b1;
|
||||
else if(uav_waitrequest)
|
||||
end_begintransfer <= end_begintransfer;
|
||||
else
|
||||
end_begintransfer <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Beginbursttransfer Assigment
|
||||
// -------------------
|
||||
reg end_beginbursttransfer;
|
||||
reg in_transfer;
|
||||
|
||||
always@* begin
|
||||
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
|
||||
end
|
||||
|
||||
always@ ( posedge clk or posedge reset ) begin
|
||||
if(reset) begin
|
||||
end_beginbursttransfer <= 1'b0;
|
||||
in_transfer <= 1'b0;
|
||||
end else begin
|
||||
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
|
||||
if(uav_write && uav_burstcount == symbols_per_word)
|
||||
in_transfer <=1'b0;
|
||||
else if(uav_write)
|
||||
in_transfer <=1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,787 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter.sv#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -----------------------------------------------------
|
||||
// Merlin Traffic Limiter
|
||||
//
|
||||
// Ensures that non-posted transaction responses are returned
|
||||
// in order of request. Out-of-order responses can happen
|
||||
// when a master does a non-posted transaction on a slave
|
||||
// while responses are pending from a different slave.
|
||||
//
|
||||
// Examples:
|
||||
// 1) read to any latent slave, followed by a read to a
|
||||
// variable-latent slave
|
||||
// 2) read to any fixed-latency slave, followed by a read
|
||||
// to another fixed-latency slave whose fixed latency is smaller.
|
||||
// 3) non-posted write to any latent slave, followed by a non-posted
|
||||
// write or read to any variable-latent slave.
|
||||
//
|
||||
// This component has two implementation modes that ensure
|
||||
// response order, controlled by the REORDER parameter.
|
||||
//
|
||||
// 0) Backpressure to prevent a master from switching slaves
|
||||
// until all outstanding responses have returned. We also
|
||||
// have to suppress the non-posted transaction, obviously.
|
||||
//
|
||||
// 1) Reorder the responses as they return using a memory
|
||||
// block.
|
||||
// -----------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// altera message_off 10036
|
||||
module altera_merlin_traffic_limiter
|
||||
#(
|
||||
parameter
|
||||
PKT_TRANS_POSTED = 1,
|
||||
PKT_DEST_ID_H = 0,
|
||||
PKT_DEST_ID_L = 0,
|
||||
PKT_SRC_ID_H = 0,
|
||||
PKT_SRC_ID_L = 0,
|
||||
PKT_BYTE_CNT_H = 0,
|
||||
PKT_BYTE_CNT_L = 0,
|
||||
PKT_BYTEEN_H = 0,
|
||||
PKT_BYTEEN_L = 0,
|
||||
PKT_TRANS_WRITE = 0,
|
||||
PKT_TRANS_READ = 0,
|
||||
ST_DATA_W = 72,
|
||||
ST_CHANNEL_W = 32,
|
||||
|
||||
MAX_OUTSTANDING_RESPONSES = 1,
|
||||
PIPELINED = 0,
|
||||
ENFORCE_ORDER = 1,
|
||||
|
||||
// -------------------------------------
|
||||
// internal: allows optimization between this
|
||||
// component and the demux
|
||||
// -------------------------------------
|
||||
VALID_WIDTH = 1,
|
||||
|
||||
// -------------------------------------
|
||||
// Prevents all RAW and WAR hazards by waiting for
|
||||
// responses to return before issuing a command
|
||||
// with different direction.
|
||||
//
|
||||
// This is intended for Avalon masters which are
|
||||
// connected to AXI slaves, because of the differing
|
||||
// ordering models for the protocols.
|
||||
//
|
||||
// If PREVENT_HAZARDS is 1, then the current implementation
|
||||
// needs to know whether incoming writes will be posted or
|
||||
// not at compile-time. Only one of SUPPORTS_POSTED_WRITES
|
||||
// and SUPPORTS_NONPOSTED_WRITES can be 1.
|
||||
//
|
||||
// When PREVENT_HAZARDS is 0 there is no such restriction.
|
||||
//
|
||||
// It is possible to be less restrictive for memories.
|
||||
// -------------------------------------
|
||||
PREVENT_HAZARDS = 0,
|
||||
|
||||
// -------------------------------------
|
||||
// Used only when hazard prevention is on, but may be used
|
||||
// for optimization work in the future.
|
||||
// -------------------------------------
|
||||
SUPPORTS_POSTED_WRITES = 1,
|
||||
SUPPORTS_NONPOSTED_WRITES = 0,
|
||||
|
||||
// -------------------------------------------------
|
||||
// Enables the reorder buffer which allows a master to
|
||||
// switch slaves while responses are pending.
|
||||
// Reponses will be reordered following command issue order.
|
||||
// -------------------------------------------------
|
||||
REORDER = 0
|
||||
)
|
||||
(
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Command
|
||||
// -------------------
|
||||
input cmd_sink_valid,
|
||||
input [ST_DATA_W-1 : 0] cmd_sink_data,
|
||||
input [ST_CHANNEL_W-1 : 0] cmd_sink_channel,
|
||||
input cmd_sink_startofpacket,
|
||||
input cmd_sink_endofpacket,
|
||||
output cmd_sink_ready,
|
||||
|
||||
output reg [VALID_WIDTH-1 : 0] cmd_src_valid,
|
||||
output reg [ST_DATA_W-1 : 0] cmd_src_data,
|
||||
output reg [ST_CHANNEL_W-1 : 0] cmd_src_channel,
|
||||
output reg cmd_src_startofpacket,
|
||||
output reg cmd_src_endofpacket,
|
||||
input cmd_src_ready,
|
||||
|
||||
// -------------------
|
||||
// Response
|
||||
// -------------------
|
||||
input rsp_sink_valid,
|
||||
input [ST_DATA_W-1 : 0] rsp_sink_data,
|
||||
input [ST_CHANNEL_W-1 : 0] rsp_sink_channel,
|
||||
input rsp_sink_startofpacket,
|
||||
input rsp_sink_endofpacket,
|
||||
output reg rsp_sink_ready,
|
||||
|
||||
output reg rsp_src_valid,
|
||||
output reg [ST_DATA_W-1 : 0] rsp_src_data,
|
||||
output reg [ST_CHANNEL_W-1 : 0] rsp_src_channel,
|
||||
output reg rsp_src_startofpacket,
|
||||
output reg rsp_src_endofpacket,
|
||||
input rsp_src_ready
|
||||
);
|
||||
|
||||
// -------------------------------------
|
||||
// Local Parameters
|
||||
// -------------------------------------
|
||||
localparam DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
|
||||
localparam COUNTER_W = log2ceil(MAX_OUTSTANDING_RESPONSES + 1);
|
||||
localparam PAYLOAD_W = ST_DATA_W + ST_CHANNEL_W + 4;
|
||||
localparam NUMSYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
|
||||
localparam MAX_DEST_ID = 1 << (DEST_ID_W);
|
||||
localparam PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Memory Parameters
|
||||
// ------------------------------------------------------
|
||||
localparam MAX_BYTE_CNT = 1 << (PKT_BYTE_CNT_W);
|
||||
localparam MAX_BURST_LENGTH = log2ceil(MAX_BYTE_CNT/NUMSYMBOLS);
|
||||
|
||||
// Memory stores packet width, including sop and eop
|
||||
localparam MEM_W = ST_DATA_W + ST_CHANNEL_W + 1 + 1;
|
||||
localparam MEM_DEPTH = MAX_OUTSTANDING_RESPONSES * (MAX_BYTE_CNT/NUMSYMBOLS);
|
||||
|
||||
// -----------------------------------------------------
|
||||
// Input Stage
|
||||
//
|
||||
// Figure out if the destination id has changed
|
||||
// -----------------------------------------------------
|
||||
wire stage1_dest_changed;
|
||||
wire stage1_trans_changed;
|
||||
wire [PAYLOAD_W-1 : 0] stage1_payload;
|
||||
wire in_nonposted_cmd;
|
||||
reg [ST_CHANNEL_W-1:0] last_channel;
|
||||
wire [DEST_ID_W-1 : 0] dest_id;
|
||||
reg [DEST_ID_W-1 : 0] last_dest_id;
|
||||
reg was_write;
|
||||
wire is_write;
|
||||
wire suppress;
|
||||
wire save_dest_id;
|
||||
|
||||
wire suppress_change_dest_id;
|
||||
wire suppress_max_outstanding;
|
||||
wire suppress_change_trans_but_not_dest;
|
||||
wire suppress_change_trans_for_one_slave;
|
||||
|
||||
generate if (PREVENT_HAZARDS == 1) begin : convert_posted_to_nonposted_block
|
||||
assign in_nonposted_cmd = 1'b1;
|
||||
end else begin : non_posted_cmd_assignment_block
|
||||
assign in_nonposted_cmd = (cmd_sink_data[PKT_TRANS_POSTED] == 0);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ------------------------------------
|
||||
// Optimization: for the unpipelined case, we can save the destid if
|
||||
// this is an unsuppressed nonposted command. This eliminates
|
||||
// dependence on the backpressure signal.
|
||||
//
|
||||
// Not a problem for the pipelined case.
|
||||
// ------------------------------------
|
||||
generate
|
||||
if (PIPELINED) begin : pipelined_save_dest_id
|
||||
assign save_dest_id = cmd_sink_valid & cmd_sink_ready & in_nonposted_cmd;
|
||||
end else begin : unpipelined_save_dest_id
|
||||
assign save_dest_id = cmd_sink_valid & ~(suppress_change_dest_id | suppress_max_outstanding) & in_nonposted_cmd;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
last_dest_id <= 0;
|
||||
last_channel <= 0;
|
||||
was_write <= 0;
|
||||
end
|
||||
else if (save_dest_id) begin
|
||||
last_dest_id <= dest_id;
|
||||
last_channel <= cmd_sink_channel;
|
||||
was_write <= is_write;
|
||||
end
|
||||
end
|
||||
|
||||
assign dest_id = cmd_sink_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
|
||||
assign is_write = cmd_sink_data[PKT_TRANS_WRITE];
|
||||
assign stage1_dest_changed = (last_dest_id != dest_id);
|
||||
assign stage1_trans_changed = (was_write != is_write);
|
||||
|
||||
assign stage1_payload = {
|
||||
cmd_sink_data,
|
||||
cmd_sink_channel,
|
||||
cmd_sink_startofpacket,
|
||||
cmd_sink_endofpacket,
|
||||
stage1_dest_changed,
|
||||
stage1_trans_changed };
|
||||
|
||||
// -----------------------------------------------------
|
||||
// (Optional) pipeline between input and output
|
||||
// -----------------------------------------------------
|
||||
wire stage2_valid;
|
||||
reg stage2_ready;
|
||||
wire [PAYLOAD_W-1 : 0] stage2_payload;
|
||||
|
||||
generate
|
||||
if (PIPELINED == 1) begin : pipelined_limiter
|
||||
altera_avalon_st_pipeline_base
|
||||
#(
|
||||
.BITS_PER_SYMBOL(PAYLOAD_W)
|
||||
) stage1_pipe (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (cmd_sink_ready),
|
||||
.in_valid (cmd_sink_valid),
|
||||
.in_data (stage1_payload),
|
||||
.out_valid (stage2_valid),
|
||||
.out_ready (stage2_ready),
|
||||
.out_data (stage2_payload)
|
||||
);
|
||||
end else begin : unpipelined_limiter
|
||||
assign stage2_valid = cmd_sink_valid;
|
||||
assign stage2_payload = stage1_payload;
|
||||
assign cmd_sink_ready = stage2_ready;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// -----------------------------------------------------
|
||||
// Output Stage
|
||||
// -----------------------------------------------------
|
||||
wire [ST_DATA_W-1 : 0] stage2_data;
|
||||
wire [ST_CHANNEL_W-1:0] stage2_channel;
|
||||
wire stage2_startofpacket;
|
||||
wire stage2_endofpacket;
|
||||
wire stage2_dest_changed;
|
||||
wire stage2_trans_changed;
|
||||
reg has_pending_responses;
|
||||
reg [COUNTER_W-1 : 0] pending_response_count;
|
||||
reg [COUNTER_W-1 : 0] next_pending_response_count;
|
||||
wire nonposted_cmd;
|
||||
wire nonposted_cmd_accepted;
|
||||
wire response_accepted;
|
||||
wire response_sink_accepted;
|
||||
wire response_src_accepted;
|
||||
wire count_is_1;
|
||||
wire count_is_0;
|
||||
reg internal_valid;
|
||||
wire [VALID_WIDTH-1:0] wide_valid;
|
||||
|
||||
assign { stage2_data,
|
||||
stage2_channel,
|
||||
stage2_startofpacket,
|
||||
stage2_endofpacket,
|
||||
stage2_dest_changed,
|
||||
stage2_trans_changed } = stage2_payload;
|
||||
|
||||
generate if (PREVENT_HAZARDS == 1) begin : stage2_nonposted_block
|
||||
assign nonposted_cmd = 1'b1;
|
||||
end else begin
|
||||
assign nonposted_cmd = (stage2_data[PKT_TRANS_POSTED] == 0);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign nonposted_cmd_accepted = nonposted_cmd && internal_valid && (cmd_src_ready && cmd_src_endofpacket);
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// Use the sink's control signals here, because write responses may be dropped
|
||||
// when hazard prevention is on.
|
||||
//
|
||||
// When case REORDER, move all side to rsp_source as all packets from rsp_sink will
|
||||
// go in the reorder memory.
|
||||
// One special case when PREVENT_HAZARD is on, need to use reorder_memory_valid
|
||||
// as the rsp_source will drop
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
assign response_sink_accepted = rsp_sink_valid && rsp_sink_ready && rsp_sink_endofpacket;
|
||||
// Avoid Qis warning when incase, no REORDER, the signal reorder_mem_valid is not in used.
|
||||
wire reorder_mem_out_valid;
|
||||
wire reorder_mem_valid;
|
||||
generate
|
||||
if (REORDER) begin
|
||||
assign reorder_mem_out_valid = reorder_mem_valid;
|
||||
end else begin
|
||||
assign reorder_mem_out_valid = '0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign response_src_accepted = reorder_mem_out_valid & rsp_src_ready & rsp_src_endofpacket;
|
||||
assign response_accepted = (REORDER == 1) ? response_src_accepted : response_sink_accepted;
|
||||
|
||||
always @* begin
|
||||
next_pending_response_count = pending_response_count;
|
||||
|
||||
if (nonposted_cmd_accepted)
|
||||
next_pending_response_count = pending_response_count + 1'b1;
|
||||
if (response_accepted)
|
||||
next_pending_response_count = pending_response_count - 1'b1;
|
||||
if (nonposted_cmd_accepted && response_accepted)
|
||||
next_pending_response_count = pending_response_count;
|
||||
end
|
||||
|
||||
assign count_is_1 = (pending_response_count == 1);
|
||||
assign count_is_0 = (pending_response_count == 0);
|
||||
// ------------------------------------------------------------------
|
||||
// count_max_reached : count if maximum command reach to backpressure
|
||||
// ------------------------------------------------------------------
|
||||
reg count_max_reached;
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
pending_response_count <= 0;
|
||||
has_pending_responses <= 0;
|
||||
count_max_reached <= 0;
|
||||
end
|
||||
else begin
|
||||
pending_response_count <= next_pending_response_count;
|
||||
// synthesis translate_off
|
||||
if (count_is_0 && response_accepted)
|
||||
$display("%t: %m: Error: unexpected response: pending_response_count underflow", $time());
|
||||
// synthesis translate_on
|
||||
has_pending_responses <= has_pending_responses
|
||||
&& ~(count_is_1 && response_accepted && ~nonposted_cmd_accepted)
|
||||
|| (count_is_0 && nonposted_cmd_accepted && ~response_accepted);
|
||||
count_max_reached <= (next_pending_response_count == MAX_OUTSTANDING_RESPONSES);
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
wire suppress_prevent_harzard_for_particular_destid;
|
||||
wire this_destid_trans_changed;
|
||||
genvar j;
|
||||
generate
|
||||
if (REORDER) begin: fifo_dest_id_write_read_control_reorder_on
|
||||
wire [COUNTER_W - 1 : 0] current_trans_seq_of_this_destid;
|
||||
wire [MAX_DEST_ID - 1 : 0] current_trans_seq_of_this_destid_valid;
|
||||
wire [MAX_DEST_ID - 1 : 0] responses_arrived;
|
||||
reg [COUNTER_W - 1:0] trans_sequence;
|
||||
wire [MAX_DEST_ID - 1 : 0] trans_sequence_we;
|
||||
|
||||
wire [COUNTER_W : 0] trans_sequence_plus_trans_type;
|
||||
wire current_trans_type_of_this_destid;
|
||||
wire [COUNTER_W : 0] current_trans_seq_of_this_destid_plus_trans_type [MAX_DEST_ID];
|
||||
// ------------------------------------------------------------
|
||||
// Control write trans_sequence to fifos
|
||||
//
|
||||
// 1. when command accepted, read destid from command packet,
|
||||
// write this id to the fifo (each fifo for each desitid)
|
||||
// 2. when response acepted, read the destid from response packet,
|
||||
// will know which sequence of this response, write it to
|
||||
// correct segment in memory.
|
||||
// what if two commands go to same slave, the two sequences
|
||||
// go time same fifo, this even helps us to maintain order
|
||||
// when two commands same thread to one slave.
|
||||
// -----------------------------------------------------------
|
||||
wire [DEST_ID_W - 1 : 0] rsp_sink_dest_id;
|
||||
wire [DEST_ID_W - 1 : 0] cmd_dest_id;
|
||||
assign rsp_sink_dest_id = rsp_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
|
||||
|
||||
// write in fifo the trans_sequence and type of transaction
|
||||
assign trans_sequence_plus_trans_type = {stage2_data[PKT_TRANS_WRITE], trans_sequence};
|
||||
|
||||
// read the cmd_dest_id from output of pipeline stage so that either
|
||||
// or not, it wont affect how we write to fifo
|
||||
assign cmd_dest_id = stage2_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
|
||||
// -------------------------------------
|
||||
// Get the transaction_seq for that dest_id
|
||||
// -------------------------------------
|
||||
wire [COUNTER_W - 1: 0] trans_sequence_rsp;
|
||||
wire [COUNTER_W : 0] trans_sequence_rsp_plus_trans_type;
|
||||
wire [COUNTER_W - 1: 0] trans_sequence_rsp_this_destid_waiting;
|
||||
wire [COUNTER_W : 0] sequence_and_trans_type_this_destid_waiting;
|
||||
wire trans_sequence_rsp_this_destid_waiting_valid;
|
||||
assign trans_sequence_rsp_plus_trans_type = current_trans_seq_of_this_destid_plus_trans_type[rsp_sink_dest_id];
|
||||
assign trans_sequence_rsp = trans_sequence_rsp_plus_trans_type[COUNTER_W - 1: 0];
|
||||
|
||||
// do I need to check if this fifo is valid, it should be always valid, unless a command not yet sent
|
||||
// and response comes back which means something weird happens.
|
||||
// It is worth to do an assertion but now to avoid QIS warning, just do as normal ST handshaking
|
||||
// check valid and ready
|
||||
|
||||
for (j = 0; j < MAX_DEST_ID; j = j+1)
|
||||
begin : write_and_read_trans_sequence
|
||||
assign trans_sequence_we[j] = (cmd_dest_id == j) && nonposted_cmd_accepted;
|
||||
assign responses_arrived[j] = (rsp_sink_dest_id == j) && response_sink_accepted;
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------------
|
||||
// This is array of fifos, which will be created base on how many slaves
|
||||
// that this master can see (max dest_id_width)
|
||||
// Each fifo, will store the trans_sequence, which go to that slave
|
||||
// On the response path, based in the response from which slave
|
||||
// the fifo of that slave will be read, to check the sequences.
|
||||
// and this sequence is the write address to the memory
|
||||
// -----------------------------------------------------------------------------------
|
||||
// There are 3 sequences run around the limiter, they have a relationship
|
||||
// And this is how the key point of reorder work:
|
||||
//
|
||||
// trans_sequence : command sequence, each command go thru the limiter
|
||||
// will have a sequence to show their order. A simple
|
||||
// counter from 0 go up and repeat.
|
||||
// trans_sequence_rsp : response sequence, each response that go back to limiter,
|
||||
// will be read from trans_fifos to know their sequence.
|
||||
// expect_trans_sequence : Expected sequences for response that the master is waiting
|
||||
// The limiter will hold this sequence and wait until exactly response
|
||||
// for this sequence come back (trans_sequence_rsp)
|
||||
// aka: if trans_sequence_rsp back is same as expect_trans_sequence
|
||||
// then it is correct order, else response store in memory and
|
||||
// send out to master later, when expect_trans_sequence match.
|
||||
// ------------------------------------------------------------------------------------
|
||||
for (j = 0;j < MAX_DEST_ID; j = j+1) begin : trans_sequence_per_fifo
|
||||
altera_avalon_sc_fifo
|
||||
#(
|
||||
.SYMBOLS_PER_BEAT (1),
|
||||
.BITS_PER_SYMBOL (COUNTER_W + 1), // one bit extra to store type of transaction
|
||||
.FIFO_DEPTH (MAX_OUTSTANDING_RESPONSES),
|
||||
.CHANNEL_WIDTH (0),
|
||||
.ERROR_WIDTH (0),
|
||||
.USE_PACKETS (0),
|
||||
.USE_FILL_LEVEL (0),
|
||||
.EMPTY_LATENCY (1),
|
||||
.USE_MEMORY_BLOCKS (0),
|
||||
.USE_STORE_FORWARD (0),
|
||||
.USE_ALMOST_FULL_IF (0),
|
||||
.USE_ALMOST_EMPTY_IF (0)
|
||||
) dest_id_fifo
|
||||
(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_data (trans_sequence_plus_trans_type),
|
||||
.in_valid (trans_sequence_we[j]),
|
||||
.in_ready (),
|
||||
.out_data (current_trans_seq_of_this_destid_plus_trans_type[j]),
|
||||
.out_valid (current_trans_seq_of_this_destid_valid[j]),
|
||||
.out_ready (responses_arrived[j]),
|
||||
.csr_address (2'b00), // (terminated)
|
||||
.csr_read (1'b0), // (terminated)
|
||||
.csr_write (1'b0), // (terminated)
|
||||
.csr_readdata (), // (terminated)
|
||||
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
||||
.almost_full_data (), // (terminated)
|
||||
.almost_empty_data (), // (terminated)
|
||||
.in_startofpacket (1'b0), // (terminated)
|
||||
.in_endofpacket (1'b0), // (terminated)
|
||||
.out_startofpacket (), // (terminated)
|
||||
.out_endofpacket (), // (terminated)
|
||||
.in_empty (1'b0), // (terminated)
|
||||
.out_empty (), // (terminated)
|
||||
.in_error (1'b0), // (terminated)
|
||||
.out_error (), // (terminated)
|
||||
.in_channel (1'b0), // (terminated)
|
||||
.out_channel () // (terminated)
|
||||
);
|
||||
end // block: trans_sequence_per_fifo
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Calculate the transaction sequence, just simple increase
|
||||
// when each commands pass by
|
||||
// --------------------------------------------------------
|
||||
always @(posedge clk or posedge reset)
|
||||
begin
|
||||
if (reset) begin
|
||||
trans_sequence <= '0;
|
||||
end else begin
|
||||
if (nonposted_cmd_accepted)
|
||||
trans_sequence <= ( (trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : trans_sequence + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------
|
||||
// Control Memory for reorder responses
|
||||
// -------------------------------------
|
||||
wire [COUNTER_W - 1 : 0] next_rd_trans_sequence;
|
||||
reg [COUNTER_W - 1 : 0] rd_trans_sequence;
|
||||
reg [COUNTER_W - 1 : 0] next_expected_trans_sequence;
|
||||
reg [COUNTER_W - 1 : 0] expect_trans_sequence;
|
||||
wire [ST_DATA_W - 1 : 0] reorder_mem_data;
|
||||
wire [ST_CHANNEL_W - 1 : 0] reorder_mem_channel;
|
||||
wire reorder_mem_startofpacket;
|
||||
wire reorder_mem_endofpacket;
|
||||
wire reorder_mem_ready;
|
||||
// -------------------------------------------
|
||||
// Data to write and read from reorder memory
|
||||
// Store everything includes channel, sop, eop
|
||||
// -------------------------------------------
|
||||
reg [MEM_W - 1 : 0] mem_in_rsp_sink_data;
|
||||
reg [MEM_W - 1 : 0] reorder_mem_out_data;
|
||||
always_comb
|
||||
begin
|
||||
mem_in_rsp_sink_data = {rsp_sink_data, rsp_sink_channel, rsp_sink_startofpacket, rsp_sink_endofpacket};
|
||||
end
|
||||
|
||||
assign next_rd_trans_sequence = ((rd_trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : rd_trans_sequence + 1'b1;
|
||||
assign next_expected_trans_sequence = ((expect_trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : expect_trans_sequence + 1'b1;
|
||||
|
||||
always_ff @(posedge clk, posedge reset)
|
||||
begin
|
||||
if (reset) begin
|
||||
rd_trans_sequence <= '0;
|
||||
expect_trans_sequence <= '0;
|
||||
end else begin
|
||||
if (rsp_src_ready && reorder_mem_valid) begin
|
||||
if (reorder_mem_endofpacket == 1) begin //endofpacket
|
||||
expect_trans_sequence <= next_expected_trans_sequence;
|
||||
rd_trans_sequence <= next_rd_trans_sequence;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // always_ff @
|
||||
|
||||
// For PREVENT_HAZARD,
|
||||
// Case: Master Write to S0, read S1, and Read S0 back but if Write for S0
|
||||
// not yet return then we need to backpressure this, else read S0 might take over write
|
||||
// This is more checking after the fifo destid, as read S1 is inserted in midle
|
||||
// when see new packet, try to look at the fifo for that slave id, check if it
|
||||
// type of transaction
|
||||
assign sequence_and_trans_type_this_destid_waiting = current_trans_seq_of_this_destid_plus_trans_type[cmd_dest_id];
|
||||
assign current_trans_type_of_this_destid = sequence_and_trans_type_this_destid_waiting[COUNTER_W];
|
||||
assign trans_sequence_rsp_this_destid_waiting_valid = current_trans_seq_of_this_destid_valid[cmd_dest_id];
|
||||
// it might waiting other sequence, check if different type of transaction as only for PREVENT HAZARD
|
||||
// if comming comamnd to one slave and this slave is still waiting for response from previous command
|
||||
// which has diiferent type of transaction, we back-pressure this command to avoid HAZARD
|
||||
assign suppress_prevent_harzard_for_particular_destid = (current_trans_type_of_this_destid != is_write) & trans_sequence_rsp_this_destid_waiting_valid;
|
||||
|
||||
// -------------------------------------
|
||||
// Memory for reorder buffer
|
||||
// -------------------------------------
|
||||
altera_merlin_reorder_memory
|
||||
#(
|
||||
.DATA_W (MEM_W),
|
||||
.ADDR_H_W (COUNTER_W),
|
||||
.ADDR_L_W (MAX_BURST_LENGTH),
|
||||
.NUM_SEGMENT (MAX_OUTSTANDING_RESPONSES),
|
||||
.DEPTH (MEM_DEPTH)
|
||||
) reorder_memory
|
||||
(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_data (mem_in_rsp_sink_data),
|
||||
.in_valid (rsp_sink_valid),
|
||||
.in_ready (reorder_mem_ready),
|
||||
.out_data (reorder_mem_out_data),
|
||||
.out_valid (reorder_mem_valid),
|
||||
.out_ready (rsp_src_ready),
|
||||
.wr_segment (trans_sequence_rsp),
|
||||
.rd_segment (expect_trans_sequence)
|
||||
);
|
||||
// -------------------------------------
|
||||
// Output from reorder buffer
|
||||
// -------------------------------------
|
||||
assign reorder_mem_data = reorder_mem_out_data[MEM_W -1 : ST_CHANNEL_W + 2];
|
||||
assign reorder_mem_channel = reorder_mem_out_data[ST_CHANNEL_W + 2 - 1 : 2];
|
||||
assign reorder_mem_startofpacket = reorder_mem_out_data[1];
|
||||
assign reorder_mem_endofpacket = reorder_mem_out_data[0];
|
||||
|
||||
// -------------------------------------
|
||||
// Because use generate statment
|
||||
// so move all rsp_src_xxx controls here
|
||||
// -------------------------------------
|
||||
always_comb begin
|
||||
cmd_src_data = stage2_data;
|
||||
rsp_src_valid = reorder_mem_valid;
|
||||
rsp_src_data = reorder_mem_data;
|
||||
rsp_src_channel = reorder_mem_channel;
|
||||
rsp_src_startofpacket = reorder_mem_startofpacket;
|
||||
rsp_src_endofpacket = reorder_mem_endofpacket;
|
||||
// -------------------------------------
|
||||
// Forces commands to be non-posted if hazard prevention
|
||||
// is on, also drops write responses
|
||||
// -------------------------------------
|
||||
rsp_sink_ready = reorder_mem_ready; // now it takes ready signal from the memory not direct from master
|
||||
if (PREVENT_HAZARDS == 1) begin
|
||||
cmd_src_data[PKT_TRANS_POSTED] = 1'b0;
|
||||
|
||||
if (rsp_src_data[PKT_TRANS_WRITE] == 1'b1 && SUPPORTS_POSTED_WRITES == 1 && SUPPORTS_NONPOSTED_WRITES == 0) begin
|
||||
rsp_src_valid = 1'b0;
|
||||
rsp_sink_ready = 1'b1;
|
||||
end
|
||||
end
|
||||
end // always_comb
|
||||
|
||||
end // block: fifo_dest_id_write_read_control_reorder_on
|
||||
endgenerate
|
||||
|
||||
// -------------------------------------
|
||||
// Pass-through command and response
|
||||
// -------------------------------------
|
||||
|
||||
always_comb
|
||||
begin
|
||||
cmd_src_channel = stage2_channel;
|
||||
cmd_src_startofpacket = stage2_startofpacket;
|
||||
cmd_src_endofpacket = stage2_endofpacket;
|
||||
end // always_comb
|
||||
|
||||
// -------------------------------------
|
||||
// When there is no REORDER requirement
|
||||
// Just pass through signals
|
||||
// -------------------------------------
|
||||
generate
|
||||
if (!REORDER) begin : use_selector_or_pass_thru_rsp
|
||||
always_comb begin
|
||||
cmd_src_data = stage2_data;
|
||||
// pass thru almost signals
|
||||
rsp_src_valid = rsp_sink_valid;
|
||||
rsp_src_data = rsp_sink_data;
|
||||
rsp_src_channel = rsp_sink_channel;
|
||||
rsp_src_startofpacket = rsp_sink_startofpacket;
|
||||
rsp_src_endofpacket = rsp_sink_endofpacket;
|
||||
// -------------------------------------
|
||||
// Forces commands to be non-posted if hazard prevention
|
||||
// is on, also drops write responses
|
||||
// -------------------------------------
|
||||
rsp_sink_ready = rsp_src_ready; // take care this, should check memory empty
|
||||
if (PREVENT_HAZARDS == 1) begin
|
||||
cmd_src_data[PKT_TRANS_POSTED] = 1'b0;
|
||||
|
||||
if (rsp_sink_data[PKT_TRANS_WRITE] == 1'b1 && SUPPORTS_POSTED_WRITES == 1 && SUPPORTS_NONPOSTED_WRITES == 0) begin
|
||||
rsp_src_valid = 1'b0;
|
||||
rsp_sink_ready = 1'b1;
|
||||
end
|
||||
end
|
||||
end // always_comb
|
||||
end // if (!REORDER)
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Backpressure & Suppression
|
||||
// --------------------------------------------------------
|
||||
// ENFORCE_ORDER: unused option, always is 1, remove it
|
||||
// Now the limiter will suppress when max_outstanding reach
|
||||
// --------------------------------------------------------
|
||||
generate
|
||||
if (ENFORCE_ORDER) begin : enforce_order_block
|
||||
assign suppress_change_dest_id = (REORDER == 1) ? 1'b0 : nonposted_cmd && has_pending_responses &&
|
||||
(stage2_dest_changed || (PREVENT_HAZARDS == 1 && stage2_trans_changed));
|
||||
end else begin : no_order_block
|
||||
assign suppress_change_dest_id = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Even we allow change slave while still have pending responses
|
||||
// But one special case, when PREVENT_HAZARD=1, we still allow
|
||||
// switch slave while type of transaction change (RAW, WAR) but
|
||||
// only to different slaves.
|
||||
// if to same slave, we still need back pressure that to make
|
||||
// sure no racing
|
||||
// ------------------------------------------------------------
|
||||
|
||||
generate
|
||||
if (REORDER) begin : prevent_hazard_block
|
||||
assign suppress_change_trans_but_not_dest = nonposted_cmd && has_pending_responses &&
|
||||
!stage2_dest_changed && (PREVENT_HAZARDS == 1 && stage2_trans_changed);
|
||||
end else begin : no_hazard_block
|
||||
assign suppress_change_trans_but_not_dest = 1'b0; // no REORDER, the suppress_changes_destid take care of this.
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (REORDER) begin : prevent_hazard_block_for_particular_slave
|
||||
assign suppress_change_trans_for_one_slave = nonposted_cmd && has_pending_responses && (PREVENT_HAZARDS == 1 && suppress_prevent_harzard_for_particular_destid);
|
||||
end else begin : no_hazard_block_for_particular_slave
|
||||
assign suppress_change_trans_for_one_slave = 1'b0; // no REORDER, the suppress_changes_destid take care of this.
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// ------------------------------------------
|
||||
// Backpressure when max outstanding transactions are reached
|
||||
// ------------------------------------------
|
||||
generate
|
||||
if (REORDER) begin : max_outstanding_block
|
||||
assign suppress_max_outstanding = count_max_reached;
|
||||
end else begin
|
||||
assign suppress_max_outstanding = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign suppress = suppress_change_trans_for_one_slave | suppress_change_dest_id | suppress_max_outstanding;
|
||||
assign wide_valid = { VALID_WIDTH {stage2_valid} } & stage2_channel;
|
||||
|
||||
always @* begin
|
||||
stage2_ready = cmd_src_ready;
|
||||
internal_valid = stage2_valid;
|
||||
// --------------------------------------------------------
|
||||
// change suppress condidtion, in case REODER it will alllow changing slave
|
||||
// even still have pending transactions.
|
||||
// -------------------------------------------------------
|
||||
if (suppress) begin
|
||||
stage2_ready = 0;
|
||||
internal_valid = 0;
|
||||
end
|
||||
|
||||
if (VALID_WIDTH == 1) begin
|
||||
cmd_src_valid = {VALID_WIDTH{1'b0}};
|
||||
cmd_src_valid[0] = internal_valid;
|
||||
end else begin
|
||||
// -------------------------------------
|
||||
// Use the one-hot channel to determine if the destination
|
||||
// has changed. This results in a wide valid bus
|
||||
// -------------------------------------
|
||||
cmd_src_valid = wide_valid;
|
||||
if (nonposted_cmd & has_pending_responses) begin
|
||||
if (!REORDER) begin
|
||||
cmd_src_valid = wide_valid & last_channel;
|
||||
// -------------------------------------
|
||||
// Mask the valid signals if the transaction type has changed
|
||||
// if hazard prevention is enabled
|
||||
// -------------------------------------
|
||||
if (PREVENT_HAZARDS == 1)
|
||||
cmd_src_valid = wide_valid & last_channel & { VALID_WIDTH {!stage2_trans_changed} };
|
||||
end else begin // else: !if(!REORDER) if REORDER happen
|
||||
if (PREVENT_HAZARDS == 1)
|
||||
cmd_src_valid = wide_valid & { VALID_WIDTH {!suppress_change_trans_for_one_slave} };
|
||||
if (suppress_max_outstanding) begin
|
||||
cmd_src_valid = {VALID_WIDTH {1'b0}};
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------------------
|
||||
// Calculates the log2ceil of the input value.
|
||||
//
|
||||
// This function occurs a lot... please refactor.
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input integer val;
|
||||
integer i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -0,0 +1,30 @@
|
||||
# (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License Subscription
|
||||
# Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
# Intel or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
# +---------------------------------------------------
|
||||
# | Cut the async clear paths
|
||||
# +---------------------------------------------------
|
||||
set aclr_counter 0
|
||||
set clrn_counter 0
|
||||
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
set aclr_counter [get_collection_size $aclr_collection]
|
||||
set clrn_counter [get_collection_size $clrn_collection]
|
||||
|
||||
if {$aclr_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
}
|
||||
|
||||
if {$clrn_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
}
|
||||
@ -0,0 +1,319 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// --------------------------------------
|
||||
// Reset controller
|
||||
//
|
||||
// Combines all the input resets and synchronizes
|
||||
// the result to the clk.
|
||||
// ACDS13.1 - Added reset request as part of reset sequencing
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_controller
|
||||
#(
|
||||
parameter NUM_RESET_INPUTS = 6,
|
||||
parameter USE_RESET_REQUEST_IN0 = 0,
|
||||
parameter USE_RESET_REQUEST_IN1 = 0,
|
||||
parameter USE_RESET_REQUEST_IN2 = 0,
|
||||
parameter USE_RESET_REQUEST_IN3 = 0,
|
||||
parameter USE_RESET_REQUEST_IN4 = 0,
|
||||
parameter USE_RESET_REQUEST_IN5 = 0,
|
||||
parameter USE_RESET_REQUEST_IN6 = 0,
|
||||
parameter USE_RESET_REQUEST_IN7 = 0,
|
||||
parameter USE_RESET_REQUEST_IN8 = 0,
|
||||
parameter USE_RESET_REQUEST_IN9 = 0,
|
||||
parameter USE_RESET_REQUEST_IN10 = 0,
|
||||
parameter USE_RESET_REQUEST_IN11 = 0,
|
||||
parameter USE_RESET_REQUEST_IN12 = 0,
|
||||
parameter USE_RESET_REQUEST_IN13 = 0,
|
||||
parameter USE_RESET_REQUEST_IN14 = 0,
|
||||
parameter USE_RESET_REQUEST_IN15 = 0,
|
||||
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
|
||||
parameter SYNC_DEPTH = 2,
|
||||
parameter RESET_REQUEST_PRESENT = 0,
|
||||
parameter RESET_REQ_WAIT_TIME = 3,
|
||||
parameter MIN_RST_ASSERTION_TIME = 11,
|
||||
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
|
||||
parameter ADAPT_RESET_REQUEST = 0
|
||||
)
|
||||
(
|
||||
// --------------------------------------
|
||||
// We support up to 16 reset inputs, for now
|
||||
// --------------------------------------
|
||||
input reset_in0,
|
||||
input reset_in1,
|
||||
input reset_in2,
|
||||
input reset_in3,
|
||||
input reset_in4,
|
||||
input reset_in5,
|
||||
input reset_in6,
|
||||
input reset_in7,
|
||||
input reset_in8,
|
||||
input reset_in9,
|
||||
input reset_in10,
|
||||
input reset_in11,
|
||||
input reset_in12,
|
||||
input reset_in13,
|
||||
input reset_in14,
|
||||
input reset_in15,
|
||||
input reset_req_in0,
|
||||
input reset_req_in1,
|
||||
input reset_req_in2,
|
||||
input reset_req_in3,
|
||||
input reset_req_in4,
|
||||
input reset_req_in5,
|
||||
input reset_req_in6,
|
||||
input reset_req_in7,
|
||||
input reset_req_in8,
|
||||
input reset_req_in9,
|
||||
input reset_req_in10,
|
||||
input reset_req_in11,
|
||||
input reset_req_in12,
|
||||
input reset_req_in13,
|
||||
input reset_req_in14,
|
||||
input reset_req_in15,
|
||||
|
||||
|
||||
input clk,
|
||||
output reg reset_out,
|
||||
output reg reset_req
|
||||
);
|
||||
|
||||
// Always use async reset synchronizer if reset_req is used
|
||||
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
|
||||
|
||||
// --------------------------------------
|
||||
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
|
||||
// --------------------------------------
|
||||
localparam MIN_METASTABLE = 3;
|
||||
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
|
||||
|
||||
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
|
||||
|
||||
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
|
||||
MIN_RST_ASSERTION_TIME + 1 :
|
||||
(
|
||||
(MIN_RST_ASSERTION_TIME > LARGER)?
|
||||
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
|
||||
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
|
||||
);
|
||||
|
||||
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
|
||||
// --------------------------------------
|
||||
|
||||
wire merged_reset;
|
||||
wire merged_reset_req_in;
|
||||
wire reset_out_pre;
|
||||
wire reset_req_pre;
|
||||
|
||||
// Registers and Interconnect
|
||||
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
|
||||
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
|
||||
reg r_sync_rst;
|
||||
reg r_early_rst;
|
||||
|
||||
// --------------------------------------
|
||||
// "Or" all the input resets together
|
||||
// --------------------------------------
|
||||
assign merged_reset = (
|
||||
reset_in0 |
|
||||
reset_in1 |
|
||||
reset_in2 |
|
||||
reset_in3 |
|
||||
reset_in4 |
|
||||
reset_in5 |
|
||||
reset_in6 |
|
||||
reset_in7 |
|
||||
reset_in8 |
|
||||
reset_in9 |
|
||||
reset_in10 |
|
||||
reset_in11 |
|
||||
reset_in12 |
|
||||
reset_in13 |
|
||||
reset_in14 |
|
||||
reset_in15
|
||||
);
|
||||
|
||||
assign merged_reset_req_in = (
|
||||
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
|
||||
);
|
||||
|
||||
|
||||
// --------------------------------------
|
||||
// And if required, synchronize it to the required clock domain,
|
||||
// with the correct synchronization type
|
||||
// --------------------------------------
|
||||
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
|
||||
|
||||
assign reset_out_pre = merged_reset;
|
||||
assign reset_req_pre = merged_reset_req_in;
|
||||
|
||||
end else begin
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
|
||||
)
|
||||
alt_rst_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset),
|
||||
.reset_out (reset_out_pre)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_req_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset_req_in),
|
||||
.reset_out (reset_req_pre)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
|
||||
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
|
||||
always @* begin
|
||||
reset_out = reset_out_pre;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
|
||||
|
||||
wire reset_out_pre2;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH+1),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_sync_uq2
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (reset_out_pre),
|
||||
.reset_out (reset_out_pre2)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
reset_out = reset_out_pre2;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
// 3-FF Metastability Synchronizer
|
||||
initial
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
|
||||
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
|
||||
end
|
||||
|
||||
// Synchronous reset pipe
|
||||
initial
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
|
||||
end
|
||||
end
|
||||
|
||||
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
|
||||
// matches the early input.
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
reset_out = r_sync_rst;
|
||||
reset_req = r_early_rst;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,87 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,195 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
|
||||
// $Revision: #8 $
|
||||
// $Date: 2009/02/18 $
|
||||
// $Author: pscheidt $
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// File: altera_std_synchronizer_nocut.v
|
||||
//
|
||||
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
|
||||
// as altera_std_synchronizer.v, except that the embedded false
|
||||
// path constraint is removed in this module. If you use this
|
||||
// module, you will have to apply the appropriate timing
|
||||
// constraints.
|
||||
//
|
||||
// We expect to make this a standard Quartus atom eventually.
|
||||
//
|
||||
// Composed of two or more flip flops connected in series.
|
||||
// Random metastable condition is simulated when the
|
||||
// __ALTERA_STD__METASTABLE_SIM macro is defined.
|
||||
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
|
||||
// on the Verilog simulator compiler command line to
|
||||
// enable this mode. In addition, define the macro
|
||||
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
|
||||
// with every metastable event generated in the synchronizer.
|
||||
//
|
||||
// Copyright (C) Altera Corporation 2009, All Rights Reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_std_synchronizer_nocut (
|
||||
clk,
|
||||
reset_n,
|
||||
din,
|
||||
dout
|
||||
);
|
||||
|
||||
parameter depth = 3; // This value must be >= 2 !
|
||||
parameter rst_value = 0;
|
||||
|
||||
input clk;
|
||||
input reset_n;
|
||||
input din;
|
||||
output dout;
|
||||
|
||||
// QuartusII synthesis directives:
|
||||
// 1. Preserve all registers ie. do not touch them.
|
||||
// 2. Do not merge other flip-flops with synchronizer flip-flops.
|
||||
// QuartusII TimeQuest directives:
|
||||
// 1. Identify all flip-flops in this module as members of the synchronizer
|
||||
// to enable automatic metastability MTBF analysis.
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
|
||||
|
||||
//synthesis translate_off
|
||||
initial begin
|
||||
if (depth <2) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
|
||||
end
|
||||
end
|
||||
|
||||
// the first synchronizer register is either a simple D flop for synthesis
|
||||
// and non-metastable simulation or a D flop with a method to inject random
|
||||
// metastable events resulting in random delay of [0,1] cycles
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM
|
||||
|
||||
reg[31:0] RANDOM_SEED = 123456;
|
||||
wire next_din_s1;
|
||||
wire dout;
|
||||
reg din_last;
|
||||
reg random;
|
||||
event metastable_event; // hook for debug monitoring
|
||||
|
||||
initial begin
|
||||
$display("%m: Info: Metastable event injection simulation mode enabled");
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset_n == 0)
|
||||
random <= $random(RANDOM_SEED);
|
||||
else
|
||||
random <= $random;
|
||||
end
|
||||
|
||||
assign next_din_s1 = (din_last ^ din) ? random : din;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_last <= din;
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_s1 <= next_din_s1;
|
||||
end
|
||||
|
||||
`else
|
||||
|
||||
//synthesis translate_on
|
||||
generate if (rst_value == 0)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b0;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (rst_value == 1)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b1;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
//synthesis translate_off
|
||||
|
||||
`endif
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
|
||||
always @(*) begin
|
||||
if (reset_n && (din_last != din) && (random != din)) begin
|
||||
$display("%m: Verbose Info: metastable event @ time %t", $time);
|
||||
->metastable_event;
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
//synthesis translate_on
|
||||
|
||||
// the remaining synchronizer registers form a simple shift register
|
||||
// of length depth-1
|
||||
generate if (rst_value == 0)
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (rst_value == 1)
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign dout = dreg[depth-2];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,59 @@
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
//simulation files), and any associated documentation or information are
|
||||
//expressly subject to the terms and conditions of the Altera Program
|
||||
//License Subscription Agreement or other applicable license agreement,
|
||||
//including, without limitation, that your use is for the sole purpose
|
||||
//of programming logic devices manufactured by Altera and sold by Altera
|
||||
//or its authorized distributors. Please refer to the applicable
|
||||
//agreement for further details.
|
||||
|
||||
// synthesis translate_off
|
||||
`timescale 1ns / 1ps
|
||||
// synthesis translate_on
|
||||
|
||||
// turn off superfluous verilog processor warnings
|
||||
// altera message_level Level1
|
||||
// altera message_off 10034 10035 10036 10037 10230 10240 10030
|
||||
|
||||
module jtag_io_in0 (
|
||||
// inputs:
|
||||
address,
|
||||
clk,
|
||||
in_port,
|
||||
reset_n,
|
||||
|
||||
// outputs:
|
||||
readdata
|
||||
)
|
||||
;
|
||||
|
||||
output [ 31: 0] readdata;
|
||||
input [ 1: 0] address;
|
||||
input clk;
|
||||
input [ 31: 0] in_port;
|
||||
input reset_n;
|
||||
|
||||
|
||||
wire clk_en;
|
||||
wire [ 31: 0] data_in;
|
||||
wire [ 31: 0] read_mux_out;
|
||||
reg [ 31: 0] readdata;
|
||||
assign clk_en = 1;
|
||||
//s1, which is an e_avalon_slave
|
||||
assign read_mux_out = {32 {(address == 0)}} & data_in;
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
readdata <= 0;
|
||||
else if (clk_en)
|
||||
readdata <= {32'b0 | read_mux_out};
|
||||
end
|
||||
|
||||
|
||||
assign data_in = in_port;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,354 @@
|
||||
// jtag_io_master_0.v
|
||||
|
||||
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
|
||||
// will probably be lost.
|
||||
//
|
||||
// Generated using ACDS version 20.1 711
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module jtag_io_master_0 #(
|
||||
parameter USE_PLI = 0,
|
||||
parameter PLI_PORT = 50000,
|
||||
parameter FIFO_DEPTHS = 2
|
||||
) (
|
||||
input wire clk_clk, // clk.clk
|
||||
input wire clk_reset_reset, // clk_reset.reset
|
||||
output wire [31:0] master_address, // master.address
|
||||
input wire [31:0] master_readdata, // .readdata
|
||||
output wire master_read, // .read
|
||||
output wire master_write, // .write
|
||||
output wire [31:0] master_writedata, // .writedata
|
||||
input wire master_waitrequest, // .waitrequest
|
||||
input wire master_readdatavalid, // .readdatavalid
|
||||
output wire [3:0] master_byteenable, // .byteenable
|
||||
output wire master_reset_reset // master_reset.reset
|
||||
);
|
||||
|
||||
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
|
||||
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
|
||||
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
|
||||
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
|
||||
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
|
||||
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
|
||||
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
|
||||
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
|
||||
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
|
||||
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
|
||||
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
|
||||
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
|
||||
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
|
||||
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
|
||||
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
|
||||
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
|
||||
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
|
||||
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
|
||||
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
|
||||
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
|
||||
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
|
||||
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
|
||||
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
|
||||
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
|
||||
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
|
||||
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
|
||||
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
|
||||
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
|
||||
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
|
||||
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
|
||||
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
|
||||
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
|
||||
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
|
||||
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
|
||||
|
||||
generate
|
||||
// If any of the display statements (or deliberately broken
|
||||
// instantiations) within this generate block triggers then this module
|
||||
// has been instantiated this module with a set of parameters different
|
||||
// from those it was generated for. This will usually result in a
|
||||
// non-functioning system.
|
||||
if (USE_PLI != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
use_pli_check ( .error(1'b1) );
|
||||
end
|
||||
if (PLI_PORT != 50000)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
pli_port_check ( .error(1'b1) );
|
||||
end
|
||||
if (FIFO_DEPTHS != 2)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
fifo_depths_check ( .error(1'b1) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
altera_avalon_st_jtag_interface #(
|
||||
.PURPOSE (1),
|
||||
.UPSTREAM_FIFO_SIZE (0),
|
||||
.DOWNSTREAM_FIFO_SIZE (64),
|
||||
.MGMT_CHANNEL_WIDTH (-1),
|
||||
.EXPORT_JTAG (0),
|
||||
.USE_PLI (0),
|
||||
.PLI_PORT (50000)
|
||||
) jtag_phy_embedded_in_jtag_master (
|
||||
.clk (clk_clk), // clock.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
|
||||
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
|
||||
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
|
||||
.sink_data (p2b_out_bytes_stream_data), // sink.data
|
||||
.sink_valid (p2b_out_bytes_stream_valid), // .valid
|
||||
.sink_ready (p2b_out_bytes_stream_ready), // .ready
|
||||
.resetrequest (master_reset_reset), // resetrequest.reset
|
||||
.source_ready (1'b1), // (terminated)
|
||||
.mgmt_valid (), // (terminated)
|
||||
.mgmt_channel (), // (terminated)
|
||||
.mgmt_data (), // (terminated)
|
||||
.jtag_tck (1'b0), // (terminated)
|
||||
.jtag_tms (1'b0), // (terminated)
|
||||
.jtag_tdi (1'b0), // (terminated)
|
||||
.jtag_tdo (), // (terminated)
|
||||
.jtag_ena (1'b0), // (terminated)
|
||||
.jtag_usr1 (1'b0), // (terminated)
|
||||
.jtag_clr (1'b0), // (terminated)
|
||||
.jtag_clrn (1'b0), // (terminated)
|
||||
.jtag_state_tlr (1'b0), // (terminated)
|
||||
.jtag_state_rti (1'b0), // (terminated)
|
||||
.jtag_state_sdrs (1'b0), // (terminated)
|
||||
.jtag_state_cdr (1'b0), // (terminated)
|
||||
.jtag_state_sdr (1'b0), // (terminated)
|
||||
.jtag_state_e1dr (1'b0), // (terminated)
|
||||
.jtag_state_pdr (1'b0), // (terminated)
|
||||
.jtag_state_e2dr (1'b0), // (terminated)
|
||||
.jtag_state_udr (1'b0), // (terminated)
|
||||
.jtag_state_sirs (1'b0), // (terminated)
|
||||
.jtag_state_cir (1'b0), // (terminated)
|
||||
.jtag_state_sir (1'b0), // (terminated)
|
||||
.jtag_state_e1ir (1'b0), // (terminated)
|
||||
.jtag_state_pir (1'b0), // (terminated)
|
||||
.jtag_state_e2ir (1'b0), // (terminated)
|
||||
.jtag_state_uir (1'b0), // (terminated)
|
||||
.jtag_ir_in (3'b000), // (terminated)
|
||||
.jtag_irq (), // (terminated)
|
||||
.jtag_ir_out () // (terminated)
|
||||
);
|
||||
|
||||
jtag_io_master_0_timing_adt timing_adt (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data
|
||||
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
|
||||
.out_data (timing_adt_out_data), // out.data
|
||||
.out_valid (timing_adt_out_valid), // .valid
|
||||
.out_ready (timing_adt_out_ready) // .ready
|
||||
);
|
||||
|
||||
altera_avalon_sc_fifo #(
|
||||
.SYMBOLS_PER_BEAT (1),
|
||||
.BITS_PER_SYMBOL (8),
|
||||
.FIFO_DEPTH (64),
|
||||
.CHANNEL_WIDTH (0),
|
||||
.ERROR_WIDTH (0),
|
||||
.USE_PACKETS (0),
|
||||
.USE_FILL_LEVEL (0),
|
||||
.EMPTY_LATENCY (3),
|
||||
.USE_MEMORY_BLOCKS (1),
|
||||
.USE_STORE_FORWARD (0),
|
||||
.USE_ALMOST_FULL_IF (0),
|
||||
.USE_ALMOST_EMPTY_IF (0)
|
||||
) fifo (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset (rst_controller_reset_out_reset), // clk_reset.reset
|
||||
.in_data (timing_adt_out_data), // in.data
|
||||
.in_valid (timing_adt_out_valid), // .valid
|
||||
.in_ready (timing_adt_out_ready), // .ready
|
||||
.out_data (fifo_out_data), // out.data
|
||||
.out_valid (fifo_out_valid), // .valid
|
||||
.out_ready (fifo_out_ready), // .ready
|
||||
.csr_address (2'b00), // (terminated)
|
||||
.csr_read (1'b0), // (terminated)
|
||||
.csr_write (1'b0), // (terminated)
|
||||
.csr_readdata (), // (terminated)
|
||||
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
|
||||
.almost_full_data (), // (terminated)
|
||||
.almost_empty_data (), // (terminated)
|
||||
.in_startofpacket (1'b0), // (terminated)
|
||||
.in_endofpacket (1'b0), // (terminated)
|
||||
.out_startofpacket (), // (terminated)
|
||||
.out_endofpacket (), // (terminated)
|
||||
.in_empty (1'b0), // (terminated)
|
||||
.out_empty (), // (terminated)
|
||||
.in_error (1'b0), // (terminated)
|
||||
.out_error (), // (terminated)
|
||||
.in_channel (1'b0), // (terminated)
|
||||
.out_channel () // (terminated)
|
||||
);
|
||||
|
||||
altera_avalon_st_bytes_to_packets #(
|
||||
.CHANNEL_WIDTH (8),
|
||||
.ENCODING (0)
|
||||
) b2p (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
|
||||
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
|
||||
.out_ready (b2p_out_packets_stream_ready), // .ready
|
||||
.out_valid (b2p_out_packets_stream_valid), // .valid
|
||||
.out_data (b2p_out_packets_stream_data), // .data
|
||||
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
|
||||
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
|
||||
.in_ready (fifo_out_ready), // in_bytes_stream.ready
|
||||
.in_valid (fifo_out_valid), // .valid
|
||||
.in_data (fifo_out_data) // .data
|
||||
);
|
||||
|
||||
altera_avalon_st_packets_to_bytes #(
|
||||
.CHANNEL_WIDTH (8),
|
||||
.ENCODING (0)
|
||||
) p2b (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
|
||||
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
|
||||
.in_valid (p2b_adapter_out_valid), // .valid
|
||||
.in_data (p2b_adapter_out_data), // .data
|
||||
.in_channel (p2b_adapter_out_channel), // .channel
|
||||
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
|
||||
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
|
||||
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
|
||||
.out_valid (p2b_out_bytes_stream_valid), // .valid
|
||||
.out_data (p2b_out_bytes_stream_data) // .data
|
||||
);
|
||||
|
||||
altera_avalon_packets_to_master #(
|
||||
.FAST_VER (0),
|
||||
.FIFO_DEPTHS (2),
|
||||
.FIFO_WIDTHU (1)
|
||||
) transacto (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
|
||||
.out_ready (transacto_out_stream_ready), // out_stream.ready
|
||||
.out_valid (transacto_out_stream_valid), // .valid
|
||||
.out_data (transacto_out_stream_data), // .data
|
||||
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
|
||||
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
|
||||
.in_ready (b2p_adapter_out_ready), // in_stream.ready
|
||||
.in_valid (b2p_adapter_out_valid), // .valid
|
||||
.in_data (b2p_adapter_out_data), // .data
|
||||
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
|
||||
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
|
||||
.address (master_address), // avalon_master.address
|
||||
.readdata (master_readdata), // .readdata
|
||||
.read (master_read), // .read
|
||||
.write (master_write), // .write
|
||||
.writedata (master_writedata), // .writedata
|
||||
.waitrequest (master_waitrequest), // .waitrequest
|
||||
.readdatavalid (master_readdatavalid), // .readdatavalid
|
||||
.byteenable (master_byteenable) // .byteenable
|
||||
);
|
||||
|
||||
jtag_io_master_0_b2p_adapter b2p_adapter (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
.in_data (b2p_out_packets_stream_data), // in.data
|
||||
.in_valid (b2p_out_packets_stream_valid), // .valid
|
||||
.in_ready (b2p_out_packets_stream_ready), // .ready
|
||||
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
|
||||
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
|
||||
.in_channel (b2p_out_packets_stream_channel), // .channel
|
||||
.out_data (b2p_adapter_out_data), // out.data
|
||||
.out_valid (b2p_adapter_out_valid), // .valid
|
||||
.out_ready (b2p_adapter_out_ready), // .ready
|
||||
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
|
||||
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
|
||||
);
|
||||
|
||||
jtag_io_master_0_p2b_adapter p2b_adapter (
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
|
||||
.in_data (transacto_out_stream_data), // in.data
|
||||
.in_valid (transacto_out_stream_valid), // .valid
|
||||
.in_ready (transacto_out_stream_ready), // .ready
|
||||
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
|
||||
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
|
||||
.out_data (p2b_adapter_out_data), // out.data
|
||||
.out_valid (p2b_adapter_out_valid), // .valid
|
||||
.out_ready (p2b_adapter_out_ready), // .ready
|
||||
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
|
||||
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
|
||||
.out_channel (p2b_adapter_out_channel) // .channel
|
||||
);
|
||||
|
||||
altera_reset_controller #(
|
||||
.NUM_RESET_INPUTS (1),
|
||||
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
||||
.SYNC_DEPTH (2),
|
||||
.RESET_REQUEST_PRESENT (0),
|
||||
.RESET_REQ_WAIT_TIME (1),
|
||||
.MIN_RST_ASSERTION_TIME (3),
|
||||
.RESET_REQ_EARLY_DSRT_TIME (1),
|
||||
.USE_RESET_REQUEST_IN0 (0),
|
||||
.USE_RESET_REQUEST_IN1 (0),
|
||||
.USE_RESET_REQUEST_IN2 (0),
|
||||
.USE_RESET_REQUEST_IN3 (0),
|
||||
.USE_RESET_REQUEST_IN4 (0),
|
||||
.USE_RESET_REQUEST_IN5 (0),
|
||||
.USE_RESET_REQUEST_IN6 (0),
|
||||
.USE_RESET_REQUEST_IN7 (0),
|
||||
.USE_RESET_REQUEST_IN8 (0),
|
||||
.USE_RESET_REQUEST_IN9 (0),
|
||||
.USE_RESET_REQUEST_IN10 (0),
|
||||
.USE_RESET_REQUEST_IN11 (0),
|
||||
.USE_RESET_REQUEST_IN12 (0),
|
||||
.USE_RESET_REQUEST_IN13 (0),
|
||||
.USE_RESET_REQUEST_IN14 (0),
|
||||
.USE_RESET_REQUEST_IN15 (0),
|
||||
.ADAPT_RESET_REQUEST (0)
|
||||
) rst_controller (
|
||||
.reset_in0 (clk_reset_reset), // reset_in0.reset
|
||||
.clk (clk_clk), // clk.clk
|
||||
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
|
||||
.reset_req (), // (terminated)
|
||||
.reset_req_in0 (1'b0), // (terminated)
|
||||
.reset_in1 (1'b0), // (terminated)
|
||||
.reset_req_in1 (1'b0), // (terminated)
|
||||
.reset_in2 (1'b0), // (terminated)
|
||||
.reset_req_in2 (1'b0), // (terminated)
|
||||
.reset_in3 (1'b0), // (terminated)
|
||||
.reset_req_in3 (1'b0), // (terminated)
|
||||
.reset_in4 (1'b0), // (terminated)
|
||||
.reset_req_in4 (1'b0), // (terminated)
|
||||
.reset_in5 (1'b0), // (terminated)
|
||||
.reset_req_in5 (1'b0), // (terminated)
|
||||
.reset_in6 (1'b0), // (terminated)
|
||||
.reset_req_in6 (1'b0), // (terminated)
|
||||
.reset_in7 (1'b0), // (terminated)
|
||||
.reset_req_in7 (1'b0), // (terminated)
|
||||
.reset_in8 (1'b0), // (terminated)
|
||||
.reset_req_in8 (1'b0), // (terminated)
|
||||
.reset_in9 (1'b0), // (terminated)
|
||||
.reset_req_in9 (1'b0), // (terminated)
|
||||
.reset_in10 (1'b0), // (terminated)
|
||||
.reset_req_in10 (1'b0), // (terminated)
|
||||
.reset_in11 (1'b0), // (terminated)
|
||||
.reset_req_in11 (1'b0), // (terminated)
|
||||
.reset_in12 (1'b0), // (terminated)
|
||||
.reset_req_in12 (1'b0), // (terminated)
|
||||
.reset_in13 (1'b0), // (terminated)
|
||||
.reset_req_in13 (1'b0), // (terminated)
|
||||
.reset_in14 (1'b0), // (terminated)
|
||||
.reset_req_in14 (1'b0), // (terminated)
|
||||
.reset_in15 (1'b0), // (terminated)
|
||||
.reset_req_in15 (1'b0) // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,100 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Channel Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: jtag_io_master_0_b2p_adapter
|
||||
// in_channel_width: 8
|
||||
// in_max_channel: 255
|
||||
// out_channel_width: 0
|
||||
// out_max_channel: 0
|
||||
// data_width: 8
|
||||
// error_width: 0
|
||||
// use_ready: true
|
||||
// use_packets: true
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
|
||||
module jtag_io_master_0_b2p_adapter
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
input [8-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
|
||||
);
|
||||
|
||||
reg out_channel;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
out_startofpacket = in_startofpacket;
|
||||
out_endofpacket = in_endofpacket;
|
||||
|
||||
out_channel = in_channel; //TODO delete this to avoid Quartus warnings
|
||||
|
||||
// Suppress channels that are higher than the destination's max_channel.
|
||||
if (in_channel > 0) begin
|
||||
out_valid = 0;
|
||||
// Simulation Message goes here.
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,96 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Channel Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: jtag_io_master_0_p2b_adapter
|
||||
// in_channel_width: 0
|
||||
// in_max_channel: 0
|
||||
// out_channel_width: 8
|
||||
// out_max_channel: 255
|
||||
// data_width: 8
|
||||
// error_width: 0
|
||||
// use_ready: true
|
||||
// use_packets: true
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
|
||||
module jtag_io_master_0_p2b_adapter
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
output reg [8-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
|
||||
);
|
||||
|
||||
reg in_channel = 0;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
out_startofpacket = in_startofpacket;
|
||||
out_endofpacket = in_endofpacket;
|
||||
|
||||
out_channel = 0;
|
||||
out_channel = in_channel;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,112 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_timing_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/27 $
|
||||
// $Author: dmunday, korthner $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Timing Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: jtag_io_master_0_timing_adt
|
||||
// in_use_ready: false
|
||||
// out_use_ready: true
|
||||
// in_use_valid: true
|
||||
// out_use_valid: true
|
||||
// use_packets: false
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
// data_width: 8
|
||||
// channel_width: 0
|
||||
// error_width: 0
|
||||
// in_ready_latency: 0
|
||||
// out_ready_latency: 0
|
||||
// in_payload_width: 8
|
||||
// out_payload_width: 8
|
||||
// in_payload_map: in_data
|
||||
// out_payload_map: out_data
|
||||
// ------------------------------------------
|
||||
|
||||
|
||||
|
||||
module jtag_io_master_0_timing_adt
|
||||
(
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
/*AUTOARG*/);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg [8-1:0] in_payload;
|
||||
reg [8-1:0] out_payload;
|
||||
reg [1-1:0] ready;
|
||||
reg in_ready;
|
||||
// synthesis translate_off
|
||||
always @(negedge in_ready) begin
|
||||
$display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
|
||||
end
|
||||
// synthesis translate_on
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_payload = {in_data};
|
||||
{out_data} = out_payload;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Ready & valid signals.
|
||||
// ---------------------------------------------------------------------
|
||||
always_comb begin
|
||||
ready[0] = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_payload = in_payload;
|
||||
in_ready = ready[0];
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,202 @@
|
||||
// jtag_io_mm_interconnect_0_avalon_st_adapter.v
|
||||
|
||||
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
|
||||
// will probably be lost.
|
||||
//
|
||||
// Generated using ACDS version 20.1 711
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module jtag_io_mm_interconnect_0_avalon_st_adapter #(
|
||||
parameter inBitsPerSymbol = 34,
|
||||
parameter inUsePackets = 0,
|
||||
parameter inDataWidth = 34,
|
||||
parameter inChannelWidth = 0,
|
||||
parameter inErrorWidth = 0,
|
||||
parameter inUseEmptyPort = 0,
|
||||
parameter inUseValid = 1,
|
||||
parameter inUseReady = 1,
|
||||
parameter inReadyLatency = 0,
|
||||
parameter outDataWidth = 34,
|
||||
parameter outChannelWidth = 0,
|
||||
parameter outErrorWidth = 1,
|
||||
parameter outUseEmptyPort = 0,
|
||||
parameter outUseValid = 1,
|
||||
parameter outUseReady = 1,
|
||||
parameter outReadyLatency = 0
|
||||
) (
|
||||
input wire in_clk_0_clk, // in_clk_0.clk
|
||||
input wire in_rst_0_reset, // in_rst_0.reset
|
||||
input wire [33:0] in_0_data, // in_0.data
|
||||
input wire in_0_valid, // .valid
|
||||
output wire in_0_ready, // .ready
|
||||
output wire [33:0] out_0_data, // out_0.data
|
||||
output wire out_0_valid, // .valid
|
||||
input wire out_0_ready, // .ready
|
||||
output wire [0:0] out_0_error // .error
|
||||
);
|
||||
|
||||
generate
|
||||
// If any of the display statements (or deliberately broken
|
||||
// instantiations) within this generate block triggers then this module
|
||||
// has been instantiated this module with a set of parameters different
|
||||
// from those it was generated for. This will usually result in a
|
||||
// non-functioning system.
|
||||
if (inBitsPerSymbol != 34)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
inbitspersymbol_check ( .error(1'b1) );
|
||||
end
|
||||
if (inUsePackets != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
inusepackets_check ( .error(1'b1) );
|
||||
end
|
||||
if (inDataWidth != 34)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
indatawidth_check ( .error(1'b1) );
|
||||
end
|
||||
if (inChannelWidth != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
inchannelwidth_check ( .error(1'b1) );
|
||||
end
|
||||
if (inErrorWidth != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
inerrorwidth_check ( .error(1'b1) );
|
||||
end
|
||||
if (inUseEmptyPort != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
inuseemptyport_check ( .error(1'b1) );
|
||||
end
|
||||
if (inUseValid != 1)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
inusevalid_check ( .error(1'b1) );
|
||||
end
|
||||
if (inUseReady != 1)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
inuseready_check ( .error(1'b1) );
|
||||
end
|
||||
if (inReadyLatency != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
inreadylatency_check ( .error(1'b1) );
|
||||
end
|
||||
if (outDataWidth != 34)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
outdatawidth_check ( .error(1'b1) );
|
||||
end
|
||||
if (outChannelWidth != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
outchannelwidth_check ( .error(1'b1) );
|
||||
end
|
||||
if (outErrorWidth != 1)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
outerrorwidth_check ( .error(1'b1) );
|
||||
end
|
||||
if (outUseEmptyPort != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
outuseemptyport_check ( .error(1'b1) );
|
||||
end
|
||||
if (outUseValid != 1)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
outusevalid_check ( .error(1'b1) );
|
||||
end
|
||||
if (outUseReady != 1)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
outuseready_check ( .error(1'b1) );
|
||||
end
|
||||
if (outReadyLatency != 0)
|
||||
begin
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
outreadylatency_check ( .error(1'b1) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
|
||||
.clk (in_clk_0_clk), // clk.clk
|
||||
.reset_n (~in_rst_0_reset), // reset.reset_n
|
||||
.in_data (in_0_data), // in.data
|
||||
.in_valid (in_0_valid), // .valid
|
||||
.in_ready (in_0_ready), // .ready
|
||||
.out_data (out_0_data), // out.data
|
||||
.out_valid (out_0_valid), // .valid
|
||||
.out_ready (out_0_ready), // .ready
|
||||
.out_error (out_0_error) // .error
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,107 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Error Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
// use_ready: true
|
||||
// use_packets: false
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
// data_width: 34
|
||||
// channel_width: 0
|
||||
// in_error_width: 0
|
||||
// out_error_width: 1
|
||||
// in_errors_list
|
||||
// in_errors_indices 0
|
||||
// out_errors_list
|
||||
// has_in_error_desc: FALSE
|
||||
// has_out_error_desc: FALSE
|
||||
// out_has_other: FALSE
|
||||
// out_other_index: -1
|
||||
// dumpVar:
|
||||
// inString: in_error[
|
||||
// closeString: ] |
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
module jtag_io_mm_interconnect_0_avalon_st_adapter_error_adapter_0
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [34-1: 0] in_data,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [34-1: 0] out_data,
|
||||
output reg [0:0] out_error,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
/*AUTOARG*/);
|
||||
|
||||
reg in_error = 0;
|
||||
initial in_error = 0;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Pass-through Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always_comb begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Error Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always_comb begin
|
||||
out_error = 0;
|
||||
|
||||
out_error = in_error;
|
||||
|
||||
end //always @*
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,145 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------
|
||||
// Merlin Demultiplexer
|
||||
//
|
||||
// Asserts valid on the appropriate output
|
||||
// given a one-hot channel signal.
|
||||
// -------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: jtag_io_mm_interconnect_0_cmd_demux
|
||||
// ST_DATA_W: 104
|
||||
// ST_CHANNEL_W: 4
|
||||
// NUM_OUTPUTS: 4
|
||||
// VALID_WIDTH: 4
|
||||
// ------------------------------------------
|
||||
|
||||
//------------------------------------------
|
||||
// Message Supression Used
|
||||
// QIS Warnings
|
||||
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
|
||||
//------------------------------------------
|
||||
|
||||
module jtag_io_mm_interconnect_0_cmd_demux
|
||||
(
|
||||
// -------------------
|
||||
// Sink
|
||||
// -------------------
|
||||
input [4-1 : 0] sink_valid,
|
||||
input [104-1 : 0] sink_data, // ST_DATA_W=104
|
||||
input [4-1 : 0] sink_channel, // ST_CHANNEL_W=4
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Sources
|
||||
// -------------------
|
||||
output reg src0_valid,
|
||||
output reg [104-1 : 0] src0_data, // ST_DATA_W=104
|
||||
output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4
|
||||
output reg src0_startofpacket,
|
||||
output reg src0_endofpacket,
|
||||
input src0_ready,
|
||||
|
||||
output reg src1_valid,
|
||||
output reg [104-1 : 0] src1_data, // ST_DATA_W=104
|
||||
output reg [4-1 : 0] src1_channel, // ST_CHANNEL_W=4
|
||||
output reg src1_startofpacket,
|
||||
output reg src1_endofpacket,
|
||||
input src1_ready,
|
||||
|
||||
output reg src2_valid,
|
||||
output reg [104-1 : 0] src2_data, // ST_DATA_W=104
|
||||
output reg [4-1 : 0] src2_channel, // ST_CHANNEL_W=4
|
||||
output reg src2_startofpacket,
|
||||
output reg src2_endofpacket,
|
||||
input src2_ready,
|
||||
|
||||
output reg src3_valid,
|
||||
output reg [104-1 : 0] src3_data, // ST_DATA_W=104
|
||||
output reg [4-1 : 0] src3_channel, // ST_CHANNEL_W=4
|
||||
output reg src3_startofpacket,
|
||||
output reg src3_endofpacket,
|
||||
input src3_ready,
|
||||
|
||||
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
|
||||
input clk,
|
||||
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
|
||||
input reset
|
||||
|
||||
);
|
||||
|
||||
localparam NUM_OUTPUTS = 4;
|
||||
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
|
||||
|
||||
// -------------------
|
||||
// Demux
|
||||
// -------------------
|
||||
always @* begin
|
||||
src0_data = sink_data;
|
||||
src0_startofpacket = sink_startofpacket;
|
||||
src0_endofpacket = sink_endofpacket;
|
||||
src0_channel = sink_channel >> NUM_OUTPUTS;
|
||||
|
||||
src0_valid = sink_channel[0] && sink_valid[0];
|
||||
|
||||
src1_data = sink_data;
|
||||
src1_startofpacket = sink_startofpacket;
|
||||
src1_endofpacket = sink_endofpacket;
|
||||
src1_channel = sink_channel >> NUM_OUTPUTS;
|
||||
|
||||
src1_valid = sink_channel[1] && sink_valid[1];
|
||||
|
||||
src2_data = sink_data;
|
||||
src2_startofpacket = sink_startofpacket;
|
||||
src2_endofpacket = sink_endofpacket;
|
||||
src2_channel = sink_channel >> NUM_OUTPUTS;
|
||||
|
||||
src2_valid = sink_channel[2] && sink_valid[2];
|
||||
|
||||
src3_data = sink_data;
|
||||
src3_startofpacket = sink_startofpacket;
|
||||
src3_endofpacket = sink_endofpacket;
|
||||
src3_channel = sink_channel >> NUM_OUTPUTS;
|
||||
|
||||
src3_valid = sink_channel[3] && sink_valid[3];
|
||||
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Backpressure
|
||||
// -------------------
|
||||
assign ready_vector[0] = src0_ready;
|
||||
assign ready_vector[1] = src1_ready;
|
||||
assign ready_vector[2] = src2_ready;
|
||||
assign ready_vector[3] = src3_ready;
|
||||
|
||||
assign sink_ready = |(sink_channel & ready_vector);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,96 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2014 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// ------------------------------------------
|
||||
// Merlin Multiplexer
|
||||
// ------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: jtag_io_mm_interconnect_0_cmd_mux
|
||||
// NUM_INPUTS: 1
|
||||
// ARBITRATION_SHARES: 1
|
||||
// ARBITRATION_SCHEME "round-robin"
|
||||
// PIPELINE_ARB: 1
|
||||
// PKT_TRANS_LOCK: 72 (arbitration locking enabled)
|
||||
// ST_DATA_W: 104
|
||||
// ST_CHANNEL_W: 4
|
||||
// ------------------------------------------
|
||||
|
||||
module jtag_io_mm_interconnect_0_cmd_mux
|
||||
(
|
||||
// ----------------------
|
||||
// Sinks
|
||||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [104-1 : 0] sink0_data,
|
||||
input [4-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
||||
|
||||
// ----------------------
|
||||
// Source
|
||||
// ----------------------
|
||||
output src_valid,
|
||||
output [104-1 : 0] src_data,
|
||||
output [4-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
||||
// ----------------------
|
||||
// Clock & Reset
|
||||
// ----------------------
|
||||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 104 + 4 + 2;
|
||||
localparam NUM_INPUTS = 1;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 1;
|
||||
localparam ST_DATA_W = 104;
|
||||
localparam ST_CHANNEL_W = 4;
|
||||
localparam PKT_TRANS_LOCK = 72;
|
||||
|
||||
assign src_valid = sink0_valid;
|
||||
assign src_data = sink0_data;
|
||||
assign src_channel = sink0_channel;
|
||||
assign src_startofpacket = sink0_startofpacket;
|
||||
assign src_endofpacket = sink0_endofpacket;
|
||||
assign sink0_ready = src_ready;
|
||||
endmodule
|
||||
|
||||
|
||||
@ -0,0 +1,246 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Merlin Router
|
||||
//
|
||||
// Asserts the appropriate one-hot encoded channel based on
|
||||
// either (a) the address or (b) the dest id. The DECODER_TYPE
|
||||
// parameter controls this behaviour. 0 means address decoder,
|
||||
// 1 means dest id decoder.
|
||||
//
|
||||
// In the case of (a), it also sets the destination id.
|
||||
// -------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module jtag_io_mm_interconnect_0_router_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = 0,
|
||||
DEFAULT_WR_CHANNEL = -1,
|
||||
DEFAULT_RD_CHANNEL = -1,
|
||||
DEFAULT_DESTID = 2
|
||||
)
|
||||
(output [90 - 89 : 0] default_destination_id,
|
||||
output [4-1 : 0] default_wr_channel,
|
||||
output [4-1 : 0] default_rd_channel,
|
||||
output [4-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
DEFAULT_DESTID[90 - 89 : 0];
|
||||
|
||||
generate
|
||||
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
|
||||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 4'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
|
||||
assign default_wr_channel = '0;
|
||||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module jtag_io_mm_interconnect_0_router
|
||||
(
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Command Sink (Input)
|
||||
// -------------------
|
||||
input sink_valid,
|
||||
input [104-1 : 0] sink_data,
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Command Source (Output)
|
||||
// -------------------
|
||||
output src_valid,
|
||||
output reg [104-1 : 0] src_data,
|
||||
output reg [4-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
);
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Local parameters and variables
|
||||
// -------------------------------------------------------
|
||||
localparam PKT_ADDR_H = 67;
|
||||
localparam PKT_ADDR_L = 36;
|
||||
localparam PKT_DEST_ID_H = 90;
|
||||
localparam PKT_DEST_ID_L = 89;
|
||||
localparam PKT_PROTECTION_H = 94;
|
||||
localparam PKT_PROTECTION_L = 92;
|
||||
localparam ST_DATA_W = 104;
|
||||
localparam ST_CHANNEL_W = 4;
|
||||
localparam DECODER_TYPE = 0;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 70;
|
||||
localparam PKT_TRANS_READ = 71;
|
||||
|
||||
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
|
||||
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Figure out the number of bits to mask off for each slave span
|
||||
// during address decoding
|
||||
// -------------------------------------------------------
|
||||
localparam PAD0 = log2ceil(64'h10 - 64'h0);
|
||||
localparam PAD1 = log2ceil(64'h20 - 64'h10);
|
||||
localparam PAD2 = log2ceil(64'h30 - 64'h20);
|
||||
localparam PAD3 = log2ceil(64'h40 - 64'h30);
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h40;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
PKT_ADDR_H :
|
||||
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
|
||||
|
||||
localparam RG = RANGE_ADDR_WIDTH-1;
|
||||
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
|
||||
|
||||
reg [PKT_ADDR_W-1 : 0] address;
|
||||
always @* begin
|
||||
address = {PKT_ADDR_W{1'b0}};
|
||||
address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
|
||||
end
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Pass almost everything through, untouched
|
||||
// -------------------------------------------------------
|
||||
assign sink_ready = src_ready;
|
||||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [PKT_DEST_ID_W-1:0] default_destid;
|
||||
wire [4-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Write and read transaction signals
|
||||
// -------------------------------------------------------
|
||||
wire read_transaction;
|
||||
assign read_transaction = sink_data[PKT_TRANS_READ];
|
||||
|
||||
|
||||
jtag_io_mm_interconnect_0_router_default_decode the_default_decode(
|
||||
.default_destination_id (default_destid),
|
||||
.default_wr_channel (),
|
||||
.default_rd_channel (),
|
||||
.default_src_channel (default_src_channel)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
src_data = sink_data;
|
||||
src_channel = default_src_channel;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
|
||||
|
||||
// --------------------------------------------------
|
||||
// Address Decoder
|
||||
// Sets the channel and destination ID based on the address
|
||||
// --------------------------------------------------
|
||||
|
||||
// ( 0x0 .. 0x10 )
|
||||
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 6'h0 ) begin
|
||||
src_channel = 4'b0001;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
|
||||
end
|
||||
|
||||
// ( 0x10 .. 0x20 )
|
||||
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 6'h10 ) begin
|
||||
src_channel = 4'b0010;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
|
||||
end
|
||||
|
||||
// ( 0x20 .. 0x30 )
|
||||
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 6'h20 && read_transaction ) begin
|
||||
src_channel = 4'b0100;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
||||
end
|
||||
|
||||
// ( 0x30 .. 0x40 )
|
||||
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 6'h30 && read_transaction ) begin
|
||||
src_channel = 4'b1000;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[65:0] val;
|
||||
reg [65:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -0,0 +1,215 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Merlin Router
|
||||
//
|
||||
// Asserts the appropriate one-hot encoded channel based on
|
||||
// either (a) the address or (b) the dest id. The DECODER_TYPE
|
||||
// parameter controls this behaviour. 0 means address decoder,
|
||||
// 1 means dest id decoder.
|
||||
//
|
||||
// In the case of (a), it also sets the destination id.
|
||||
// -------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module jtag_io_mm_interconnect_0_router_001_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = 0,
|
||||
DEFAULT_WR_CHANNEL = -1,
|
||||
DEFAULT_RD_CHANNEL = -1,
|
||||
DEFAULT_DESTID = 0
|
||||
)
|
||||
(output [90 - 89 : 0] default_destination_id,
|
||||
output [4-1 : 0] default_wr_channel,
|
||||
output [4-1 : 0] default_rd_channel,
|
||||
output [4-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
DEFAULT_DESTID[90 - 89 : 0];
|
||||
|
||||
generate
|
||||
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
|
||||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 4'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
|
||||
assign default_wr_channel = '0;
|
||||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 4'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 4'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module jtag_io_mm_interconnect_0_router_001
|
||||
(
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Command Sink (Input)
|
||||
// -------------------
|
||||
input sink_valid,
|
||||
input [104-1 : 0] sink_data,
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Command Source (Output)
|
||||
// -------------------
|
||||
output src_valid,
|
||||
output reg [104-1 : 0] src_data,
|
||||
output reg [4-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
);
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Local parameters and variables
|
||||
// -------------------------------------------------------
|
||||
localparam PKT_ADDR_H = 67;
|
||||
localparam PKT_ADDR_L = 36;
|
||||
localparam PKT_DEST_ID_H = 90;
|
||||
localparam PKT_DEST_ID_L = 89;
|
||||
localparam PKT_PROTECTION_H = 94;
|
||||
localparam PKT_PROTECTION_L = 92;
|
||||
localparam ST_DATA_W = 104;
|
||||
localparam ST_CHANNEL_W = 4;
|
||||
localparam DECODER_TYPE = 1;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 70;
|
||||
localparam PKT_TRANS_READ = 71;
|
||||
|
||||
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
|
||||
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Figure out the number of bits to mask off for each slave span
|
||||
// during address decoding
|
||||
// -------------------------------------------------------
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h0;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
PKT_ADDR_H :
|
||||
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
|
||||
|
||||
localparam RG = RANGE_ADDR_WIDTH;
|
||||
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
|
||||
|
||||
reg [PKT_DEST_ID_W-1 : 0] destid;
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Pass almost everything through, untouched
|
||||
// -------------------------------------------------------
|
||||
assign sink_ready = src_ready;
|
||||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [4-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
jtag_io_mm_interconnect_0_router_001_default_decode the_default_decode(
|
||||
.default_destination_id (),
|
||||
.default_wr_channel (),
|
||||
.default_rd_channel (),
|
||||
.default_src_channel (default_src_channel)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
src_data = sink_data;
|
||||
src_channel = default_src_channel;
|
||||
|
||||
// --------------------------------------------------
|
||||
// DestinationID Decoder
|
||||
// Sets the channel based on the destination ID.
|
||||
// --------------------------------------------------
|
||||
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
|
||||
|
||||
|
||||
|
||||
if (destid == 0 ) begin
|
||||
src_channel = 4'b1;
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[65:0] val;
|
||||
reg [65:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -0,0 +1,100 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// -------------------------------------
|
||||
// Merlin Demultiplexer
|
||||
//
|
||||
// Asserts valid on the appropriate output
|
||||
// given a one-hot channel signal.
|
||||
// -------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: jtag_io_mm_interconnect_0_rsp_demux
|
||||
// ST_DATA_W: 104
|
||||
// ST_CHANNEL_W: 4
|
||||
// NUM_OUTPUTS: 1
|
||||
// VALID_WIDTH: 1
|
||||
// ------------------------------------------
|
||||
|
||||
//------------------------------------------
|
||||
// Message Supression Used
|
||||
// QIS Warnings
|
||||
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
|
||||
//------------------------------------------
|
||||
|
||||
module jtag_io_mm_interconnect_0_rsp_demux
|
||||
(
|
||||
// -------------------
|
||||
// Sink
|
||||
// -------------------
|
||||
input [1-1 : 0] sink_valid,
|
||||
input [104-1 : 0] sink_data, // ST_DATA_W=104
|
||||
input [4-1 : 0] sink_channel, // ST_CHANNEL_W=4
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Sources
|
||||
// -------------------
|
||||
output reg src0_valid,
|
||||
output reg [104-1 : 0] src0_data, // ST_DATA_W=104
|
||||
output reg [4-1 : 0] src0_channel, // ST_CHANNEL_W=4
|
||||
output reg src0_startofpacket,
|
||||
output reg src0_endofpacket,
|
||||
input src0_ready,
|
||||
|
||||
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
|
||||
input clk,
|
||||
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
|
||||
input reset
|
||||
|
||||
);
|
||||
|
||||
localparam NUM_OUTPUTS = 1;
|
||||
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
|
||||
|
||||
// -------------------
|
||||
// Demux
|
||||
// -------------------
|
||||
always @* begin
|
||||
src0_data = sink_data;
|
||||
src0_startofpacket = sink_startofpacket;
|
||||
src0_endofpacket = sink_endofpacket;
|
||||
src0_channel = sink_channel >> NUM_OUTPUTS;
|
||||
|
||||
src0_valid = sink_channel[0] && sink_valid;
|
||||
|
||||
end
|
||||
|
||||
// -------------------
|
||||
// Backpressure
|
||||
// -------------------
|
||||
assign ready_vector[0] = src0_ready;
|
||||
|
||||
assign sink_ready = |(sink_channel & {{3{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
|
||||
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,385 @@
|
||||
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2014 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/20.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2019/10/06 $
|
||||
// $Author: psgswbuild $
|
||||
|
||||
// ------------------------------------------
|
||||
// Merlin Multiplexer
|
||||
// ------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: jtag_io_mm_interconnect_0_rsp_mux
|
||||
// NUM_INPUTS: 4
|
||||
// ARBITRATION_SHARES: 1 1 1 1
|
||||
// ARBITRATION_SCHEME "no-arb"
|
||||
// PIPELINE_ARB: 0
|
||||
// PKT_TRANS_LOCK: 72 (arbitration locking enabled)
|
||||
// ST_DATA_W: 104
|
||||
// ST_CHANNEL_W: 4
|
||||
// ------------------------------------------
|
||||
|
||||
module jtag_io_mm_interconnect_0_rsp_mux
|
||||
(
|
||||
// ----------------------
|
||||
// Sinks
|
||||
// ----------------------
|
||||
input sink0_valid,
|
||||
input [104-1 : 0] sink0_data,
|
||||
input [4-1: 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output sink0_ready,
|
||||
|
||||
input sink1_valid,
|
||||
input [104-1 : 0] sink1_data,
|
||||
input [4-1: 0] sink1_channel,
|
||||
input sink1_startofpacket,
|
||||
input sink1_endofpacket,
|
||||
output sink1_ready,
|
||||
|
||||
input sink2_valid,
|
||||
input [104-1 : 0] sink2_data,
|
||||
input [4-1: 0] sink2_channel,
|
||||
input sink2_startofpacket,
|
||||
input sink2_endofpacket,
|
||||
output sink2_ready,
|
||||
|
||||
input sink3_valid,
|
||||
input [104-1 : 0] sink3_data,
|
||||
input [4-1: 0] sink3_channel,
|
||||
input sink3_startofpacket,
|
||||
input sink3_endofpacket,
|
||||
output sink3_ready,
|
||||
|
||||
|
||||
// ----------------------
|
||||
// Source
|
||||
// ----------------------
|
||||
output src_valid,
|
||||
output [104-1 : 0] src_data,
|
||||
output [4-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready,
|
||||
|
||||
// ----------------------
|
||||
// Clock & Reset
|
||||
// ----------------------
|
||||
input clk,
|
||||
input reset
|
||||
);
|
||||
localparam PAYLOAD_W = 104 + 4 + 2;
|
||||
localparam NUM_INPUTS = 4;
|
||||
localparam SHARE_COUNTER_W = 1;
|
||||
localparam PIPELINE_ARB = 0;
|
||||
localparam ST_DATA_W = 104;
|
||||
localparam ST_CHANNEL_W = 4;
|
||||
localparam PKT_TRANS_LOCK = 72;
|
||||
|
||||
// ------------------------------------------
|
||||
// Signals
|
||||
// ------------------------------------------
|
||||
wire [NUM_INPUTS - 1 : 0] request;
|
||||
wire [NUM_INPUTS - 1 : 0] valid;
|
||||
wire [NUM_INPUTS - 1 : 0] grant;
|
||||
wire [NUM_INPUTS - 1 : 0] next_grant;
|
||||
reg [NUM_INPUTS - 1 : 0] saved_grant;
|
||||
reg [PAYLOAD_W - 1 : 0] src_payload;
|
||||
wire last_cycle;
|
||||
reg packet_in_progress;
|
||||
reg update_grant;
|
||||
|
||||
wire [PAYLOAD_W - 1 : 0] sink0_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink1_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink2_payload;
|
||||
wire [PAYLOAD_W - 1 : 0] sink3_payload;
|
||||
|
||||
assign valid[0] = sink0_valid;
|
||||
assign valid[1] = sink1_valid;
|
||||
assign valid[2] = sink2_valid;
|
||||
assign valid[3] = sink3_valid;
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
// ------------------------------------------
|
||||
// Grant Logic & Updates
|
||||
// ------------------------------------------
|
||||
// ------------------------------------------
|
||||
reg [NUM_INPUTS - 1 : 0] lock;
|
||||
always @* begin
|
||||
lock[0] = sink0_data[72];
|
||||
lock[1] = sink1_data[72];
|
||||
lock[2] = sink2_data[72];
|
||||
lock[3] = sink3_data[72];
|
||||
end
|
||||
|
||||
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
|
||||
|
||||
// ------------------------------------------
|
||||
// We're working on a packet at any time valid is high, except
|
||||
// when this is the endofpacket.
|
||||
// ------------------------------------------
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
packet_in_progress <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (last_cycle)
|
||||
packet_in_progress <= 1'b0;
|
||||
else if (src_valid)
|
||||
packet_in_progress <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
// Shares
|
||||
//
|
||||
// Special case: all-equal shares _should_ be optimized into assigning a
|
||||
// constant to next_grant_share.
|
||||
// Special case: all-1's shares _should_ result in the share counter
|
||||
// being optimized away.
|
||||
// ------------------------------------------
|
||||
// Input | arb shares | counter load value
|
||||
// 0 | 1 | 0
|
||||
// 1 | 1 | 0
|
||||
// 2 | 1 | 0
|
||||
// 3 | 1 | 0
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
|
||||
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
|
||||
|
||||
// ------------------------------------------
|
||||
// Choose the share value corresponding to the grant.
|
||||
// ------------------------------------------
|
||||
reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
|
||||
always @* begin
|
||||
next_grant_share =
|
||||
share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
|
||||
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
|
||||
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
|
||||
share_3 & { SHARE_COUNTER_W {next_grant[3]} };
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
// Flag to indicate first packet of an arb sequence.
|
||||
// ------------------------------------------
|
||||
wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
|
||||
reg first_packet_r;
|
||||
wire first_packet = grant_changed | first_packet_r;
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
first_packet_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (update_grant)
|
||||
first_packet_r <= 1'b1;
|
||||
else if (last_cycle)
|
||||
first_packet_r <= 1'b0;
|
||||
else if (grant_changed)
|
||||
first_packet_r <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
// Compute the next share-count value.
|
||||
// ------------------------------------------
|
||||
reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
|
||||
reg [SHARE_COUNTER_W - 1 : 0] share_count;
|
||||
reg share_count_zero_flag;
|
||||
|
||||
always @* begin
|
||||
if (first_packet) begin
|
||||
p1_share_count = next_grant_share;
|
||||
end
|
||||
else begin
|
||||
// Update the counter, but don't decrement below 0.
|
||||
p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
// Update the share counter and share-counter=zero flag.
|
||||
// ------------------------------------------
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
share_count <= '0;
|
||||
share_count_zero_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (last_cycle) begin
|
||||
share_count <= p1_share_count;
|
||||
share_count_zero_flag <= (p1_share_count == '0);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
// For each input, maintain a final_packet signal which goes active for the
|
||||
// last packet of a full-share packet sequence. Example: if I have 4
|
||||
// shares and I'm continuously requesting, final_packet is active in the
|
||||
// 4th packet.
|
||||
// ------------------------------------------
|
||||
wire final_packet_0 = 1'b1;
|
||||
|
||||
wire final_packet_1 = 1'b1;
|
||||
|
||||
wire final_packet_2 = 1'b1;
|
||||
|
||||
wire final_packet_3 = 1'b1;
|
||||
|
||||
|
||||
// ------------------------------------------
|
||||
// Concatenate all final_packet signals (wire or reg) into a handy vector.
|
||||
// ------------------------------------------
|
||||
wire [NUM_INPUTS - 1 : 0] final_packet = {
|
||||
final_packet_3,
|
||||
final_packet_2,
|
||||
final_packet_1,
|
||||
final_packet_0
|
||||
};
|
||||
|
||||
// ------------------------------------------
|
||||
// ------------------------------------------
|
||||
wire p1_done = |(final_packet & grant);
|
||||
|
||||
// ------------------------------------------
|
||||
// Flag for the first cycle of packets within an
|
||||
// arb sequence
|
||||
// ------------------------------------------
|
||||
reg first_cycle;
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
first_cycle <= 0;
|
||||
else
|
||||
first_cycle <= last_cycle && ~p1_done;
|
||||
end
|
||||
|
||||
|
||||
always @* begin
|
||||
update_grant = 0;
|
||||
|
||||
// ------------------------------------------
|
||||
// No arbitration pipeline, update grant whenever
|
||||
// the current arb winner has consumed all shares,
|
||||
// or all requests are low
|
||||
// ------------------------------------------
|
||||
update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
|
||||
update_grant = last_cycle;
|
||||
end
|
||||
|
||||
wire save_grant;
|
||||
assign save_grant = 1;
|
||||
assign grant = next_grant;
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
saved_grant <= '0;
|
||||
else if (save_grant)
|
||||
saved_grant <= next_grant;
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
// ------------------------------------------
|
||||
// Arbitrator
|
||||
// ------------------------------------------
|
||||
// ------------------------------------------
|
||||
|
||||
// ------------------------------------------
|
||||
// Create a request vector that stays high during
|
||||
// the packet for unpipelined arbitration.
|
||||
//
|
||||
// The pipelined arbitration scheme does not require
|
||||
// request to be held high during the packet.
|
||||
// ------------------------------------------
|
||||
assign request = valid;
|
||||
|
||||
wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
|
||||
|
||||
altera_merlin_arbitrator
|
||||
#(
|
||||
.NUM_REQUESTERS(NUM_INPUTS),
|
||||
.SCHEME ("no-arb"),
|
||||
.PIPELINE (0)
|
||||
) arb (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.request (request),
|
||||
.grant (next_grant_from_arb),
|
||||
.save_top_priority (src_valid),
|
||||
.increment_top_priority (update_grant)
|
||||
);
|
||||
|
||||
assign next_grant = next_grant_from_arb;
|
||||
|
||||
// ------------------------------------------
|
||||
// ------------------------------------------
|
||||
// Mux
|
||||
//
|
||||
// Implemented as a sum of products.
|
||||
// ------------------------------------------
|
||||
// ------------------------------------------
|
||||
|
||||
assign sink0_ready = src_ready && grant[0];
|
||||
assign sink1_ready = src_ready && grant[1];
|
||||
assign sink2_ready = src_ready && grant[2];
|
||||
assign sink3_ready = src_ready && grant[3];
|
||||
|
||||
assign src_valid = |(grant & valid);
|
||||
|
||||
always @* begin
|
||||
src_payload =
|
||||
sink0_payload & {PAYLOAD_W {grant[0]} } |
|
||||
sink1_payload & {PAYLOAD_W {grant[1]} } |
|
||||
sink2_payload & {PAYLOAD_W {grant[2]} } |
|
||||
sink3_payload & {PAYLOAD_W {grant[3]} };
|
||||
end
|
||||
|
||||
// ------------------------------------------
|
||||
// Mux Payload Mapping
|
||||
// ------------------------------------------
|
||||
|
||||
assign sink0_payload = {sink0_channel,sink0_data,
|
||||
sink0_startofpacket,sink0_endofpacket};
|
||||
assign sink1_payload = {sink1_channel,sink1_data,
|
||||
sink1_startofpacket,sink1_endofpacket};
|
||||
assign sink2_payload = {sink2_channel,sink2_data,
|
||||
sink2_startofpacket,sink2_endofpacket};
|
||||
assign sink3_payload = {sink3_channel,sink3_data,
|
||||
sink3_startofpacket,sink3_endofpacket};
|
||||
|
||||
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
|
||||
endmodule
|
||||
|
||||
|
||||
@ -0,0 +1,67 @@
|
||||
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
//simulation files), and any associated documentation or information are
|
||||
//expressly subject to the terms and conditions of the Altera Program
|
||||
//License Subscription Agreement or other applicable license agreement,
|
||||
//including, without limitation, that your use is for the sole purpose
|
||||
//of programming logic devices manufactured by Altera and sold by Altera
|
||||
//or its authorized distributors. Please refer to the applicable
|
||||
//agreement for further details.
|
||||
|
||||
// synthesis translate_off
|
||||
`timescale 1ns / 1ps
|
||||
// synthesis translate_on
|
||||
|
||||
// turn off superfluous verilog processor warnings
|
||||
// altera message_level Level1
|
||||
// altera message_off 10034 10035 10036 10037 10230 10240 10030
|
||||
|
||||
module jtag_io_out0 (
|
||||
// inputs:
|
||||
address,
|
||||
chipselect,
|
||||
clk,
|
||||
reset_n,
|
||||
write_n,
|
||||
writedata,
|
||||
|
||||
// outputs:
|
||||
out_port,
|
||||
readdata
|
||||
)
|
||||
;
|
||||
|
||||
output [ 31: 0] out_port;
|
||||
output [ 31: 0] readdata;
|
||||
input [ 1: 0] address;
|
||||
input chipselect;
|
||||
input clk;
|
||||
input reset_n;
|
||||
input write_n;
|
||||
input [ 31: 0] writedata;
|
||||
|
||||
|
||||
wire clk_en;
|
||||
reg [ 31: 0] data_out;
|
||||
wire [ 31: 0] out_port;
|
||||
wire [ 31: 0] read_mux_out;
|
||||
wire [ 31: 0] readdata;
|
||||
assign clk_en = 1;
|
||||
//s1, which is an e_avalon_slave
|
||||
assign read_mux_out = {32 {(address == 0)}} & data_out;
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
data_out <= 0;
|
||||
else if (chipselect && ~write_n && (address == 0))
|
||||
data_out <= writedata[31 : 0];
|
||||
end
|
||||
|
||||
|
||||
assign readdata = {32'b0 | read_mux_out};
|
||||
assign out_port = data_out;
|
||||
|
||||
endmodule
|
||||
|
||||
93
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.bsf
Executable file
93
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.bsf
Executable file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 184)
|
||||
(text "sys_pll" (rect 60 -1 88 11)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 168 20 180)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
|
||||
(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
|
||||
(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 48 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 72)
|
||||
(output)
|
||||
(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
|
||||
(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 72)(pt 112 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 112)
|
||||
(output)
|
||||
(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
|
||||
(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 112)(pt 112 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 152)
|
||||
(output)
|
||||
(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
|
||||
(text "locked" (rect 127 141 163 152)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 152)(pt 112 152)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
|
||||
(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
|
||||
(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
|
||||
(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
|
||||
(text "locked" (rect 113 123 262 259)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 82 147 200 304)(font "Arial" (color 0 0 0)))
|
||||
(text " altera_pll " (rect 118 168 308 346)(font "Arial" ))
|
||||
(line (pt 48 32)(pt 112 32)(line_width 1))
|
||||
(line (pt 112 32)(pt 112 168)(line_width 1))
|
||||
(line (pt 48 168)(pt 112 168)(line_width 1))
|
||||
(line (pt 48 32)(pt 48 168)(line_width 1))
|
||||
(line (pt 49 52)(pt 49 76)(line_width 1))
|
||||
(line (pt 50 52)(pt 50 76)(line_width 1))
|
||||
(line (pt 49 92)(pt 49 116)(line_width 1))
|
||||
(line (pt 50 92)(pt 50 116)(line_width 1))
|
||||
(line (pt 111 52)(pt 111 76)(line_width 1))
|
||||
(line (pt 110 52)(pt 110 76)(line_width 1))
|
||||
(line (pt 111 92)(pt 111 116)(line_width 1))
|
||||
(line (pt 110 92)(pt 110 116)(line_width 1))
|
||||
(line (pt 111 132)(pt 111 156)(line_width 1))
|
||||
(line (pt 110 132)(pt 110 156)(line_width 1))
|
||||
(line (pt 0 0)(pt 160 0)(line_width 1))
|
||||
(line (pt 160 0)(pt 160 184)(line_width 1))
|
||||
(line (pt 0 184)(pt 160 184)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 184)(line_width 1))
|
||||
)
|
||||
)
|
||||
10
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.cmp
Executable file
10
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.cmp
Executable file
@ -0,0 +1,10 @@
|
||||
component sys_pll is
|
||||
port (
|
||||
refclk : in std_logic := 'X'; -- clk
|
||||
rst : in std_logic := 'X'; -- reset
|
||||
outclk_0 : out std_logic; -- clk
|
||||
outclk_1 : out std_logic; -- clk
|
||||
locked : out std_logic -- export
|
||||
);
|
||||
end component sys_pll;
|
||||
|
||||
14
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.ppf
Executable file
14
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.ppf
Executable file
@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<pinplan
|
||||
variation_name="sys_pll"
|
||||
megafunction_name="ALTERA_PLL"
|
||||
intended_family="Cyclone V"
|
||||
specifies="all_ports">
|
||||
<global>
|
||||
<pin name="refclk" direction="input" scope="external" />
|
||||
<pin name="rst" direction="input" scope="external" />
|
||||
<pin name="outclk_0" direction="output" scope="external" />
|
||||
<pin name="outclk_1" direction="output" scope="external" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
</global>
|
||||
</pinplan>
|
||||
337
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.qip
Executable file
337
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.qip
Executable file
@ -0,0 +1,337 @@
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "sys_pll" -name MISC_FILE [file join $::quartus(qip_path) "sys_pll.cmp"]
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_QSYS_MODE "UNKNOWN"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_COMPONENT_NAME "c3lzX3BsbA=="
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "sys_pll" -library "sys_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_NAME "c3lzX3BsbF8wMDAy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTI1LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTI1LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::NTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw1LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDIsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMjU2LDI1NiwxLDAscGhfbXV4X2Nsayx0cnVlLGZhbHNlLDIsMjAsNDAwMCw1MDAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLGZhbHNl::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
|
||||
|
||||
set_global_assignment -library "sys_pll" -name VERILOG_FILE [file join $::quartus(qip_path) "sys_pll.v"]
|
||||
set_global_assignment -library "sys_pll" -name VERILOG_FILE [file join $::quartus(qip_path) "sys_pll/sys_pll_0002.v"]
|
||||
set_global_assignment -library "sys_pll" -name QIP_FILE [file join $::quartus(qip_path) "sys_pll/sys_pll_0002.qip"]
|
||||
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "sys_pll_0002" -library "sys_pll" -name IP_TOOL_ENV "mwpim"
|
||||
6
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.sip
Executable file
6
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.sip
Executable file
@ -0,0 +1,6 @@
|
||||
set_global_assignment -entity "sys_pll" -library "lib_sys_pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "sys_pll" -library "lib_sys_pll" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "sys_pll" -library "lib_sys_pll" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "lib_sys_pll" -name SPD_FILE [file join $::quartus(sip_path) "sys_pll.spd"]
|
||||
|
||||
set_global_assignment -library "lib_sys_pll" -name MISC_FILE [file join $::quartus(sip_path) "sys_pll_sim/sys_pll.vo"]
|
||||
6
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.spd
Executable file
6
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.spd
Executable file
@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<simPackage>
|
||||
<file path="sys_pll_sim/sys_pll.vo" type="VERILOG" />
|
||||
<topLevel name="sys_pll" />
|
||||
<deviceFamily name="cyclonev" />
|
||||
</simPackage>
|
||||
255
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.v
Executable file
255
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll.v
Executable file
@ -0,0 +1,255 @@
|
||||
// megafunction wizard: %PLL Intel FPGA IP v20.1%
|
||||
// GENERATION: XML
|
||||
// sys_pll.v
|
||||
|
||||
// Generated using ACDS version 20.1 711
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module sys_pll (
|
||||
input wire refclk, // refclk.clk
|
||||
input wire rst, // reset.reset
|
||||
output wire outclk_0, // outclk0.clk
|
||||
output wire outclk_1, // outclk1.clk
|
||||
output wire locked // locked.export
|
||||
);
|
||||
|
||||
sys_pll_0002 sys_pll_inst (
|
||||
.refclk (refclk), // refclk.clk
|
||||
.rst (rst), // reset.reset
|
||||
.outclk_0 (outclk_0), // outclk0.clk
|
||||
.outclk_1 (outclk_1), // outclk1.clk
|
||||
.locked (locked) // locked.export
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2022 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="20.1" >
|
||||
// Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
|
||||
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
|
||||
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
|
||||
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
|
||||
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
|
||||
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
|
||||
// Retrieval info: <generic name="gui_use_locked" value="true" />
|
||||
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
|
||||
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
|
||||
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency0" value="125.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency1" value="500.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
|
||||
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
|
||||
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
|
||||
// Retrieval info: <generic name="gui_en_reconf" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
|
||||
// Retrieval info: <generic name="gui_phout_division" value="1" />
|
||||
// Retrieval info: <generic name="gui_mif_generate" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
|
||||
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
|
||||
// Retrieval info: <generic name="gui_dps_num" value="1" />
|
||||
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
|
||||
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
|
||||
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
|
||||
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
|
||||
// Retrieval info: <generic name="gui_active_clk" value="false" />
|
||||
// Retrieval info: <generic name="gui_clk_bad" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
|
||||
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
|
||||
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
|
||||
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : sys_pll.vo
|
||||
// RELATED_FILES: sys_pll.v, sys_pll_0002.v
|
||||
@ -0,0 +1,4 @@
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*sys_pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
|
||||
set_instance_assignment -name PLL_AUTO_RESET OFF -to "*sys_pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*sys_pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
@ -0,0 +1,90 @@
|
||||
`timescale 1ns/10ps
|
||||
module sys_pll_0002(
|
||||
|
||||
// interface 'refclk'
|
||||
input wire refclk,
|
||||
|
||||
// interface 'reset'
|
||||
input wire rst,
|
||||
|
||||
// interface 'outclk0'
|
||||
output wire outclk_0,
|
||||
|
||||
// interface 'outclk1'
|
||||
output wire outclk_1,
|
||||
|
||||
// interface 'locked'
|
||||
output wire locked
|
||||
);
|
||||
|
||||
altera_pll #(
|
||||
.fractional_vco_multiplier("false"),
|
||||
.reference_clock_frequency("50.0 MHz"),
|
||||
.operation_mode("direct"),
|
||||
.number_of_clocks(2),
|
||||
.output_clock_frequency0("125.000000 MHz"),
|
||||
.phase_shift0("0 ps"),
|
||||
.duty_cycle0(50),
|
||||
.output_clock_frequency1("500.000000 MHz"),
|
||||
.phase_shift1("0 ps"),
|
||||
.duty_cycle1(50),
|
||||
.output_clock_frequency2("0 MHz"),
|
||||
.phase_shift2("0 ps"),
|
||||
.duty_cycle2(50),
|
||||
.output_clock_frequency3("0 MHz"),
|
||||
.phase_shift3("0 ps"),
|
||||
.duty_cycle3(50),
|
||||
.output_clock_frequency4("0 MHz"),
|
||||
.phase_shift4("0 ps"),
|
||||
.duty_cycle4(50),
|
||||
.output_clock_frequency5("0 MHz"),
|
||||
.phase_shift5("0 ps"),
|
||||
.duty_cycle5(50),
|
||||
.output_clock_frequency6("0 MHz"),
|
||||
.phase_shift6("0 ps"),
|
||||
.duty_cycle6(50),
|
||||
.output_clock_frequency7("0 MHz"),
|
||||
.phase_shift7("0 ps"),
|
||||
.duty_cycle7(50),
|
||||
.output_clock_frequency8("0 MHz"),
|
||||
.phase_shift8("0 ps"),
|
||||
.duty_cycle8(50),
|
||||
.output_clock_frequency9("0 MHz"),
|
||||
.phase_shift9("0 ps"),
|
||||
.duty_cycle9(50),
|
||||
.output_clock_frequency10("0 MHz"),
|
||||
.phase_shift10("0 ps"),
|
||||
.duty_cycle10(50),
|
||||
.output_clock_frequency11("0 MHz"),
|
||||
.phase_shift11("0 ps"),
|
||||
.duty_cycle11(50),
|
||||
.output_clock_frequency12("0 MHz"),
|
||||
.phase_shift12("0 ps"),
|
||||
.duty_cycle12(50),
|
||||
.output_clock_frequency13("0 MHz"),
|
||||
.phase_shift13("0 ps"),
|
||||
.duty_cycle13(50),
|
||||
.output_clock_frequency14("0 MHz"),
|
||||
.phase_shift14("0 ps"),
|
||||
.duty_cycle14(50),
|
||||
.output_clock_frequency15("0 MHz"),
|
||||
.phase_shift15("0 ps"),
|
||||
.duty_cycle15(50),
|
||||
.output_clock_frequency16("0 MHz"),
|
||||
.phase_shift16("0 ps"),
|
||||
.duty_cycle16(50),
|
||||
.output_clock_frequency17("0 MHz"),
|
||||
.phase_shift17("0 ps"),
|
||||
.duty_cycle17(50),
|
||||
.pll_type("General"),
|
||||
.pll_subtype("General")
|
||||
) altera_pll_i (
|
||||
.rst (rst),
|
||||
.outclk ({outclk_1, outclk_0}),
|
||||
.locked (locked),
|
||||
.fboutclk ( ),
|
||||
.fbclk (1'b0),
|
||||
.refclk (refclk)
|
||||
);
|
||||
endmodule
|
||||
|
||||
1
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll_sim.f
Executable file
1
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll_sim.f
Executable file
@ -0,0 +1 @@
|
||||
sys_pll_sim/sys_pll.vo
|
||||
@ -0,0 +1,278 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 20.1 711 win32 2022.04.01.12:36:35
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script rivierapro_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# sys_pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Altera simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "aldec.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog -sv2k5 <your compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If sys_pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "sys_pll"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "C:/intelfpga_lite/20.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
|
||||
} else {
|
||||
}
|
||||
|
||||
set Aldec "Riviera"
|
||||
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
|
||||
set Aldec "Active"
|
||||
}
|
||||
|
||||
if { [ string match "Active" $Aldec ] } {
|
||||
scripterconf -tcl
|
||||
createdesign "$TOP_LEVEL_NAME" "."
|
||||
opendesign "$TOP_LEVEL_NAME"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
ensure_lib ./libraries
|
||||
ensure_lib ./libraries/work
|
||||
vmap work ./libraries/work
|
||||
ensure_lib ./libraries/altera_ver
|
||||
vmap altera_ver ./libraries/altera_ver
|
||||
ensure_lib ./libraries/lpm_ver
|
||||
vmap lpm_ver ./libraries/lpm_ver
|
||||
ensure_lib ./libraries/sgate_ver
|
||||
vmap sgate_ver ./libraries/sgate_ver
|
||||
ensure_lib ./libraries/altera_mf_ver
|
||||
vmap altera_mf_ver ./libraries/altera_mf_ver
|
||||
ensure_lib ./libraries/altera_lnsim_ver
|
||||
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
|
||||
ensure_lib ./libraries/cyclonev_ver
|
||||
vmap cyclonev_ver ./libraries/cyclonev_ver
|
||||
ensure_lib ./libraries/cyclonev_hssi_ver
|
||||
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
|
||||
ensure_lib ./libraries/cyclonev_pcie_hip_ver
|
||||
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
echo "\[exec\] dev_com"
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
|
||||
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
echo "\[exec\] com"
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/sys_pll.vo"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
echo "\[exec\] elab"
|
||||
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -dbg -O2 option
|
||||
alias elab_debug {
|
||||
echo "\[exec\] elab_debug"
|
||||
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -dbg -O2
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
@ -0,0 +1,19 @@
|
||||
|
||||
DEFINE std $CDS_ROOT/tools/inca/files/STD/
|
||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
|
||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
|
||||
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
|
||||
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
|
||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
|
||||
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
|
||||
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
|
||||
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
|
||||
DEFINE work ./libraries/work/
|
||||
DEFINE altera_ver ./libraries/altera_ver/
|
||||
DEFINE lpm_ver ./libraries/lpm_ver/
|
||||
DEFINE sgate_ver ./libraries/sgate_ver/
|
||||
DEFINE altera_mf_ver ./libraries/altera_mf_ver/
|
||||
DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/
|
||||
DEFINE cyclonev_ver ./libraries/cyclonev_ver/
|
||||
DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
|
||||
DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
|
||||
@ -0,0 +1,2 @@
|
||||
|
||||
DEFINE WORK work
|
||||
@ -0,0 +1,195 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 20.1 711 win32 2022.04.01.12:36:35
|
||||
|
||||
# ----------------------------------------
|
||||
# ncsim - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# sys_pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Altera simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "ncsim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated files
|
||||
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
|
||||
# # into the location from which you launch the simulator, or incorporate
|
||||
# # into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/cadence/ncsim_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# ncvlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/cadence/ncsim_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME=<simulation top> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If sys_pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 20.1 711 win32 2022.04.01.12:36:35
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="sys_pll"
|
||||
QSYS_SIMDIR="./../"
|
||||
QUARTUS_INSTALL_DIR="C:/intelfpga_lite/20.1/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
|
||||
:
|
||||
else
|
||||
:
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
mkdir -p ./libraries/work/
|
||||
mkdir -p ./libraries/altera_ver/
|
||||
mkdir -p ./libraries/lpm_ver/
|
||||
mkdir -p ./libraries/sgate_ver/
|
||||
mkdir -p ./libraries/altera_mf_ver/
|
||||
mkdir -p ./libraries/altera_lnsim_ver/
|
||||
mkdir -p ./libraries/cyclonev_ver/
|
||||
mkdir -p ./libraries/cyclonev_hssi_ver/
|
||||
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
|
||||
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/sys_pll.vo"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
export GENERIC_PARAM_COMPAT_CHECK=1
|
||||
ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
@ -0,0 +1,272 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script msim_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# sys_pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Altera simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "mentor.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run -a
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If sys_pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 20.1 711 win32 2022.04.01.12:36:35
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "sys_pll"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "C:/intelfpga_lite/20.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
|
||||
} else {
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
ensure_lib ./libraries/
|
||||
ensure_lib ./libraries/work/
|
||||
vmap work ./libraries/work/
|
||||
vmap work_lib ./libraries/work/
|
||||
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
|
||||
ensure_lib ./libraries/altera_ver/
|
||||
vmap altera_ver ./libraries/altera_ver/
|
||||
ensure_lib ./libraries/lpm_ver/
|
||||
vmap lpm_ver ./libraries/lpm_ver/
|
||||
ensure_lib ./libraries/sgate_ver/
|
||||
vmap sgate_ver ./libraries/sgate_ver/
|
||||
ensure_lib ./libraries/altera_mf_ver/
|
||||
vmap altera_mf_ver ./libraries/altera_mf_ver/
|
||||
ensure_lib ./libraries/altera_lnsim_ver/
|
||||
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
|
||||
ensure_lib ./libraries/cyclonev_ver/
|
||||
vmap cyclonev_ver ./libraries/cyclonev_ver/
|
||||
ensure_lib ./libraries/cyclonev_hssi_ver/
|
||||
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
|
||||
ensure_lib ./libraries/cyclonev_pcie_hip_ver/
|
||||
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
echo "\[exec\] dev_com"
|
||||
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
|
||||
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
|
||||
}
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
echo "\[exec\] com"
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/sys_pll.vo"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
echo "\[exec\] elab"
|
||||
eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -voptargs=+acc option
|
||||
alias elab_debug {
|
||||
echo "\[exec\] elab_debug"
|
||||
eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -voptargs=+acc
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
@ -0,0 +1,152 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 20.1 711 win32 2022.04.01.12:36:35
|
||||
|
||||
# ----------------------------------------
|
||||
# vcs - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# sys_pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Altera simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, follow the guidelines below.
|
||||
#
|
||||
# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
|
||||
# below into a new file, e.g. named "vcs_sim.sh".
|
||||
#
|
||||
# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
|
||||
# a separate file, e.g. named "filelist.f".
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
|
||||
# # set the top-level simulation or testbench module/entity name.
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# # Source the Quartus-generated IP simulation script and do the following:
|
||||
# # - Compile the Quartus EDA simulation library and IP simulation files.
|
||||
# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
|
||||
# # - Compile the design and top-level simulation module/entity using
|
||||
# # information specified in "filelist.f".
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# # - Run the simulation.
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
|
||||
# TOP_LEVEL_NAME=<simulation top> \
|
||||
# QSYS_SIMDIR=<script generation output directory> \
|
||||
# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# +systemverilogext+.sv
|
||||
# <design and testbench files, compile-time options, elaboration options>
|
||||
# #
|
||||
# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If sys_pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 20.1 711 win32 2022.04.01.12:36:35
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="sys_pll"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="C:/intelfpga_lite/20.1/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `vcs -platform` != *"amd64"* ]]; then
|
||||
:
|
||||
else
|
||||
:
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
|
||||
vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
|
||||
$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
|
||||
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
|
||||
$QSYS_SIMDIR/sys_pll.vo \
|
||||
-top $TOP_LEVEL_NAME
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
|
||||
fi
|
||||
@ -0,0 +1,13 @@
|
||||
|
||||
WORK > DEFAULT
|
||||
DEFAULT: ./libraries/work/
|
||||
work: ./libraries/work/
|
||||
altera_ver: ./libraries/altera_ver/
|
||||
lpm_ver: ./libraries/lpm_ver/
|
||||
sgate_ver: ./libraries/sgate_ver/
|
||||
altera_mf_ver: ./libraries/altera_mf_ver/
|
||||
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
|
||||
cyclonev_ver: ./libraries/cyclonev_ver/
|
||||
cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/
|
||||
cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
|
||||
LIBRARY_SCAN = TRUE
|
||||
@ -0,0 +1,195 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 20.1 711 win32 2022.04.01.12:36:35
|
||||
|
||||
# ----------------------------------------
|
||||
# vcsmx - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# sys_pll
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Altera simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated library
|
||||
# # setup "synopsys_sim.setup" into the location from which you launch the
|
||||
# # simulator, or incorporate into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# #
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# vlogan <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME="'-top <simulation top>'" \
|
||||
# QSYS_SIMDIR=<script generation output directory> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If sys_pll is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 20.1 711 win32 2022.04.01.12:36:35
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="sys_pll"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="C:/intelfpga_lite/20.1/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `vcs -platform` != *"amd64"* ]]; then
|
||||
:
|
||||
else
|
||||
:
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
mkdir -p ./libraries/work/
|
||||
mkdir -p ./libraries/altera_ver/
|
||||
mkdir -p ./libraries/lpm_ver/
|
||||
mkdir -p ./libraries/sgate_ver/
|
||||
mkdir -p ./libraries/altera_mf_ver/
|
||||
mkdir -p ./libraries/altera_lnsim_ver/
|
||||
mkdir -p ./libraries/cyclonev_ver/
|
||||
mkdir -p ./libraries/cyclonev_hssi_ver/
|
||||
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/sys_pll.vo"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
|
||||
fi
|
||||
300
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll_sim/sys_pll.vo
Executable file
300
example_projects/quartus_test_prj_template_v4/ip/sys_pll/sys_pll_sim/sys_pll.vo
Executable file
@ -0,0 +1,300 @@
|
||||
//IP Functional Simulation Model
|
||||
//VERSION_BEGIN 20.1 cbx_mgl 2020:06:05:12:11:10:SJ cbx_simgen 2020:06:05:12:04:51:SJ VERSION_END
|
||||
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||||
// altera message_off 10463
|
||||
|
||||
|
||||
|
||||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// You may only use these simulation model output files for simulation
|
||||
// purposes and expressly not for synthesis or any other purposes (in which
|
||||
// event Intel disclaims all warranties of any kind).
|
||||
|
||||
|
||||
//synopsys translate_off
|
||||
|
||||
//synthesis_resources = altera_pll 1
|
||||
`timescale 1 ps / 1 ps
|
||||
module sys_pll
|
||||
(
|
||||
locked,
|
||||
outclk_0,
|
||||
outclk_1,
|
||||
refclk,
|
||||
rst) /* synthesis synthesis_clearbox=1 */;
|
||||
output locked;
|
||||
output outclk_0;
|
||||
output outclk_1;
|
||||
input refclk;
|
||||
input rst;
|
||||
|
||||
wire wire_sys_pll_altera_pll_altera_pll_i_1098_locked;
|
||||
wire [1:0] wire_sys_pll_altera_pll_altera_pll_i_1098_outclk;
|
||||
|
||||
altera_pll sys_pll_altera_pll_altera_pll_i_1098
|
||||
(
|
||||
.fbclk(1'b0),
|
||||
.locked(wire_sys_pll_altera_pll_altera_pll_i_1098_locked),
|
||||
.outclk(wire_sys_pll_altera_pll_altera_pll_i_1098_outclk),
|
||||
.refclk(refclk),
|
||||
.rst(rst));
|
||||
defparam
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en0 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en1 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en10 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en11 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en12 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en13 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en14 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en15 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en16 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en17 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en2 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en3 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en4 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en5 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en6 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en7 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en8 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_bypass_en9 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div0 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div1 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div10 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div11 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div12 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div13 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div14 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div15 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div16 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div17 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div2 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div3 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div4 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div5 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div6 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div7 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div8 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_hi_div9 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src0 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src1 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src10 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src11 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src12 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src13 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src14 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src15 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src16 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src17 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src2 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src3 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src4 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src5 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src6 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src7 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src8 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_in_src9 = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div0 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div1 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div10 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div11 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div12 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div13 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div14 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div15 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div16 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div17 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div2 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div3 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div4 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div5 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div6 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div7 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div8 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_lo_div9 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en0 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en1 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en10 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en11 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en12 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en13 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en14 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en15 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en16 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en17 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en2 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en3 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en4 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en5 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en6 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en7 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en8 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_odd_div_duty_en9 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst0 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst1 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst10 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst11 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst12 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst13 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst14 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst15 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst16 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst17 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst2 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst3 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst4 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst5 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst6 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst7 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst8 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_ph_mux_prst9 = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst0 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst1 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst10 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst11 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst12 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst13 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst14 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst15 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst16 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst17 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst2 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst3 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst4 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst5 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst6 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst7 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst8 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.c_cnt_prst9 = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_0 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_1 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_2 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_3 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_4 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_5 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_6 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_7 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_8 = "UNUSED",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_0 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_1 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_2 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_3 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_4 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_5 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_6 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_7 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.clock_name_global_8 = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.data_rate = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.deserialization_factor = 4,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle0 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle1 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle10 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle11 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle12 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle13 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle14 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle15 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle16 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle17 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle2 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle3 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle4 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle5 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle6 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle7 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle8 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.duty_cycle9 = 50,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.fractional_vco_multiplier = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.m_cnt_bypass_en = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.m_cnt_hi_div = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.m_cnt_lo_div = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.m_cnt_odd_div_duty_en = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.mimic_fbclk_type = "gclk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.n_cnt_bypass_en = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.n_cnt_hi_div = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.n_cnt_lo_div = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.n_cnt_odd_div_duty_en = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.number_of_clocks = 2,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.operation_mode = "direct",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency0 = "125.000000 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency1 = "500.000000 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency10 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency11 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency12 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency13 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency14 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency15 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency16 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency17 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency2 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency3 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency4 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency5 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency6 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency7 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency8 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.output_clock_frequency9 = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift0 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift1 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift10 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift11 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift12 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift13 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift14 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift15 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift16 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift17 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift2 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift3 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift4 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift5 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift6 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift7 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift8 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.phase_shift9 = "0 ps",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_auto_clk_sw_en = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_bw_sel = "low",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_bwctrl = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_clk_loss_sw_en = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_clk_sw_dly = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_clkin_0_src = "clk_0",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_clkin_1_src = "clk_0",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_cp_current = 0,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_dsm_out_sel = "1st_order",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_fbclk_mux_1 = "glb",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_fbclk_mux_2 = "fb_1",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_fractional_cout = 24,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_fractional_division = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_m_cnt_in_src = "ph_mux_clk",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_manu_clk_sw_en = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_output_clk_frequency = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_slf_rst = "false",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_subtype = "General",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_type = "General",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_vco_div = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.pll_vcoph_div = 1,
|
||||
sys_pll_altera_pll_altera_pll_i_1098.refclk1_frequency = "0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.reference_clock_frequency = "50.0 MHz",
|
||||
sys_pll_altera_pll_altera_pll_i_1098.sim_additional_refclk_cycles_to_lock = 0;
|
||||
assign
|
||||
locked = wire_sys_pll_altera_pll_altera_pll_i_1098_locked,
|
||||
outclk_0 = wire_sys_pll_altera_pll_altera_pll_i_1098_outclk[0],
|
||||
outclk_1 = wire_sys_pll_altera_pll_altera_pll_i_1098_outclk[1];
|
||||
endmodule //sys_pll
|
||||
//synopsys translate_on
|
||||
//VALID FILE
|
||||
16
example_projects/quartus_test_prj_template_v4/program_de10.bat
Executable file
16
example_projects/quartus_test_prj_template_v4/program_de10.bat
Executable file
@ -0,0 +1,16 @@
|
||||
@echo off
|
||||
rem ------------------------------------------------------------------------------
|
||||
rem program_de10.bat
|
||||
rem Konstantin Pavlov, pavlovconst@gmail.com
|
||||
rem ------------------------------------------------------------------------------
|
||||
|
||||
echo "Listing programmers"
|
||||
C:\intelFPGA\18.0\quartus\bin64\quartus_pgm -l
|
||||
|
||||
echo "Programming FPGA"
|
||||
C:\intelFPGA\18.0\quartus\bin64\quartus_pgm -c ^
|
||||
"DE-SoC [USB-1]" -m jtag -o ^
|
||||
"P;%~dp0out\test.sof@2"
|
||||
|
||||
pause
|
||||
exit
|
||||
24
example_projects/quartus_test_prj_template_v4/src/clogb2.svh
Executable file
24
example_projects/quartus_test_prj_template_v4/src/clogb2.svh
Executable file
@ -0,0 +1,24 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// clogb2.svh
|
||||
// published as part of https://github.com/pConst/basic_verilog
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// Calculates counter/address width based on specified vector/RAM depth
|
||||
//
|
||||
// Function should be instantiated inside a module
|
||||
// But you are free to call it from anywhere by its hierarchical name
|
||||
//
|
||||
// To add clogb2 function to your module:
|
||||
// `include "clogb2.svh"
|
||||
//
|
||||
|
||||
function integer clogb2;
|
||||
input integer depth;
|
||||
|
||||
for( clogb2=0; depth>0; clogb2=clogb2+1 ) begin
|
||||
depth = depth >> 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
32
example_projects/quartus_test_prj_template_v4/src/define.svh
Executable file
32
example_projects/quartus_test_prj_template_v4/src/define.svh
Executable file
@ -0,0 +1,32 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// Quartus test project template
|
||||
// published as part of https://github.com/pConst/basic_verilog
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
// Vivado bugfix ===============================================================
|
||||
|
||||
// This is a workaround for Vivado bug of not providing errors
|
||||
// when using undeclared signals in your code
|
||||
// See https://forums.xilinx.com/t5/Synthesis/Bug-in-handling-undeclared-signals-in-instance-statement-named/td-p/300127
|
||||
//`define VIVADO_MODULE_HEADER `default_nettype none
|
||||
//`define VIVADO_MODULE_FOOTER `default_nettype wire
|
||||
|
||||
// Declare these stubs to safely reuse your Vivado modules in non-Xilinx FPGA projects
|
||||
`define VIVADO_MODULE_HEADER
|
||||
`define VIVADO_MODULE_FOOTER
|
||||
|
||||
// =============================================================================
|
||||
|
||||
`define INC( AVAL ) \
|
||||
``AVAL <= ``AVAL + 1'b1;
|
||||
|
||||
`define DEC( AVAL ) \
|
||||
``AVAL <= ``AVAL - 1'b1;
|
||||
|
||||
`define SET( AVAL ) \
|
||||
``AVAL <= 1'b1;
|
||||
|
||||
`define RESET( AVAL ) \
|
||||
``AVAL <= 1'b0;
|
||||
211
example_projects/quartus_test_prj_template_v4/src/delay.sv
Executable file
211
example_projects/quartus_test_prj_template_v4/src/delay.sv
Executable file
@ -0,0 +1,211 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// delay.v
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO -------------------------------------------------------------------------
|
||||
// Static Delay for arbitrary signal, v2
|
||||
// Another equivalent names for this module:
|
||||
// conveyor.sv
|
||||
// synchronizer.sv
|
||||
//
|
||||
// Tip for Xilinx-based implementations: Leave nrst=1'b1 and ena=1'b1 on
|
||||
// purpose of inferring Xilinx`s SRL16E/SRL32E primitives
|
||||
//
|
||||
//
|
||||
// CAUTION: delay module is widely used for synchronizing signals across clock
|
||||
// domains. When synchronizing, please exclude input data paths from timing
|
||||
// analisys manually by writing appropriate set_false_path SDC constraint
|
||||
//
|
||||
// Version 2 introduces "ALTERA_BLOCK_RAM" option to implement delays using
|
||||
// block RAM. Quartus can make shifters on block RAM aautomatically
|
||||
// using 'altshift_taps' internal module when "Auto Shift Register
|
||||
// Replacement" option is ON
|
||||
|
||||
|
||||
/* --- INSTANTIATION TEMPLATE BEGIN ---
|
||||
|
||||
delay #(
|
||||
.LENGTH( 2 ),
|
||||
.WIDTH( 1 ),
|
||||
.TYPE( "CELLS" ),
|
||||
.REGISTER_OUTPUTS( "FALSE" )
|
||||
) S1 (
|
||||
.clk( clk ),
|
||||
.nrst( 1'b1 ),
|
||||
.ena( 1'b1 ),
|
||||
|
||||
.in( ),
|
||||
.out( )
|
||||
);
|
||||
|
||||
--- INSTANTIATION TEMPLATE END ---*/
|
||||
|
||||
|
||||
module delay #( parameter
|
||||
LENGTH = 2, // delay/synchronizer chain length
|
||||
WIDTH = 1, // signal width
|
||||
|
||||
TYPE = "CELLS", // "ALTERA_BLOCK_RAM" infers block ram fifo
|
||||
// "ALTERA_TAPS" infers altshift_taps
|
||||
// all other values infer registers
|
||||
|
||||
REGISTER_OUTPUTS = "FALSE", // for block RAM implementations: "TRUE" means that
|
||||
// last delay stage will be implemented
|
||||
// by means of cell registers to improve timing
|
||||
// all other values infer block RAMs only
|
||||
|
||||
CNTR_W = $clog2(LENGTH)
|
||||
)(
|
||||
input clk,
|
||||
input nrst,
|
||||
input ena,
|
||||
|
||||
input [WIDTH-1:0] in,
|
||||
output [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
generate
|
||||
|
||||
if ( LENGTH == 0 ) begin
|
||||
|
||||
assign out[WIDTH-1:0] = in[WIDTH-1:0];
|
||||
|
||||
end else if( LENGTH == 1 ) begin
|
||||
|
||||
logic [WIDTH-1:0] data = '0;
|
||||
always_ff @(posedge clk) begin
|
||||
if( ~nrst ) begin
|
||||
data[WIDTH-1:0] <= '0;
|
||||
end else if( ena ) begin
|
||||
data[WIDTH-1:0] <= in[WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
assign out[WIDTH-1:0] = data[WIDTH-1:0];
|
||||
|
||||
end else begin
|
||||
if( TYPE=="ALTERA_BLOCK_RAM" && LENGTH>=3 ) begin
|
||||
|
||||
logic [WIDTH-1:0] fifo_out;
|
||||
logic full;
|
||||
logic [CNTR_W-1:0] usedw;
|
||||
|
||||
logic fifo_out_ena;
|
||||
if( REGISTER_OUTPUTS=="TRUE" ) begin
|
||||
assign fifo_out_ena = (usedw[CNTR_W-1:0] == LENGTH-1);
|
||||
end else begin
|
||||
assign fifo_out_ena = full;
|
||||
end
|
||||
|
||||
scfifo #(
|
||||
.LPM_WIDTH( WIDTH ),
|
||||
.LPM_NUMWORDS( LENGTH ), // must be at least 4
|
||||
.LPM_WIDTHU( CNTR_W ),
|
||||
.LPM_SHOWAHEAD( "ON" ),
|
||||
.UNDERFLOW_CHECKING( "ON" ),
|
||||
.OVERFLOW_CHECKING( "ON" ),
|
||||
.ENABLE_ECC( "FALSE" ),
|
||||
.ALLOW_RWCYCLE_WHEN_FULL( "ON" ),
|
||||
.USE_EAB( "ON" )
|
||||
) internal_fifo (
|
||||
.clock( clk ),
|
||||
.aclr( 1'b0 ),
|
||||
.sclr( ~nrst ),
|
||||
|
||||
.data( in[WIDTH-1:0] ),
|
||||
.wrreq( ena ),
|
||||
.rdreq( ena && fifo_out_ena ),
|
||||
|
||||
.q( fifo_out[WIDTH-1:0] ),
|
||||
.empty( ),
|
||||
.full( full ),
|
||||
.almost_full( ),
|
||||
.almost_empty( ),
|
||||
.usedw( usedw[CNTR_W-1:0] ),
|
||||
.eccstatus( )
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0] reg_out = '0;
|
||||
always_ff @(posedge clk) begin
|
||||
if( ~nrst ) begin
|
||||
reg_out[WIDTH-1:0] <= '0;
|
||||
end else if( ena && fifo_out_ena ) begin
|
||||
reg_out[WIDTH-1:0] <= fifo_out[WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
if( REGISTER_OUTPUTS=="TRUE" ) begin
|
||||
assign out[WIDTH-1:0] = reg_out[WIDTH-1:0];
|
||||
end else begin
|
||||
// avoiding first word fall-through
|
||||
assign out[WIDTH-1:0] = (fifo_out_ena)?(fifo_out[WIDTH-1:0]):('0);
|
||||
end
|
||||
|
||||
end else if( TYPE=="ALTERA_TAPS" && LENGTH>=2 ) begin
|
||||
|
||||
logic [WIDTH-1:0] fifo_out;
|
||||
logic [CNTR_W-1:0] delay_cntr = CNTR_W'(LENGTH-1);
|
||||
|
||||
logic fifo_out_ena;
|
||||
assign fifo_out_ena = (delay_cntr[CNTR_W-1:0] == '0);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if( ~nrst ) begin
|
||||
delay_cntr[CNTR_W-1:0] <= CNTR_W'(LENGTH-1);
|
||||
end else if( ena && ~fifo_out_ena ) begin
|
||||
delay_cntr[CNTR_W-1:0] <= delay_cntr[CNTR_W-1:0] - 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
altshift_taps #(
|
||||
.intended_device_family( "Cyclone V" ),
|
||||
.lpm_hint( "RAM_BLOCK_TYPE=AUTO" ),
|
||||
.lpm_type( "altshift_taps" ),
|
||||
.number_of_taps( 1 ),
|
||||
.tap_distance( (REGISTER_OUTPUTS=="TRUE")?(LENGTH-1):(LENGTH) ), // min. of 3
|
||||
.width( WIDTH )
|
||||
) internal_taps (
|
||||
//.aclr( 1'b0 ),
|
||||
//.sclr( ~nrst ),
|
||||
.clock( clk ),
|
||||
.clken( ena ),
|
||||
.shiftin( in[WIDTH-1:0] ),
|
||||
.shiftout( fifo_out[WIDTH-1:0] )
|
||||
);
|
||||
|
||||
if( REGISTER_OUTPUTS=="TRUE" ) begin
|
||||
logic [WIDTH-1:0] reg_out = '0;
|
||||
always_ff @(posedge clk) begin
|
||||
if( ~nrst ) begin
|
||||
reg_out[WIDTH-1:0] <= '0;
|
||||
end else if( ena && fifo_out_ena ) begin
|
||||
reg_out[WIDTH-1:0] <= fifo_out[WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
assign out[WIDTH-1:0] = reg_out[WIDTH-1:0];
|
||||
end else begin
|
||||
assign out[WIDTH-1:0] = fifo_out[WIDTH-1:0];
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
logic [LENGTH:1][WIDTH-1:0] data = '0;
|
||||
always_ff @(posedge clk) begin
|
||||
integer i;
|
||||
if( ~nrst ) begin
|
||||
data <= '0;
|
||||
end else if( ena ) begin
|
||||
for(i=LENGTH-1; i>0; i--) begin
|
||||
data[i+1][WIDTH-1:0] <= data[i][WIDTH-1:0];
|
||||
end
|
||||
data[1][WIDTH-1:0] <= in[WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
assign out[WIDTH-1:0] = data[LENGTH][WIDTH-1:0];
|
||||
|
||||
end // if TYPE
|
||||
end // if LENGTH
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
100
example_projects/quartus_test_prj_template_v4/src/edge_detect.sv
Executable file
100
example_projects/quartus_test_prj_template_v4/src/edge_detect.sv
Executable file
@ -0,0 +1,100 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// edge_detect.sv
|
||||
// published as part of https://github.com/pConst/basic_verilog
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// Edge detector, ver.4
|
||||
//
|
||||
// (new!) Added WIDTH parameter to simplify instantiating arrays of edge detectors
|
||||
// (new!) Made reset to be asynchronous
|
||||
//
|
||||
// Added parameter to select combinational implementation (zero clocks delay)
|
||||
// or registered implementation (one clocks delay)
|
||||
//
|
||||
// In case when "in" port has toggle rate 100% (changes every clock period)
|
||||
// "rising" and "falling" outputs will completely replicate input
|
||||
// "both" output will be always active in this case
|
||||
//
|
||||
|
||||
|
||||
/* --- INSTANTIATION TEMPLATE BEGIN ---
|
||||
|
||||
edge_detect #(
|
||||
.WIDTH( 32 ),
|
||||
.REGISTER_OUTPUTS( 1'b1 )
|
||||
) in_ed (
|
||||
.clk( clk ),
|
||||
.anrst( 1'b1 ),
|
||||
.in( in[31:0] ),
|
||||
.rising( in_rise[31:0] ),
|
||||
.falling( ),
|
||||
.both( )
|
||||
);
|
||||
|
||||
--- INSTANTIATION TEMPLATE END ---*/
|
||||
|
||||
|
||||
module edge_detect #( parameter
|
||||
bit [7:0] WIDTH = 1, // signal width
|
||||
bit [0:0] REGISTER_OUTPUTS = 1'b0 // 0 - comb. implementation (default)
|
||||
// 1 - registered implementation
|
||||
)(
|
||||
input clk,
|
||||
input anrst,
|
||||
|
||||
input [WIDTH-1:0] in,
|
||||
output logic [WIDTH-1:0] rising,
|
||||
output logic [WIDTH-1:0] falling,
|
||||
output logic [WIDTH-1:0] both
|
||||
);
|
||||
|
||||
// data delay line
|
||||
logic [WIDTH-1:0] in_d = '0;
|
||||
always_ff @(posedge clk or negedge anrst) begin
|
||||
if ( ~anrst ) begin
|
||||
in_d[WIDTH-1:0] <= '0;
|
||||
end else begin
|
||||
in_d[WIDTH-1:0] <= in[WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
logic [WIDTH-1:0] rising_comb;
|
||||
logic [WIDTH-1:0] falling_comb;
|
||||
logic [WIDTH-1:0] both_comb;
|
||||
always_comb begin
|
||||
rising_comb[WIDTH-1:0] = {WIDTH{anrst}} & (in[WIDTH-1:0] & ~in_d[WIDTH-1:0]);
|
||||
falling_comb[WIDTH-1:0] = {WIDTH{anrst}} & (~in[WIDTH-1:0] & in_d[WIDTH-1:0]);
|
||||
both_comb[WIDTH-1:0] = {WIDTH{anrst}} & (rising_comb[WIDTH-1:0] | falling_comb[WIDTH-1:0]);
|
||||
end
|
||||
|
||||
generate
|
||||
if( REGISTER_OUTPUTS==1'b0 ) begin
|
||||
|
||||
// combinational outputs, no delay
|
||||
always_comb begin
|
||||
rising[WIDTH-1:0] = rising_comb[WIDTH-1:0];
|
||||
falling[WIDTH-1:0] = falling_comb[WIDTH-1:0];
|
||||
both[WIDTH-1:0] = both_comb[WIDTH-1:0];
|
||||
end // always
|
||||
|
||||
end else begin
|
||||
|
||||
// registered outputs, 1 cycle delay
|
||||
always_ff @(posedge clk or negedge anrst) begin
|
||||
if( ~anrst ) begin
|
||||
rising[WIDTH-1:0] <= '0;
|
||||
falling[WIDTH-1:0] <= '0;
|
||||
both[WIDTH-1:0] <= '0;
|
||||
end else begin
|
||||
rising[WIDTH-1:0] <= rising_comb[WIDTH-1:0];
|
||||
falling[WIDTH-1:0] <= falling_comb[WIDTH-1:0];
|
||||
both[WIDTH-1:0] <= both_comb[WIDTH-1:0];
|
||||
end // always
|
||||
end // if
|
||||
|
||||
end // end else
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
13
example_projects/quartus_test_prj_template_v4/src/main.sdc
Normal file
13
example_projects/quartus_test_prj_template_v4/src/main.sdc
Normal file
@ -0,0 +1,13 @@
|
||||
#------------------------------------------------------------------------------
|
||||
# Quartus test project template
|
||||
# published as part of https://github.com/pConst/basic_verilog
|
||||
# Konstantin Pavlov, pavlovconst@gmail.com
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
# main reference clock, 500 MHz
|
||||
create_clock -period 2.000 -waveform { 0.000 1.000 } [get_ports {FPGA_CLK1_50}]
|
||||
create_clock -period 2.000 -waveform { 0.000 1.000 } [get_ports {FPGA_CLK2_50}]
|
||||
create_clock -period 2.000 -waveform { 0.000 1.000 } [get_ports {FPGA_CLK3_50}]
|
||||
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
192
example_projects/quartus_test_prj_template_v4/src/main.sv
Normal file
192
example_projects/quartus_test_prj_template_v4/src/main.sv
Normal file
@ -0,0 +1,192 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// Quartus test project template
|
||||
// published as part of https://github.com/pConst/basic_verilog
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// Quartus test project template, v4
|
||||
// Compatible with DE10-Nano board
|
||||
//
|
||||
// - use this as a boilerplate project for fast prototyping
|
||||
// - inputs and outputs are registered to allow valid timequest output
|
||||
// even if your custom logic/IPs have combinational outputs
|
||||
// - SDC constraint file assigns clk to 500MHz to force fitter to synthesize
|
||||
// the fastest possible circuit
|
||||
//
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
`include "define.svh"
|
||||
|
||||
|
||||
`define WIDTH 32
|
||||
|
||||
module main(
|
||||
|
||||
input FPGA_CLK1_50,
|
||||
input FPGA_CLK2_50,
|
||||
input FPGA_CLK3_50,
|
||||
|
||||
// ADC
|
||||
input ADC_CONVST,
|
||||
input ADC_SCK,
|
||||
input ADC_SDI,
|
||||
input ADC_SDO,
|
||||
|
||||
// ARDUINO
|
||||
input ARDUINO_RESET_N,
|
||||
input [15:0] ARDUINO_IO,
|
||||
|
||||
// HDMI
|
||||
input [23:0] HDMI_TX_D,
|
||||
input HDMI_I2C_SCL,
|
||||
input HDMI_I2C_SDA,
|
||||
input HDMI_I2S,
|
||||
input HDMI_LRCLK,
|
||||
input HDMI_MCLK,
|
||||
input HDMI_SCLK,
|
||||
input HDMI_TX_CLK,
|
||||
input HDMI_TX_DE,
|
||||
input HDMI_TX_HS,
|
||||
input HDMI_TX_INT,
|
||||
input HDMI_TX_VS,
|
||||
|
||||
// GPIO
|
||||
input [35:0] GPIO_0,
|
||||
output [35:0] GPIO_1,
|
||||
input [1:0] KEY,
|
||||
input [3:0] SW,
|
||||
output [7:0] LED,
|
||||
|
||||
// virtual pins
|
||||
input [`WIDTH-1:0] in_data,
|
||||
input [`WIDTH-1:0] in_datb,
|
||||
output logic [`WIDTH-1:0] out_data = '0
|
||||
);
|
||||
|
||||
|
||||
// clocks ======================================================================
|
||||
|
||||
logic sys_pll_locked; // asyn
|
||||
logic clk125;
|
||||
logic clk500;
|
||||
|
||||
logic nrst;
|
||||
|
||||
sys_pll sys_pll_b (
|
||||
.refclk( FPGA_CLK1_50 ),
|
||||
.rst( 1'b0 ),
|
||||
.outclk_0( clk125 ),
|
||||
.outclk_1( clk500 ),
|
||||
.locked( sys_pll_locked )
|
||||
);
|
||||
|
||||
logic [31:0] div_clk125;
|
||||
clk_divider #(
|
||||
.WIDTH( 32 )
|
||||
) cd_125 (
|
||||
.clk( clk125 ),
|
||||
.nrst( nrst ),
|
||||
.ena( 1'b1 ),
|
||||
.out( div_clk125[31:0] )
|
||||
);
|
||||
|
||||
logic [31:0] div_clk500;
|
||||
clk_divider #(
|
||||
.WIDTH( 32 )
|
||||
) cd_500 (
|
||||
.clk( clk500 ),
|
||||
.nrst( nrst ),
|
||||
.ena( 1'b1 ),
|
||||
.out( div_clk500[31:0] )
|
||||
);
|
||||
|
||||
assign LED[7] = div_clk125[25];
|
||||
|
||||
// nrst ========================================================================
|
||||
logic [3:0] sw_s;
|
||||
logic [1:0] key_s;
|
||||
|
||||
always_ff @(posedge clk125) begin
|
||||
nrst <= ~key_s[0]; // external reset
|
||||
end
|
||||
|
||||
assign LED[6] = ~nrst;
|
||||
|
||||
// buttons =====================================================================
|
||||
|
||||
delay #(
|
||||
.LENGTH( 2 ),
|
||||
.WIDTH( 6 )
|
||||
) sw_SYNC_ATTR (
|
||||
.clk( clk125 ),
|
||||
.nrst( 1'b1 ),
|
||||
.ena( 1'b1 ),
|
||||
.in( {SW[3:0], KEY[1:0]} ),
|
||||
.out( {sw_s[3:0], key_s[1:0]} )
|
||||
);
|
||||
|
||||
logic [3:0] sw_s_rise;
|
||||
logic [1:0] key_s_rise;
|
||||
|
||||
edge_detect #(
|
||||
.WIDTH( 6 )
|
||||
) sw_s_ed (
|
||||
.clk( clk125 ),
|
||||
.anrst( nrst ),
|
||||
.in( {sw_s[3:0], key_s[1:0]} ),
|
||||
.rising( {sw_s_rise[3:0], key_s_rise[1:0]} ),
|
||||
.falling( ),
|
||||
.both( )
|
||||
);
|
||||
|
||||
// =============================================================================
|
||||
|
||||
// input registers
|
||||
logic [`WIDTH-1:0] in_data_reg = 0;
|
||||
always_ff @(posedge clk500) begin
|
||||
if( ~nrst ) begin
|
||||
in_data_reg[`WIDTH-1:0] <= '0;
|
||||
end else begin
|
||||
in_data_reg[`WIDTH-1:0] <= in_data[`WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
// place your test logic here ==================================================
|
||||
|
||||
logic [`WIDTH-1:0] out_data_comb = 0;
|
||||
always_comb begin
|
||||
out_data_comb[`WIDTH-1:0] <= in_data_reg[`WIDTH-1:0] ^ div_clk500[31:0];
|
||||
end
|
||||
|
||||
// output registers
|
||||
always_ff @(posedge clk500) begin
|
||||
if( ~nrst ) begin
|
||||
out_data[`WIDTH-1:0] <= '0;
|
||||
end else begin
|
||||
out_data[`WIDTH-1:0] <= out_data_comb[`WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
// =============================================================================
|
||||
|
||||
/*logic [`WIDTH-1:0] in_datc;
|
||||
logic [`WIDTH-1:0] in_datd;
|
||||
logic [`WIDTH-1:0] out_datc;
|
||||
assign out_datc[`WIDTH-1:0] = in_datc[`WIDTH-1:0] | in_datd[`WIDTH-1:0];
|
||||
|
||||
jtag_io jtag_io_b (
|
||||
.clk_clk( clk125 ),
|
||||
.reset_reset_n( nrst ),
|
||||
.out0_export( in_datc[`WIDTH-1:0] ),
|
||||
.out1_export( in_datd[`WIDTH-1:0] ),
|
||||
.in0_export( div_clk125[31:0] ),
|
||||
.in1_export( out_datc[`WIDTH-1:0] )
|
||||
);
|
||||
*/
|
||||
|
||||
`include "clogb2.svh"
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1 +1 @@
|
||||
PROJECT_REVISION = "test"
|
||||
PROJECT_REVISION = "test"
|
||||
490
example_projects/quartus_test_prj_template_v4/test.qsf
Normal file
490
example_projects/quartus_test_prj_template_v4/test.qsf
Normal file
@ -0,0 +1,490 @@
|
||||
#------------------------------------------------------------------------------
|
||||
# Quartus test project template
|
||||
# published as part of https://github.com/pConst/basic_verilog
|
||||
# Konstantin Pavlov, pavlovconst@gmail.com
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name DEVICE 5CSEBA6U23I7
|
||||
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY main
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
||||
|
||||
|
||||
|
||||
# ADC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
|
||||
|
||||
# ARDUINO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
|
||||
|
||||
# FPGA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
|
||||
|
||||
# GPIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
|
||||
|
||||
# HDMI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
|
||||
|
||||
# HPS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RZQ
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
|
||||
|
||||
# KEY
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
|
||||
|
||||
# LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
|
||||
# SW
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_location_assignment PIN_U9 -to ADC_CONVST
|
||||
set_location_assignment PIN_V10 -to ADC_SCK
|
||||
set_location_assignment PIN_AC4 -to ADC_SDI
|
||||
set_location_assignment PIN_AD4 -to ADC_SDO
|
||||
set_location_assignment PIN_AG13 -to ARDUINO_IO[0]
|
||||
set_location_assignment PIN_AF13 -to ARDUINO_IO[1]
|
||||
set_location_assignment PIN_AG10 -to ARDUINO_IO[2]
|
||||
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
|
||||
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
|
||||
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
|
||||
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
|
||||
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
|
||||
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
|
||||
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
|
||||
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
|
||||
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
|
||||
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
|
||||
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
|
||||
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
|
||||
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
|
||||
set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
|
||||
set_location_assignment PIN_V11 -to FPGA_CLK1_50
|
||||
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
|
||||
set_location_assignment PIN_E11 -to FPGA_CLK3_50
|
||||
set_location_assignment PIN_V12 -to GPIO_0[0]
|
||||
set_location_assignment PIN_E8 -to GPIO_0[1]
|
||||
set_location_assignment PIN_W12 -to GPIO_0[2]
|
||||
set_location_assignment PIN_D11 -to GPIO_0[3]
|
||||
set_location_assignment PIN_D8 -to GPIO_0[4]
|
||||
set_location_assignment PIN_AH13 -to GPIO_0[5]
|
||||
set_location_assignment PIN_AF7 -to GPIO_0[6]
|
||||
set_location_assignment PIN_AH14 -to GPIO_0[7]
|
||||
set_location_assignment PIN_AF4 -to GPIO_0[8]
|
||||
set_location_assignment PIN_AH3 -to GPIO_0[9]
|
||||
set_location_assignment PIN_AD5 -to GPIO_0[10]
|
||||
set_location_assignment PIN_AG14 -to GPIO_0[11]
|
||||
set_location_assignment PIN_AE23 -to GPIO_0[12]
|
||||
set_location_assignment PIN_AE6 -to GPIO_0[13]
|
||||
set_location_assignment PIN_AD23 -to GPIO_0[14]
|
||||
set_location_assignment PIN_AE24 -to GPIO_0[15]
|
||||
set_location_assignment PIN_D12 -to GPIO_0[16]
|
||||
set_location_assignment PIN_AD20 -to GPIO_0[17]
|
||||
set_location_assignment PIN_C12 -to GPIO_0[18]
|
||||
set_location_assignment PIN_AD17 -to GPIO_0[19]
|
||||
set_location_assignment PIN_AC23 -to GPIO_0[20]
|
||||
set_location_assignment PIN_AC22 -to GPIO_0[21]
|
||||
set_location_assignment PIN_Y19 -to GPIO_0[22]
|
||||
set_location_assignment PIN_AB23 -to GPIO_0[23]
|
||||
set_location_assignment PIN_AA19 -to GPIO_0[24]
|
||||
set_location_assignment PIN_W11 -to GPIO_0[25]
|
||||
set_location_assignment PIN_AA18 -to GPIO_0[26]
|
||||
set_location_assignment PIN_W14 -to GPIO_0[27]
|
||||
set_location_assignment PIN_Y18 -to GPIO_0[28]
|
||||
set_location_assignment PIN_Y17 -to GPIO_0[29]
|
||||
set_location_assignment PIN_AB25 -to GPIO_0[30]
|
||||
set_location_assignment PIN_AB26 -to GPIO_0[31]
|
||||
set_location_assignment PIN_Y11 -to GPIO_0[32]
|
||||
set_location_assignment PIN_AA26 -to GPIO_0[33]
|
||||
set_location_assignment PIN_AA13 -to GPIO_0[34]
|
||||
set_location_assignment PIN_AA11 -to GPIO_0[35]
|
||||
set_location_assignment PIN_Y15 -to GPIO_1[0]
|
||||
set_location_assignment PIN_AC24 -to GPIO_1[1]
|
||||
set_location_assignment PIN_AA15 -to GPIO_1[2]
|
||||
set_location_assignment PIN_AD26 -to GPIO_1[3]
|
||||
set_location_assignment PIN_AG28 -to GPIO_1[4]
|
||||
set_location_assignment PIN_AF28 -to GPIO_1[5]
|
||||
set_location_assignment PIN_AE25 -to GPIO_1[6]
|
||||
set_location_assignment PIN_AF27 -to GPIO_1[7]
|
||||
set_location_assignment PIN_AG26 -to GPIO_1[8]
|
||||
set_location_assignment PIN_AH27 -to GPIO_1[9]
|
||||
set_location_assignment PIN_AG25 -to GPIO_1[10]
|
||||
set_location_assignment PIN_AH26 -to GPIO_1[11]
|
||||
set_location_assignment PIN_AH24 -to GPIO_1[12]
|
||||
set_location_assignment PIN_AF25 -to GPIO_1[13]
|
||||
set_location_assignment PIN_AG23 -to GPIO_1[14]
|
||||
set_location_assignment PIN_AF23 -to GPIO_1[15]
|
||||
set_location_assignment PIN_AG24 -to GPIO_1[16]
|
||||
set_location_assignment PIN_AH22 -to GPIO_1[17]
|
||||
set_location_assignment PIN_AH21 -to GPIO_1[18]
|
||||
set_location_assignment PIN_AG21 -to GPIO_1[19]
|
||||
set_location_assignment PIN_AH23 -to GPIO_1[20]
|
||||
set_location_assignment PIN_AA20 -to GPIO_1[21]
|
||||
set_location_assignment PIN_AF22 -to GPIO_1[22]
|
||||
set_location_assignment PIN_AE22 -to GPIO_1[23]
|
||||
set_location_assignment PIN_AG20 -to GPIO_1[24]
|
||||
set_location_assignment PIN_AF21 -to GPIO_1[25]
|
||||
set_location_assignment PIN_AG19 -to GPIO_1[26]
|
||||
set_location_assignment PIN_AH19 -to GPIO_1[27]
|
||||
set_location_assignment PIN_AG18 -to GPIO_1[28]
|
||||
set_location_assignment PIN_AH18 -to GPIO_1[29]
|
||||
set_location_assignment PIN_AF18 -to GPIO_1[30]
|
||||
set_location_assignment PIN_AF20 -to GPIO_1[31]
|
||||
set_location_assignment PIN_AG15 -to GPIO_1[32]
|
||||
set_location_assignment PIN_AE20 -to GPIO_1[33]
|
||||
set_location_assignment PIN_AE19 -to GPIO_1[34]
|
||||
set_location_assignment PIN_AE17 -to GPIO_1[35]
|
||||
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
|
||||
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
|
||||
set_location_assignment PIN_T13 -to HDMI_I2S
|
||||
set_location_assignment PIN_T11 -to HDMI_LRCLK
|
||||
set_location_assignment PIN_U11 -to HDMI_MCLK
|
||||
set_location_assignment PIN_T12 -to HDMI_SCLK
|
||||
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
|
||||
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
|
||||
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
|
||||
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
|
||||
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
|
||||
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
|
||||
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
|
||||
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
|
||||
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
|
||||
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
|
||||
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
|
||||
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
|
||||
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
|
||||
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
|
||||
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
|
||||
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
|
||||
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
|
||||
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
|
||||
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
|
||||
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
|
||||
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
|
||||
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
|
||||
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
|
||||
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
|
||||
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
|
||||
set_location_assignment PIN_AD19 -to HDMI_TX_DE
|
||||
set_location_assignment PIN_T8 -to HDMI_TX_HS
|
||||
set_location_assignment PIN_AF11 -to HDMI_TX_INT
|
||||
set_location_assignment PIN_V13 -to HDMI_TX_VS
|
||||
|
||||
set_location_assignment PIN_AH17 -to KEY[0]
|
||||
set_location_assignment PIN_AH16 -to KEY[1]
|
||||
set_location_assignment PIN_W15 -to LED[0]
|
||||
set_location_assignment PIN_AA24 -to LED[1]
|
||||
set_location_assignment PIN_V16 -to LED[2]
|
||||
set_location_assignment PIN_V15 -to LED[3]
|
||||
set_location_assignment PIN_AF26 -to LED[4]
|
||||
set_location_assignment PIN_AE26 -to LED[5]
|
||||
set_location_assignment PIN_Y16 -to LED[6]
|
||||
set_location_assignment PIN_AA23 -to LED[7]
|
||||
set_location_assignment PIN_Y24 -to SW[0]
|
||||
set_location_assignment PIN_W24 -to SW[1]
|
||||
set_location_assignment PIN_W21 -to SW[2]
|
||||
set_location_assignment PIN_W20 -to SW[3]
|
||||
|
||||
set_instance_assignment -name VIRTUAL_PIN ON -to in_data[*]
|
||||
set_instance_assignment -name VIRTUAL_PIN ON -to in_datb[*]
|
||||
set_instance_assignment -name VIRTUAL_PIN ON -to out_data[*]
|
||||
|
||||
# fastio =======================================================================
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to *
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to *
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to *
|
||||
|
||||
# files ========================================================================
|
||||
set_global_assignment -name QIP_FILE ./ip/jtag_io/synthesis/jtag_io.qip
|
||||
set_global_assignment -name QIP_FILE ./ip/sys_pll/sys_pll.qip
|
||||
set_global_assignment -name SIP_FILE ./ip/sys_pll/sys_pll.sip
|
||||
set_global_assignment -name SDC_FILE ./src/main.sdc
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ./src/clk_divider.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ./src/delay.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ./src/clogb2.svh
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ./src/edge_detect.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ./src/main.sv
|
||||
|
||||
|
||||
# other ========================================================================
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
|
||||
|
||||
# signaltap ====================================================================
|
||||
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE debug/in_out_data.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE debug/in_out_data.stp
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Binary file not shown.
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Reference in New Issue
Block a user