From 343abf82f72d27c74537fe57b40635535cc05fb3 Mon Sep 17 00:00:00 2001
From: Konstantin Pavlov <pavlovconst@gmail.com>
Date: Sun, 20 Feb 2022 05:50:35 +0300
Subject: [PATCH] Added fifo initialization from file

---
 fifo_single_clock_ram.sv                  |  75 +--------------
 pos2bin.sv                                |   8 +-
 true_dual_port_write_first_2_clock_ram.sv | 110 ++++++++++++++++++++++
 3 files changed, 118 insertions(+), 75 deletions(-)
 create mode 100755 true_dual_port_write_first_2_clock_ram.sv

diff --git a/fifo_single_clock_ram.sv b/fifo_single_clock_ram.sv
index f47d2b0..8a00a0e 100755
--- a/fifo_single_clock_ram.sv
+++ b/fifo_single_clock_ram.sv
@@ -15,6 +15,7 @@
 //  - configurable depth and data width
 //  - only "normal" mode is supported here, no FWFT mode
 //  - protected against overflow and underflow
+//  - provides fifo contents initialization (!)
 //
 
 
@@ -49,7 +50,8 @@ module fifo_single_clock_ram #( parameter
   DEPTH_W = $clog2(DEPTH)+1,      // elements counter width, extra bit to store
                                   // "fifo full" state, see cnt[] variable comments
 
-  DATA_W = 32                     // data field width
+  DATA_W = 32,                    // data field width
+  INIT_FILE = ""
 )(
 
   input clk,
@@ -87,7 +89,7 @@ assign r_req_f = r_req && ~empty;
 true_dual_port_write_first_2_clock_ram #(
   .RAM_WIDTH( DATA_W ),
   .RAM_DEPTH( DEPTH ),
-  .INIT_FILE( "" )
+  .INIT_FILE( INIT_FILE )
 ) data_ram (
   .clka( clk ),
   .addra( w_ptr[DEPTH_W-1:0] ),
@@ -152,72 +154,3 @@ end
 
 endmodule
 
-
-
-module true_dual_port_write_first_2_clock_ram #( parameter
-  RAM_WIDTH = 16,
-  RAM_DEPTH = 8,
-  INIT_FILE = ""
-)(
-  input clka,
-  input [clogb2(RAM_DEPTH-1)-1:0] addra,
-  input ena,
-  input wea,
-  input [RAM_WIDTH-1:0] dina,
-  output [RAM_WIDTH-1:0] douta,
-
-  input clkb,
-  input [clogb2(RAM_DEPTH-1)-1:0] addrb,
-  input enb,
-  input web,
-  input [RAM_WIDTH-1:0] dinb,
-  output [RAM_WIDTH-1:0] doutb
-);
-
-  reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
-  reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
-  reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
-
-  // either initializes the memory values to a specified file or to all zeros
-  //   to match hardware
-  generate
-    if (INIT_FILE != "") begin: use_init_file
-      initial
-        $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
-    end else begin: init_bram_to_zero
-      integer ram_index;
-      initial
-        for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
-          BRAM[ram_index] = {RAM_WIDTH{1'b0}};
-    end
-  endgenerate
-
-  always @(posedge clka)
-    if (ena)
-      if (wea) begin
-        BRAM[addra] <= dina;
-        ram_data_a <= dina;
-      end else
-        ram_data_a <= BRAM[addra];
-
-  always @(posedge clkb)
-    if (enb)
-      if (web) begin
-        BRAM[addrb] <= dinb;
-        ram_data_b <= dinb;
-      end else
-        ram_data_b <= BRAM[addrb];
-
-  // no output register
-  assign douta = ram_data_a;
-  assign doutb = ram_data_b;
-
-  // calculates the address width based on specified RAM depth
-  function integer clogb2;
-    input integer depth;
-      for (clogb2=0; depth>0; clogb2=clogb2+1)
-        depth = depth >> 1;
-  endfunction
-
-endmodule
-
diff --git a/pos2bin.sv b/pos2bin.sv
index 8bc6acf..c5fa8d0 100755
--- a/pos2bin.sv
+++ b/pos2bin.sv
@@ -45,13 +45,13 @@ integer i;
 
 logic found_hot;
 always_comb begin
-  err_multi_hot=0;
-  bin[(BIN_WIDTH-1):0]=0;
+  err_multi_hot = 0;
+  bin[(BIN_WIDTH-1):0] = 0;
   found_hot = 0;
-  for (i = 0; i < POS_WIDTH ; i++) begin
+  for (i=0; i<POS_WIDTH; i++) begin
 
     if ( ~found_hot && pos[i] ) begin
-      bin[(BIN_WIDTH-1):0] = i;
+      bin[(BIN_WIDTH-1):0] = i[(BIN_WIDTH-1):0];
     end
 
     if ( found_hot && pos[i] ) begin
diff --git a/true_dual_port_write_first_2_clock_ram.sv b/true_dual_port_write_first_2_clock_ram.sv
new file mode 100755
index 0000000..d74f1d7
--- /dev/null
+++ b/true_dual_port_write_first_2_clock_ram.sv
@@ -0,0 +1,110 @@
+//------------------------------------------------------------------------------
+// true_dual_port_write_first_2_clock_ram.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  This is originally a Vivado template for block RAM with some minor edits
+//  Also tested for Quartus IDE to automatically infer block memories
+//
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+true_dual_port_write_first_2_clock_ram #(
+  .RAM_WIDTH( DATA_W ),
+  .RAM_DEPTH( DEPTH ),
+  .INIT_FILE( "" )
+) bram (
+  .clka( w_clk ),
+  .addra( w_ptr[DEPTH_W-1:0] ),
+  .ena( w_req ),
+  .wea( 1'b1 ),
+  .dina( w_data[DATA_W-1:0] ),
+  .douta(  ),
+
+  .clkb( r_clk ),
+  .addrb( r_ptr[DEPTH_W-1:0] ),
+  .enb( r_req ),
+  .web( 1'b0 ),
+  .dinb( '0 ),
+  .doutb( r_data[DATA_W-1:0] )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module true_dual_port_write_first_2_clock_ram #( parameter
+  RAM_WIDTH = 16,
+  RAM_DEPTH = 8,
+  INIT_FILE = ""
+)(
+  input clka,
+  input [clogb2(RAM_DEPTH-1)-1:0] addra,
+  input ena,
+  input wea,
+  input [RAM_WIDTH-1:0] dina,
+  output [RAM_WIDTH-1:0] douta,
+
+  input clkb,
+  input [clogb2(RAM_DEPTH-1)-1:0] addrb,
+  input enb,
+  input web,
+  input [RAM_WIDTH-1:0] dinb,
+  output [RAM_WIDTH-1:0] doutb
+);
+
+  logic [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
+  logic [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
+  logic [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
+
+  // either initializes the memory values to a specified file or to all zeros
+  generate
+    if (INIT_FILE != "") begin: use_init_file
+      initial
+        $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
+    end else begin: init_bram_to_zero
+      integer ram_index;
+      initial begin
+        for (ram_index=0; ram_index<RAM_DEPTH; ram_index=ram_index+1 ) begin
+          BRAM[ram_index] = {RAM_WIDTH{1'b0}};
+        end
+      end
+    end
+  endgenerate
+
+  always @(posedge clka) begin
+    if (ena) begin
+      if (wea) begin
+        BRAM[addra] <= dina;
+        ram_data_a <= dina;
+      end else begin
+        ram_data_a <= BRAM[addra];
+      end
+    end
+  end
+
+  always @(posedge clkb) begin
+    if (enb) begin
+      if (web) begin
+        BRAM[addrb] <= dinb;
+        ram_data_b <= dinb;
+      end else begin
+        ram_data_b <= BRAM[addrb];
+      end
+    end
+  end
+
+  // no output register
+  assign douta = ram_data_a;
+  assign doutb = ram_data_b;
+
+  // calculates the address width based on specified RAM depth
+  function integer clogb2;
+    input integer depth;
+      for (clogb2=0; depth>0; clogb2=clogb2+1)
+        depth = depth >> 1;
+  endfunction
+
+endmodule
+