Added fast counter sources

fast_counter.sv

@@ -0,0 +1,109 @@
+//------------------------------------------------------------------------------
+// fast_counter.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//
+// - This is a synthetic fast counter which appears faster than a standard one
+//   generated from pure Verilog code
+//
+// - My tests show that it is on average 30MHz faster in direct comparisons for
+//   counters from 5 to 32 bit widths in Cyclone V
+//
+// - Use this counter only when counter performance is your last and ultimate
+//   resort to conquer timings. Fast counter is area-unefficient thing.
+//
+// - fast_counter_iterative_test project in the repo shows fast counter`s advantage
+//   https://github.com/pConst/basic_verilog/fast_counter_iterative_test/
+//
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+fast_counter #(
+  .WIDTH( 14 )
+) fc (
+  .clk( clk ),
+
+  .set(  ),           // highest priority operation, use it like a reset also
+  .set_val(  ),
+  .dec(  ),
+
+  .q(  ),
+  .q_is_zero(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module fast_counter #( parameter
+  WIDTH = 8
+)(
+  input clk,
+
+  input set,
+  input [WIDTH-1:0] set_val,
+
+  input dec,
+
+  output [WIDTH-1:0] q,
+  output q_is_zero
+);
+
+
+const logic [5:0][15:0] lsb_bits_init = { 16'b0000000000000001,
+                                          16'b1000000000000000,
+                                          16'b1111111100000000,
+                                          16'b1111000011110000,
+                                          16'b1100110011001100,
+                                          16'b1010101010101010 };
+
+
+logic [WIDTH-4-1:0] msb_bits = '0;
+logic [5:0][15:0] lsb_bits = lsb_bits_init;
+
+logic [16*6-1:0] lsb_bits_flat;
+assign lsb_bits_flat[16*6-1:0] = lsb_bits;
+
+
+integer i,j;
+always_ff @(posedge clk) begin
+  if( set ) begin
+
+    msb_bits[WIDTH-4-1:0] <= set_val[WIDTH-1:4];
+    for( i=0; i<6; i++ ) begin
+      for( j=0; j<16; j++ ) begin
+        lsb_bits[i][j] <= lsb_bits_init[i][(set_val[3:0]+j) % 16];
+      end
+    end
+
+  end else if( dec ) begin
+
+    if( lsb_bits[5][0] ) begin
+      msb_bits[WIDTH-4-1:0] <= msb_bits[WIDTH-4-1:0] - 1'b1;
+    end
+    for( i=0; i<6; i++ ) begin
+      for( j=0; j<16; j++ ) begin
+        if( j==0 ) begin
+          lsb_bits[i][j] <= lsb_bits[i][15];
+        end else begin
+          lsb_bits[i][j] <= lsb_bits[i][j-1];
+        end
+      end
+    end
+
+  end
+end
+
+
+assign q[WIDTH-1:4] = msb_bits[WIDTH-4-1:0];
+assign q[3] = lsb_bits[3][0],
+       q[2] = lsb_bits[2][0],
+       q[1] = lsb_bits[1][0],
+       q[0] = lsb_bits[0][0];
+
+assign q_is_zero = ~|q[WIDTH-1:0];
+
+endmodule
+

fast_counter_tb.sv

@@ -0,0 +1,168 @@
+//------------------------------------------------------------------------------
+// main_tb.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// Testbench for fast_counter.sv
+
+// use this define to make some things differently in simulation
+`define SIMULATION yes
+
+`timescale 1ns / 1ps
+
+module fast_counter_tb();
+
+logic clk200;
+initial begin
+  #0 clk200 = 1'b0;
+  forever
+    #2.5 clk200 = ~clk200;
+end
+
+// external device "asynchronous" clock
+logic clk33;
+initial begin
+  #0 clk33 = 1'b0;
+  forever
+    #15.151 clk33 = ~clk33;
+end
+
+logic rst;
+initial begin
+  #0 rst = 1'b0;
+  #10.2 rst = 1'b1;
+  #5 rst = 1'b0;
+  //#10000;
+  forever begin
+    #9985 rst = ~rst;
+    #5 rst = ~rst;
+  end
+end
+
+logic nrst;
+assign nrst = ~rst;
+
+logic rst_once;
+initial begin
+  #0 rst_once = 1'b0;
+  #10.2 rst_once = 1'b1;
+  #5 rst_once = 1'b0;
+end
+
+logic nrst_once;
+assign nrst_once = ~rst_once;
+
+logic [31:0] DerivedClocks;
+clk_divider #(
+  .WIDTH( 32 )
+) cd1 (
+  .clk( clk200 ),
+  .nrst( nrst_once ),
+  .ena( 1'b1 ),
+  .out( DerivedClocks[31:0] )
+);
+
+logic [31:0] E_DerivedClocks;
+edge_detect ed1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
+  .in( DerivedClocks[31:0] ),
+  .rising( E_DerivedClocks[31:0] ),
+  .falling(  ),
+  .both(  )
+);
+
+logic [31:0] RandomNumber1;
+c_rand rng1 (
+  .clk( clk200 ),
+  .rst( 1'b0 ),
+  .reseed( rst_once ),
+  .seed_val( DerivedClocks[31:0] ^ (DerivedClocks[31:0] << 1) ),
+  .out( RandomNumber1[15:0] )
+);
+
+c_rand rng2 (
+  .clk( clk200 ),
+  .rst( 1'b0 ),
+  .reseed( rst_once ),
+  .seed_val( DerivedClocks[31:0] ^ (DerivedClocks[31:0] << 2) ),
+  .out( RandomNumber1[31:16] )
+);
+
+logic start;
+initial begin
+  #0 start = 1'b0;
+  #100 start = 1'b1;
+  #20 start = 1'b0;
+end
+
+// Module under test ==========================================================
+
+
+logic inc = 1'b0;
+logic dec = 1'b0;
+logic set = 1'b0;
+
+logic [7:0] seq_cntr = '0;
+always_ff @(posedge clk200) begin
+  if( ~nrst_once ) begin
+    seq_cntr[7:0] <= '0;
+  end else begin
+    seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
+  end
+
+/*  if( seq_cntr[7:0]>5 ) begin
+    inc = 1'b1;
+  end else begin
+    inc = 1'b0;
+  end*/
+
+  if( seq_cntr[7:0]>5 ) begin
+    dec = 1'b1;
+  end else begin
+    dec = 1'b0;
+  end
+
+  if( seq_cntr[7:0]==5 ) begin
+    set = 1'b1;
+  end else begin
+    set = 1'b0;
+  end
+
+end
+
+
+
+`define WIDTH 14
+
+logic [`WIDTH-1:0] q;
+fast_counter #(
+  .WIDTH( `WIDTH )
+) fc (
+  .clk( clk200 ),
+  .nrst( nrst_once ),
+  .inc( inc ),
+  .dec( dec ),
+  .set( set ),
+  .set_val( RandomNumber1[`WIDTH-1:0] ),
+  .q( q[`WIDTH-1:0] ),
+  .q_is_zero(  )
+);
+
+logic [`WIDTH-1:0] q_d1 = '0;
+always_ff @(posedge clk200) begin
+  if( ~nrst_once ) begin
+    q_d1[`WIDTH-1:0] <= '0;
+  end else begin
+    q_d1[`WIDTH-1:0] <= q[`WIDTH-1:0];
+  end
+end
+
+logic success_dec;
+assign success_dec = (q_d1[`WIDTH-1:0] == (q[`WIDTH-1:0]+1'b1));
+logic success_inc;
+assign success_inc = (q_d1[`WIDTH-1:0] == (q[`WIDTH-1:0]-1'b1));
+
+endmodule
+