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Rewritten arst conditions in cdc_strobe.sv
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@ -35,7 +35,7 @@
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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cdc_strobe_v2 cdc_wr_req (
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cdc_strobe cdc_wr_req (
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.arst( 1'b0 ),
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.arst( 1'b0 ),
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.clk1( clk1 ),
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.clk1( clk1 ),
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@ -77,19 +77,22 @@ module cdc_strobe (
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// strb1 edge detector
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// strb1 edge detector
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// prevents secondary strobe generation in case strb1 is not one-cycle-high
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// prevents secondary strobe generation in case strb1 is not one-cycle-high
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logic strb1_ed;
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logic strb1_ed;
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assign strb1_ed = (~strb1_b && strb1) && ~arst;
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assign strb1_ed = ( ~strb1_b && strb1 );
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// 2 bit gray counter, it must NEVER be reset
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// 2 bit gray counter, it must NEVER be reset
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logic [1:0] gc_FP_ATTR = '0;
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logic [1:0] gc_FP_ATTR = '0;
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always @(posedge clk1) begin
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always @(posedge clk1 or posedge arst) begin
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if( strb1_ed ) begin
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if( arst ) begin
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gc_FP_ATTR[1:0] <= {gc_FP_ATTR[0],~gc_FP_ATTR[1]}; // incrementing counter
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// nop
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end else begin
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if( strb1_ed ) begin
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gc_FP_ATTR[1:0] <= {gc_FP_ATTR[0],~gc_FP_ATTR[1]}; // incrementing counter
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end
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end
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end
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end
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end
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// buffering counter value on clk2
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// buffering counter value on clk2
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// gray counter does not need a synchronizer
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// gray counter doesnt need a synchronizer
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logic [1:0][1:0] gc_b = '0;
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logic [1:0][1:0] gc_b = '0;
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always @(posedge clk2 or posedge arst) begin
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always @(posedge clk2 or posedge arst) begin
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if( arst ) begin
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if( arst ) begin
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@ -102,7 +105,7 @@ module cdc_strobe (
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end
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end
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// gray_bit_b edge detector
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// gray_bit_b edge detector
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assign strb2 = (gc_b[1][1:0] != gc_b[0][1:0] ) && ~arst;
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assign strb2 = ( gc_b[1][1:0] != gc_b[0][1:0] );
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endmodule
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endmodule
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