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Konstantin Pavlov
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README.md
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README.md
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Must-have verilog systemverilog modules
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---------------------------------------
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=======================================
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Originally published as part of https://github.com/pConst/basic_verilog
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by Konstantin Pavlov, pavlovconst@gmail.com
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Hello! This is a collection of verilog systemverilog synthesizable modules.<br>
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All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors.<br>
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Please feel free to contact me in case you found any code issues.<br>
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Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects!<br>
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Hi! This is a collection of Verilog SystemVerilog synthesizable modules.
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Konstantin Pavlov, pavlovconst@gmail.com
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All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors.
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The code is licensed under CC BY-SA 4_0.<br>
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You can remix, transform, and build upon the material for any purpose, even commercially<br>
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You must provide the name of the creator and distribute your contributions under the same license as the original<br>
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Please feel free to make pull requests or contact me in case you spot any code issues.
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Directories description:
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-----------------------
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| DIRECTORY | DESCRIPTION |
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|-----------|-------------|
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| Advanced Synthesis Cookbook/ | useful code from Altera's cookbook |
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| KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processo |
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| pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices |
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| example_projects/ | FPGA project examples |
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| benchmark_projects/ | compilation time benchmarks for a dosen of FPGA types |
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| scripts/ | useful TCL scripts |
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Scripts description:
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Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects!
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Licensing
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---------
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The code is licensed under CC BY-SA 4_0
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That means, that you can remix, transform, and build upon the material for any purpose, even commercially.
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However, YOU MUST provide the name of the creator and distribute your contributions under the same license as the original.
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Contents description
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--------------------
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| SCRIPT | DESCRIPTION |
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|--------|-------------|
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| scripts/allow_undefined_ports.tcl | allows generation of test projects with undefined pins for Vivado IDE |
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| scripts/compile_quartus.tcl | boilerplate script for commandline project compilation in Quartus IDE |
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| scripts/convert_sof_to_jam.bat | Altera/Intel FPGA configuration file converter |
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| scripts/convert_sof_to_rbf.bat | another Altera/Intel FPGA configuration file converter |
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| scripts/iverilog_compile.tcl | complete script to compile Verilog sources with iverilog tool and run simulation in gtkwave tool |
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| scripts/modelsim_compile.tcl | Modelsim no-project-mode compilation script |
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| scripts/post_flow_quartus.tcl | custom reporting or report analisys for Intel Quartus IDE |
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| scripts/post_flow_vivado.tcl | custom reporting or report analisys for Xilinx Vivado IDE |
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| scripts/program_all.bat | command line programmer example for Altera/Intel FPGAs |
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| scripts/project_version_auto_increment.tcl | project version autoincrement script for Quartus IDE |
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| scripts/quartus_system_console_init.tcl | initialization script for reading/writing Avalon-MM through JTAG-to-Avalon-MM bridge IP |
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| scripts/set_project_directory.tcl | changes current directory to match project directory in Vivado IDE |
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| scripts/write_avalon_mm_from_file.tcl | writing bulk binary data from binary file to Avalon-MM through JTAG-to-Avalon-MM bridge IP |
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Modules description:
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--------------------
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| MODULE | DESCRIPTION |
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|--------|-------------|
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| ActionBurst.v | multichannel one-shot triggering module |
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| ActionBurst2.v | multichannel one-shot triggering with variable steps |
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| adder_tree.sv | adding multiple values together in parallel |
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| bin2gray.sv | combinational Gray code to binary converter |
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| bin2pos.sv | converts binary coded value to positional (one-hot) code |
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| clk_divider.sv | wide reference clock divider |
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| debounce.v | two-cycle debounce for input buttons |
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| delay.sv | useful module to make static delays or to synchronize across clock domains |
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| dynamic_delay.sv | dynamic delay for arbitrary input signal |
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| edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
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| encoder.v | digital encoder input logic module |
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| fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation |
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| gray2bin.sv | combinational binary to Gray code converter |
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| leave_one_hot.sv | combinational module that leaves only lowest hot bit |
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| lifo.sv | single-clock LIFO buffer (stack) implementation |
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| main_tb.sv | basic testbench template |
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| NDivide.v | primitive integer divider |
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| pos2bin.sv | converts positional (one-hot) value to binary representation |
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| pos2bin.sv | converts positional (one-hot) value to binary representation |
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| prbs_gen_chk.sv | PRBS pattern generator or checker |
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| pulse_gen.sv | generates pulses with given width and delay |
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| pulse_stretch.sv | configurable pulse stretcher/extender module |
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| reset_set.sv | SR trigger variant w/o metastable state, set dominates here |
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| reverse_bytes.sv | reverses bytes order within multi-byte array |
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| reverse_vector.sv | reverses signal order within multi-bit bus |
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| set_reset.sv | SR trigger variant w/o metastable state, reset dominates here |
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| spi_master.sv | universal spi master module |
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| UartRx.v | straightforward yet simple UART receiver |
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| UartTx.v | straightforward yet simple UART transmitter |
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| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
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| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
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| UartRxExtreme.v | extreme minimal UART receiver implementation |
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| UartTxExtreme.v | extreme minimal UART transmitter implementation |
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Also added testbenches for selected modules
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For your convinience I`ve tagged some sources by their "difficulty":
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:green_circle: - for the most basic tasks
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:red_circle: - for advanced or special purpose routines
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If you are a beginner in HW design - you may want to start exploring :green_circle: code first.
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Almost every source file in the repository contains detailed description and instantiation template!
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| USAGE | DIRECTORY | DESCRIPTION |
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|---------------|--------------|-------------|
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| | Advanced Synthesis Cookbook/ | useful code from Altera's cookbook |
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| | KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processor sources |
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| :red_circle: | XilinxBoardStore_with_Alveo_cards_support | board definitions for Xilinx Alveo accelerator cards |
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| | pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices |
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| | avalon_mm_master_templates/ | Avalon-MM component templates from Altera |
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| | axi_master_slave_templates/ | AXI componet templates generated by Vivado |
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| | benchmark_projects/ | benchmarking various IDEs to compile exact same Verilog project |
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| | dual_port_ram_templates/ | Block RAM templates |
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| | example_projects/ | FPGA project boilerplates and examples |
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| | gitignores/ | gitignore files for FPGA projects |
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| | scripts/ | useful TCL, batch and shell scripts |
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| :red_circle: | scripts_for_intel_hls/ | useful scripts for compiling for Intel HLS |
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| :red_circle: | scripts_for_xilinx_hls/ | useful scripts for compiling for Xilinx HLS |
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| | xpm | Xilinx parametrizable macros sources |
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| USAGE | FILE | DESCRIPTION |
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|----------------|--------------------|-------------|
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| | adder_tree.sv | adding multiple values together in parallel |
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| | axi4l_logger.sv | |
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| :green_circle: | bin2gray.sv | combinational Gray code to binary converter |
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| | bin2pos.sv | converts binary coded value to positional (one-hot) code |
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| | cdc_data.sv | |
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| | cdc_strobe.sv | |
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| :green_circle: | clk_divider.sv | wide reference clock divider |
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| | clogb2.svh | |
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| :green_circle: | debounce.v | two-cycle debounce for input buttons |
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| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains |
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| | delayed_event.sv | |
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| | dynamic_delay.sv | dynamic delay for arbitrary input signal |
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| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
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| | encoder.v | digital encoder input logic module |
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| :red_circle: | fast_counter.sv | |
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| | fifo_combiner.sv | |
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| | fifo_operator.sv | |
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| :red_circle: | fifo_single_clock_ram_*.sv | single-clock FIFO buffer (queue) implementation |
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| :red_circle: | fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation |
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| :green_circle: | gray2bin.sv | combinational binary to Gray code converter |
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| :red_circle: | gray_functions.vh | |
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| :green_circle: | hex2ascii.sv | |
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| | leave_one_hot.sv | combinational module that leaves only lowest hot bit |
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| | lifo.sv | single-clock LIFO buffer (stack) implementation |
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| | main_tb.sv | basic testbench template |
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| | moving_average.sv | |
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| | pack_unpack_array.v | |
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| | pattern_detect.sv | |
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| | pdm_modulator.sv | |
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| | pos2bin.sv | converts positional (one-hot) value to binary representation |
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| | prbs_gen_chk.sv | PRBS pattern generator or checker |
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| | preview_fifo.sv | |
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| | priority_enc.sv | |
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| | pulse_gen.sv | generates pulses with given width and delay |
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| | pulse_stretch.sv | configurable pulse stretcher/extender module |
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| | pwm_modulator.sv | |
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| :red_circle: | read_ahead_buf.sv | |
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| | reset_set.sv | SR trigger variant w/o metastable state, set dominates here |
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| | reset_set_comb.sv | |
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| | reverse_bytes.sv | reverses bytes order within multi-byte array |
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| | reverse_dimensions.sv | |
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| | reverse_vector.sv | reverses signal order within multi-bit bus |
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| | round_robin_enc.sv | |
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| | round_robin_performance_enc.sv | |
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| | set_reset.sv | SR trigger variant w/o metastable state, reset dominates here |
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| | set_reset_comb.sv | |
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| | sim_clk_gen.sv | |
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| :red_circle: | soft_latch.sv | |
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| | spi_master.sv | universal spi master module |
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| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | |
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| :red_circle: | true_single_port_write_first_ram.sv | |
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| | uart_debug_printer.sv | |
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| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver |
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| | uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
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| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter |
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| | uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs |
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Also added testbenches for selected modules.
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