diff --git a/README.md b/README.md index 546c8a1..b451d8f 100644 --- a/README.md +++ b/README.md @@ -1,85 +1,106 @@ Must-have verilog systemverilog modules ---------------------------------------- +======================================= +Originally published as part of https://github.com/pConst/basic_verilog +by Konstantin Pavlov, pavlovconst@gmail.com -Hello! This is a collection of verilog systemverilog synthesizable modules.
-All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors.
-Please feel free to contact me in case you found any code issues.
-Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects!
+Hi! This is a collection of Verilog SystemVerilog synthesizable modules. -Konstantin Pavlov, pavlovconst@gmail.com +All the code is highly reusable across typical FPGA projects and mainstream FPGA vendors. -The code is licensed under CC BY-SA 4_0.
-You can remix, transform, and build upon the material for any purpose, even commercially
-You must provide the name of the creator and distribute your contributions under the same license as the original
+Please feel free to make pull requests or contact me in case you spot any code issues. -Directories description: ------------------------ - -| DIRECTORY | DESCRIPTION | -|-----------|-------------| -| Advanced Synthesis Cookbook/ | useful code from Altera's cookbook | -| KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processo | -| pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices | -| example_projects/ | FPGA project examples | -| benchmark_projects/ | compilation time benchmarks for a dosen of FPGA types | -| scripts/ | useful TCL scripts | - -Scripts description: +Also, give me a pleasure, tell me if the code has got succesfully implemented in your hobby, scientific or industrial projects! + +Licensing +--------- +The code is licensed under CC BY-SA 4_0 +That means, that you can remix, transform, and build upon the material for any purpose, even commercially. +However, YOU MUST provide the name of the creator and distribute your contributions under the same license as the original. + +Contents description -------------------- - -| SCRIPT | DESCRIPTION | -|--------|-------------| -| scripts/allow_undefined_ports.tcl | allows generation of test projects with undefined pins for Vivado IDE | -| scripts/compile_quartus.tcl | boilerplate script for commandline project compilation in Quartus IDE | -| scripts/convert_sof_to_jam.bat | Altera/Intel FPGA configuration file converter | -| scripts/convert_sof_to_rbf.bat | another Altera/Intel FPGA configuration file converter | -| scripts/iverilog_compile.tcl | complete script to compile Verilog sources with iverilog tool and run simulation in gtkwave tool | -| scripts/modelsim_compile.tcl | Modelsim no-project-mode compilation script | -| scripts/post_flow_quartus.tcl | custom reporting or report analisys for Intel Quartus IDE | -| scripts/post_flow_vivado.tcl | custom reporting or report analisys for Xilinx Vivado IDE | -| scripts/program_all.bat | command line programmer example for Altera/Intel FPGAs | -| scripts/project_version_auto_increment.tcl | project version autoincrement script for Quartus IDE | -| scripts/quartus_system_console_init.tcl | initialization script for reading/writing Avalon-MM through JTAG-to-Avalon-MM bridge IP | -| scripts/set_project_directory.tcl | changes current directory to match project directory in Vivado IDE | -| scripts/write_avalon_mm_from_file.tcl | writing bulk binary data from binary file to Avalon-MM through JTAG-to-Avalon-MM bridge IP | - -Modules description: --------------------- - -| MODULE | DESCRIPTION | -|--------|-------------| -| ActionBurst.v | multichannel one-shot triggering module | -| ActionBurst2.v | multichannel one-shot triggering with variable steps | -| adder_tree.sv | adding multiple values together in parallel | -| bin2gray.sv | combinational Gray code to binary converter | -| bin2pos.sv | converts binary coded value to positional (one-hot) code | -| clk_divider.sv | wide reference clock divider | -| debounce.v | two-cycle debounce for input buttons | -| delay.sv | useful module to make static delays or to synchronize across clock domains | -| dynamic_delay.sv | dynamic delay for arbitrary input signal | -| edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge | -| encoder.v | digital encoder input logic module | -| fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation | -| gray2bin.sv | combinational binary to Gray code converter | -| leave_one_hot.sv | combinational module that leaves only lowest hot bit | -| lifo.sv | single-clock LIFO buffer (stack) implementation | -| main_tb.sv | basic testbench template | -| NDivide.v | primitive integer divider | -| pos2bin.sv | converts positional (one-hot) value to binary representation | -| pos2bin.sv | converts positional (one-hot) value to binary representation | -| prbs_gen_chk.sv | PRBS pattern generator or checker | -| pulse_gen.sv | generates pulses with given width and delay | -| pulse_stretch.sv | configurable pulse stretcher/extender module | -| reset_set.sv | SR trigger variant w/o metastable state, set dominates here | -| reverse_bytes.sv | reverses bytes order within multi-byte array | -| reverse_vector.sv | reverses signal order within multi-bit bus | -| set_reset.sv | SR trigger variant w/o metastable state, reset dominates here | -| spi_master.sv | universal spi master module | -| UartRx.v | straightforward yet simple UART receiver | -| UartTx.v | straightforward yet simple UART transmitter | -| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs | -| uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs | -| UartRxExtreme.v | extreme minimal UART receiver implementation | -| UartTxExtreme.v | extreme minimal UART transmitter implementation | - -Also added testbenches for selected modules +For your convinience I`ve tagged some sources by their "difficulty": +:green_circle: - for the most basic tasks +:red_circle: - for advanced or special purpose routines + +If you are a beginner in HW design - you may want to start exploring :green_circle: code first. +Almost every source file in the repository contains detailed description and instantiation template! + +| USAGE | DIRECTORY | DESCRIPTION | +|---------------|--------------|-------------| +| | Advanced Synthesis Cookbook/ | useful code from Altera's cookbook | +| | KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processor sources | +| :red_circle: | XilinxBoardStore_with_Alveo_cards_support | board definitions for Xilinx Alveo accelerator cards | +| | pacoblaze-2.2/ | version of Picoblaze adapted for Altera devices | +| | avalon_mm_master_templates/ | Avalon-MM component templates from Altera | +| | axi_master_slave_templates/ | AXI componet templates generated by Vivado | +| | benchmark_projects/ | benchmarking various IDEs to compile exact same Verilog project | +| | dual_port_ram_templates/ | Block RAM templates | +| | example_projects/ | FPGA project boilerplates and examples | +| | gitignores/ | gitignore files for FPGA projects | +| | scripts/ | useful TCL, batch and shell scripts | +| :red_circle: | scripts_for_intel_hls/ | useful scripts for compiling for Intel HLS | +| :red_circle: | scripts_for_xilinx_hls/ | useful scripts for compiling for Xilinx HLS | +| | xpm | Xilinx parametrizable macros sources | + +| USAGE | FILE | DESCRIPTION | +|----------------|--------------------|-------------| +| | adder_tree.sv | adding multiple values together in parallel | +| | axi4l_logger.sv | | +| :green_circle: | bin2gray.sv | combinational Gray code to binary converter | +| | bin2pos.sv | converts binary coded value to positional (one-hot) code | +| | cdc_data.sv | | +| | cdc_strobe.sv | | +| :green_circle: | clk_divider.sv | wide reference clock divider | +| | clogb2.svh | | +| :green_circle: | debounce.v | two-cycle debounce for input buttons | +| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains | +| | delayed_event.sv | | +| | dynamic_delay.sv | dynamic delay for arbitrary input signal | +| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge | +| | encoder.v | digital encoder input logic module | +| :red_circle: | fast_counter.sv | | +| | fifo_combiner.sv | | +| | fifo_operator.sv | | +| :red_circle: | fifo_single_clock_ram_*.sv | single-clock FIFO buffer (queue) implementation | +| :red_circle: | fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation | +| :green_circle: | gray2bin.sv | combinational binary to Gray code converter | +| :red_circle: | gray_functions.vh | | +| :green_circle: | hex2ascii.sv | | +| | leave_one_hot.sv | combinational module that leaves only lowest hot bit | +| | lifo.sv | single-clock LIFO buffer (stack) implementation | +| | main_tb.sv | basic testbench template | +| | moving_average.sv | | +| | pack_unpack_array.v | | +| | pattern_detect.sv | | +| | pdm_modulator.sv | | +| | pos2bin.sv | converts positional (one-hot) value to binary representation | +| | prbs_gen_chk.sv | PRBS pattern generator or checker | +| | preview_fifo.sv | | +| | priority_enc.sv | | +| | pulse_gen.sv | generates pulses with given width and delay | +| | pulse_stretch.sv | configurable pulse stretcher/extender module | +| | pwm_modulator.sv | | +| :red_circle: | read_ahead_buf.sv | | +| | reset_set.sv | SR trigger variant w/o metastable state, set dominates here | +| | reset_set_comb.sv | | +| | reverse_bytes.sv | reverses bytes order within multi-byte array | +| | reverse_dimensions.sv | | +| | reverse_vector.sv | reverses signal order within multi-bit bus | +| | round_robin_enc.sv | | +| | round_robin_performance_enc.sv | | +| | set_reset.sv | SR trigger variant w/o metastable state, reset dominates here | +| | set_reset_comb.sv | | +| | sim_clk_gen.sv | | +| :red_circle: | soft_latch.sv | | +| | spi_master.sv | universal spi master module | +| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | | +| :red_circle: | true_single_port_write_first_ram.sv | | +| | uart_debug_printer.sv | | +| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver | +| | uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs | +| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter | +| | uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs | + +Also added testbenches for selected modules. + \ No newline at end of file