mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-14 06:42:54 +08:00
Added single clock fifo modules (two variants)
This commit is contained in:
Konstantin Pavlov
parent
cb224284b1
commit
452b3574ff
125
fifo.sv
125
fifo.sv
@ -1,125 +0,0 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// fifo.sv
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// Simple single-clock FIFO buffer implementation, also known as "queue"
|
||||
// Features one write- and one read- port in FWFT mode
|
||||
// See also "lifo.sv" module for similar LIFO buffer implementation
|
||||
|
||||
|
||||
/* --- INSTANTIATION TEMPLATE BEGIN ---
|
||||
|
||||
fifo #(
|
||||
.DEPTH( 8 ),
|
||||
.DATA_W( 32 )
|
||||
) FF1 (
|
||||
.clk( clk ),
|
||||
.rst( 1'b0 ),
|
||||
|
||||
.w_req( ),
|
||||
.w_data( ),
|
||||
|
||||
.r_req( ),
|
||||
.r_data( ),
|
||||
|
||||
.cnt( ),
|
||||
.empty( ),
|
||||
.full( )
|
||||
);
|
||||
|
||||
--- INSTANTIATION TEMPLATE END ---*/
|
||||
|
||||
module fifo #( parameter
|
||||
|
||||
DEPTH = 4, // max elements count == DEPTH, DEPTH MUST be power of 2
|
||||
DEPTH_W = $clog2(DEPTH)+1, // elements counter width, extra bit to store
|
||||
// "fifo full" state, see cnt[] variable comments
|
||||
|
||||
DATA_W = 32 // data field width
|
||||
)(
|
||||
|
||||
input clk,
|
||||
input rst, // non-inverted reset
|
||||
|
||||
// input port
|
||||
input w_req,
|
||||
input [DATA_W-1:0] w_data,
|
||||
|
||||
// output port
|
||||
input r_req,
|
||||
output logic [DATA_W-1:0] r_data,
|
||||
|
||||
// helper ports
|
||||
output logic [DATA_W-1:0] cnt = 0,
|
||||
output logic empty,
|
||||
output logic full,
|
||||
|
||||
output logic fail
|
||||
);
|
||||
|
||||
// fifo data
|
||||
logic [DEPTH-1:0][DATA_W-1:0] data = 0;
|
||||
|
||||
// cnt[] vector always holds fifo elements count
|
||||
// data[cnt[]] points to the first empty fifo slot
|
||||
// when fifo is full data[cnt[]] points "outside" of data[]
|
||||
|
||||
// please take attention to the case when cnt[]==0 && r_req==1'b1 && w_req==1'b1
|
||||
// this case makes no read/write to the fifo and should be handled externally
|
||||
|
||||
integer i;
|
||||
always_ff @(posedge clk) begin
|
||||
if ( rst ) begin
|
||||
data <= 0;
|
||||
cnt <= 0;
|
||||
end else begin
|
||||
case ({w_req, r_req})
|
||||
2'b01 : begin // reading out
|
||||
if ( cnt[DATA_W-1:0] > 1'b1 ) begin
|
||||
for ( i = (DEPTH-1); i > 0; i = i-1 ) begin
|
||||
data[i-1] <= data[i];
|
||||
end
|
||||
end
|
||||
if ( cnt[DATA_W-1:0] > 1'b0 ) begin
|
||||
cnt[DATA_W-1:0] <= cnt[DATA_W-1:0] - 1'b1;
|
||||
end
|
||||
end
|
||||
2'b10 : begin // writing in
|
||||
if ( ~full ) begin
|
||||
data[cnt[DATA_W-1:0]] <= w_data;
|
||||
cnt[DATA_W-1:0] <= cnt[DATA_W-1:0] + 1'b1;
|
||||
end
|
||||
end
|
||||
2'b11 : begin // simultaneously reading and writing
|
||||
if ( cnt[DATA_W-1:0] > 1'b1 ) begin
|
||||
for ( i = (DEPTH-1); i > 0; i = i-1 ) begin
|
||||
data[i-1] <= data[i];
|
||||
end
|
||||
end
|
||||
if ( cnt[DATA_W-1:0] > 1'b0 ) begin
|
||||
data[cnt[DATA_W-1:0]-1] <= w_data;
|
||||
end
|
||||
// cnt[DATA_W-1:0] <= cnt[DATA_W-1:0]; // data counter does not change
|
||||
end
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
empty = ( cnt[DATA_W-1:0] == 0 );
|
||||
full = ( cnt[DATA_W-1:0] == DEPTH );
|
||||
|
||||
if (~empty) begin
|
||||
r_data[DATA_W-1:0] = data[0]; // first-word fall-through mode
|
||||
end else begin
|
||||
r_data[DATA_W-1:0] = 0;
|
||||
end
|
||||
|
||||
fail = ( empty && r_req ) ||
|
||||
( full && w_req );
|
||||
end
|
||||
|
||||
endmodule
|
||||
150
fifo_single_clock_reg_v1.sv
Normal file
150
fifo_single_clock_reg_v1.sv
Normal file
@ -0,0 +1,150 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// fifo_single_clock_reg_v1.sv
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// Single-clock FIFO buffer implementation, also known as "queue"
|
||||
//
|
||||
// Features:
|
||||
// - single clock operation
|
||||
// - configurable depth and data width
|
||||
// - one write- and one read- port in "FWFT" or "normal" mode
|
||||
// - protected against overflow and underflow
|
||||
// - simultaneous read and write operations supported if not full and not empty
|
||||
// - only read operation is performed when (full && r_req && w_req)
|
||||
// - only write operation is performed when (empty && r_req && w_req)
|
||||
//
|
||||
// See also "lifo.sv" module for similar LIFO buffer implementation
|
||||
|
||||
|
||||
/* --- INSTANTIATION TEMPLATE BEGIN ---
|
||||
|
||||
fifo_single_clock_reg_v1 #(
|
||||
.FWFT_MODE( "TRUE" ),
|
||||
.DEPTH( 8 ),
|
||||
.DATA_W( 32 )
|
||||
) FF1 (
|
||||
.clk( clk ),
|
||||
.nrst( 1'b1 ),
|
||||
|
||||
.w_req( ),
|
||||
.w_data( ),
|
||||
|
||||
.r_req( ),
|
||||
.r_data( ),
|
||||
|
||||
.cnt( ),
|
||||
.empty( ),
|
||||
.full( )
|
||||
);
|
||||
|
||||
--- INSTANTIATION TEMPLATE END ---*/
|
||||
|
||||
module fifo_single_clock_reg_v1 #( parameter
|
||||
|
||||
FWFT_MODE = "TRUE", // "TRUE" - first word fall-trrough" mode
|
||||
// "FALSE" - normal fifo mode
|
||||
|
||||
DEPTH = 8, // max elements count == DEPTH, DEPTH MUST be power of 2
|
||||
DEPTH_W = $clog2(DEPTH)+1, // elements counter width, extra bit to store
|
||||
// "fifo full" state, see cnt[] variable comments
|
||||
|
||||
DATA_W = 32 // data field width
|
||||
)(
|
||||
|
||||
input clk,
|
||||
input nrst, // inverted reset
|
||||
|
||||
// input port
|
||||
input w_req,
|
||||
input [DATA_W-1:0] w_data,
|
||||
|
||||
// output port
|
||||
input r_req,
|
||||
output logic [DATA_W-1:0] r_data,
|
||||
|
||||
// helper ports
|
||||
output logic [DEPTH_W-1:0] cnt = '0,
|
||||
output logic empty,
|
||||
output logic full,
|
||||
|
||||
output logic fail
|
||||
);
|
||||
|
||||
// fifo data
|
||||
logic [DEPTH-1:0][DATA_W-1:0] data = '0;
|
||||
|
||||
// data output buffer for normal fifo mode
|
||||
logic [DATA_W-1:0] data_buf = '0;
|
||||
|
||||
// cnt[] vector always holds fifo elements count
|
||||
// data[cnt[]] points to the first empty fifo slot
|
||||
// when fifo is full data[cnt[]] points "outside" of data[]
|
||||
|
||||
// filtered requests
|
||||
logic w_req_f;
|
||||
assign w_req_f = w_req && ~full;
|
||||
|
||||
logic r_req_f;
|
||||
assign r_req_f = r_req && ~empty;
|
||||
|
||||
|
||||
integer i;
|
||||
always_ff @(posedge clk) begin
|
||||
if ( ~nrst ) begin
|
||||
data <= '0;
|
||||
cnt[DEPTH_W-1:0] <= '0;
|
||||
data_buf[DATA_W-1:0] <= '0;
|
||||
end else begin
|
||||
unique case ({w_req_f, r_req_f})
|
||||
2'b00: ; // nothing
|
||||
|
||||
2'b01: begin // reading out
|
||||
for ( i = (DEPTH-1); i > 0; i-- ) begin
|
||||
data[i-1] <= data[i];
|
||||
end
|
||||
cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] - 1'b1;
|
||||
end
|
||||
|
||||
2'b10: begin // writing in
|
||||
data[cnt[DEPTH_W-1:0]] <= w_data[DATA_W-1:0];
|
||||
cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] + 1'b1;
|
||||
end
|
||||
|
||||
2'b11: begin // simultaneously reading and writing
|
||||
for ( i = (DEPTH-1); i > 0; i-- ) begin
|
||||
data[i-1] <= data[i];
|
||||
end
|
||||
data[cnt[DEPTH_W-1:0]-1] <= w_data[DATA_W-1:0];
|
||||
// data counter does not change here
|
||||
end
|
||||
endcase
|
||||
|
||||
// data buffer works only for normal fifo mode
|
||||
if( r_req_f ) begin
|
||||
data_buf[DATA_W-1:0] <= data[0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_comb begin
|
||||
empty = ( cnt[DEPTH_W-1:0] == '0 );
|
||||
full = ( cnt[DEPTH_W-1:0] == DEPTH );
|
||||
|
||||
if( FWFT_MODE == "TRUE" ) begin
|
||||
if (~empty) begin
|
||||
r_data[DATA_W-1:0] = data[0]; // first-word fall-through mode
|
||||
end else begin
|
||||
r_data[DATA_W-1:0] = '0;
|
||||
end
|
||||
end else begin
|
||||
r_data[DATA_W-1:0] = data_buf[DATA_W-1:0]; // normal mode
|
||||
end
|
||||
|
||||
fail = ( empty && r_req ) ||
|
||||
( full && w_req );
|
||||
end
|
||||
|
||||
endmodule
|
||||
305
fifo_single_clock_reg_v1_tb.sv
Normal file
305
fifo_single_clock_reg_v1_tb.sv
Normal file
@ -0,0 +1,305 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// fifo_single_clock_reg_v1_tb.sv
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// testbench for fifo_single_clock_reg_v1.sv module
|
||||
//
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module fifo_single_clock_reg_v1_tb();
|
||||
|
||||
logic clk200;
|
||||
initial begin
|
||||
#0 clk200 = 1'b0;
|
||||
forever
|
||||
#2.5 clk200 = ~clk200;
|
||||
end
|
||||
|
||||
// external device "asynchronous" clock
|
||||
logic clk33;
|
||||
initial begin
|
||||
#0 clk33 = 1'b0;
|
||||
forever
|
||||
#15.151 clk33 = ~clk33;
|
||||
end
|
||||
|
||||
logic rst;
|
||||
initial begin
|
||||
#0 rst = 1'b0;
|
||||
#10.2 rst = 1'b1;
|
||||
#5 rst = 1'b0;
|
||||
//#10000;
|
||||
forever begin
|
||||
#9985 rst = ~rst;
|
||||
#5 rst = ~rst;
|
||||
end
|
||||
end
|
||||
|
||||
logic nrst;
|
||||
assign nrst = ~rst;
|
||||
|
||||
logic rst_once;
|
||||
initial begin
|
||||
#0 rst_once = 1'b0;
|
||||
#10.2 rst_once = 1'b1;
|
||||
#5 rst_once = 1'b0;
|
||||
end
|
||||
|
||||
logic nrst_once;
|
||||
assign nrst_once = ~rst_once;
|
||||
|
||||
logic [31:0] DerivedClocks;
|
||||
clk_divider #(
|
||||
.WIDTH( 32 )
|
||||
) cd1 (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
.ena( 1'b1 ),
|
||||
.out( DerivedClocks[31:0] )
|
||||
);
|
||||
|
||||
logic [31:0] E_DerivedClocks;
|
||||
edge_detect ed1[31:0] (
|
||||
.clk( {32{clk200}} ),
|
||||
.nrst( {32{nrst_once}} ),
|
||||
.in( DerivedClocks[31:0] ),
|
||||
.rising( E_DerivedClocks[31:0] ),
|
||||
.falling( ),
|
||||
.both( )
|
||||
);
|
||||
|
||||
logic [15:0] RandomNumber1;
|
||||
c_rand rng1 (
|
||||
.clk(clk200),
|
||||
.rst(rst_once),
|
||||
.reseed(1'b0),
|
||||
.seed_val(DerivedClocks[31:0]),
|
||||
.out( RandomNumber1[15:0] )
|
||||
);
|
||||
|
||||
logic start;
|
||||
initial begin
|
||||
#0 start = 1'b0;
|
||||
#100 start = 1'b1;
|
||||
#20 start = 1'b0;
|
||||
end
|
||||
|
||||
// Module under test ==========================================================
|
||||
|
||||
|
||||
// comment or uncomment to test FWFT and normal fifo modes
|
||||
//`define TEST_FWFT yes
|
||||
|
||||
// comment or uncomment to sweep-test or random test
|
||||
//`define TEST_SWEEP yes
|
||||
|
||||
// comment or uncomment to use bare scfifo or quartus wizard-generated wrappers
|
||||
//`define BARE_SCFIFO yes
|
||||
|
||||
logic full1, empty1;
|
||||
logic full1_d1, empty1_d1;
|
||||
|
||||
logic direction1 = 1'b0;
|
||||
always_ff @(posedge clk200) begin
|
||||
if( ~nrst ) begin
|
||||
direction1 <= 1'b0;
|
||||
end else begin
|
||||
// sweep logic
|
||||
if( full1_d1 ) begin
|
||||
direction1 <= 1'b1;
|
||||
end else if( empty1_d1 ) begin
|
||||
direction1 <= 1'b0;
|
||||
end
|
||||
|
||||
// these signals allow "erroring" requests testing:
|
||||
// - reads from the empty fifo
|
||||
// - writes to the filled fifo
|
||||
full1_d1 <= full1;
|
||||
empty1_d1 <= empty1;
|
||||
end
|
||||
end
|
||||
|
||||
logic [3:0] cnt1;
|
||||
logic [15:0] data_out1;
|
||||
fifo_single_clock_reg_v1 #(
|
||||
`ifdef TEST_FWFT
|
||||
.FWFT_MODE( "TRUE" ),
|
||||
`else
|
||||
.FWFT_MODE( "FALSE" ),
|
||||
`endif
|
||||
.DEPTH( 8 ),
|
||||
.DATA_W( 16 )
|
||||
) FF1 (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
|
||||
`ifdef TEST_SWEEP
|
||||
.w_req( ~direction1 && &RandomNumber1[10] ),
|
||||
.w_data( RandomNumber1[15:0] ),
|
||||
|
||||
.r_req( direction1 && &RandomNumber1[10] ),
|
||||
.r_data( data_out1[15:0] ),
|
||||
`else
|
||||
.w_req( &RandomNumber1[10:9] ),
|
||||
.w_data( RandomNumber1[15:0] ),
|
||||
|
||||
.r_req( &RandomNumber1[8:7] ),
|
||||
.r_data( data_out1[15:0] ),
|
||||
`endif
|
||||
|
||||
.cnt( cnt1[3:0] ),
|
||||
.empty( empty1 ),
|
||||
.full( full1 )
|
||||
);
|
||||
|
||||
|
||||
|
||||
logic full2, empty2;
|
||||
logic full2_d1, empty2_d1;
|
||||
|
||||
logic direction2 = 1'b0;
|
||||
always_ff @(posedge clk200) begin
|
||||
if( ~nrst ) begin
|
||||
direction2 <= 1'b0;
|
||||
end else begin
|
||||
// sweep logic
|
||||
if( full2_d1 ) begin
|
||||
direction2 <= 1'b1;
|
||||
end else if( empty2_d1 ) begin
|
||||
direction2 <= 1'b0;
|
||||
end
|
||||
|
||||
// these signals allow "erroring" requests testing:
|
||||
// - reads from the empty fifo
|
||||
// - writes to the filled fifo
|
||||
full2_d1 <= full2;
|
||||
empty2_d1 <= empty2;
|
||||
end
|
||||
end
|
||||
|
||||
//==============================================================================
|
||||
|
||||
logic [15:0] data_out2;
|
||||
`ifdef BARE_SCFIFO
|
||||
|
||||
SCFIFO #(
|
||||
.LPM_WIDTH( 16 ),
|
||||
.LPM_NUMWORDS( 8 ),
|
||||
.LPM_WIDTHU( $clog2(8) ), /// CEIL(LOG2(LPM_NUMWORDS)),
|
||||
|
||||
`ifdef TEST_FWFT
|
||||
.LPM_SHOWAHEAD( "ON" ),
|
||||
`else
|
||||
.LPM_SHOWAHEAD( "OFF" ),
|
||||
`endif
|
||||
.UNDERFLOW_CHECKING( "ON" ),
|
||||
.OVERFLOW_CHECKING( "ON" ),
|
||||
.ALLOW_RWCYCLE_WHEN_FULL( "ON" ),
|
||||
.ADD_RAM_OUTPUT_REGISTER( "OFF" ),
|
||||
|
||||
.ALMOST_FULL_VALUE( 0 ),
|
||||
.ALMOST_EMPTY_VALUE( 0 ),
|
||||
.ENABLE_ECC( "FALSE" )
|
||||
|
||||
//.USE_EAB( "ON" ),
|
||||
//.MAXIMIZE_SPEED( 5 ),
|
||||
//.DEVICE_FAMILY( "CYCLONE V" ),
|
||||
//.OPTIMIZE_FOR_SPEED( 5 ),
|
||||
//.CBXI_PARAMETER( "NOTHING" )
|
||||
) FF2 (
|
||||
.clock( clk200 ),
|
||||
.aclr( 1'b0 ),
|
||||
.sclr( ~nrst_once ),
|
||||
|
||||
`ifdef TEST_SWEEP
|
||||
.wrreq( ~direction1 && &RandomNumber1[10] ),
|
||||
.data( RandomNumber1[15:0] ),
|
||||
|
||||
.rdreq( direction1 && &RandomNumber1[10] ),
|
||||
.q( data_out2[15:0] ),
|
||||
`else
|
||||
.wrreq( &RandomNumber1[10:9] ),
|
||||
.data( RandomNumber1[15:0] ),
|
||||
|
||||
.rdreq( &RandomNumber1[8:7] ),
|
||||
.q( data_out2[15:0] ),
|
||||
`endif
|
||||
|
||||
.empty( empty2 ),
|
||||
.full( full2 ),
|
||||
|
||||
.almost_empty( ),
|
||||
.almost_full( ),
|
||||
.usedw( ),
|
||||
|
||||
.eccstatus( )
|
||||
);
|
||||
|
||||
`else
|
||||
|
||||
`ifdef TEST_FWFT
|
||||
altera_fifo FF2 (
|
||||
`else
|
||||
altera_fifo_normal FF2 (
|
||||
`endif
|
||||
.clock ( clk200 ),
|
||||
|
||||
`ifdef TEST_SWEEP
|
||||
.wrreq( ~direction1 && &RandomNumber1[10] ),
|
||||
.data( RandomNumber1[15:0] ),
|
||||
|
||||
.rdreq( direction1 && &RandomNumber1[10] ),
|
||||
.q( data_out2[15:0] ),
|
||||
`else
|
||||
.wrreq( &RandomNumber1[10:9] ),
|
||||
.data( RandomNumber1[15:0] ),
|
||||
|
||||
.rdreq( &RandomNumber1[8:7] ),
|
||||
.q( data_out2[15:0] ),
|
||||
`endif
|
||||
|
||||
.empty ( empty2 ),
|
||||
.full ( full2 ),
|
||||
.usedw ( )
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
//==============================================================================
|
||||
|
||||
logic outputs_equal;
|
||||
assign outputs_equal = ( data_out1[15:0] == data_out2[15:0] ) ||
|
||||
`ifdef TEST_FWFT
|
||||
// scipping minor discontinuity
|
||||
// seems like altera`s fifo has some additional buffering???
|
||||
( cnt1[3:0] == 1 && data_out1[15:0] != data_out2[15:0] );
|
||||
`else
|
||||
1'b0;
|
||||
`endif
|
||||
|
||||
logic empty_equal;
|
||||
assign empty_equal = ( empty1 == empty2 );
|
||||
|
||||
logic full_equal;
|
||||
assign full_equal = ( full1 == full2 );
|
||||
|
||||
logic success = 1'b1;
|
||||
always_ff @(posedge clk200) begin
|
||||
if( ~nrst ) begin
|
||||
success <= 1'b1;
|
||||
end else begin
|
||||
if( ~outputs_equal ) begin
|
||||
success <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// this condition is being processed differently by altera`s scfifo and
|
||||
// the custom fifo implementation
|
||||
logic test_cond;
|
||||
assign test_cond = empty1 && &RandomNumber1[10:9] && &RandomNumber1[8:7];
|
||||
|
||||
endmodule
|
||||
175
fifo_single_clock_reg_v2.sv
Normal file
175
fifo_single_clock_reg_v2.sv
Normal file
@ -0,0 +1,175 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// fifo_single_clock_reg_v2.sv
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// Single-clock FIFO buffer implementation, also known as "queue"
|
||||
//
|
||||
// Features:
|
||||
// - single clock operation
|
||||
// - configurable depth and data width
|
||||
// - one write- and one read- port in "FWFT" or "normal" mode
|
||||
// - protected against overflow and underflow
|
||||
// - simultaneous read and write operations supported if not full and not empty
|
||||
// - only read operation is performed when (full && r_req && w_req)
|
||||
// - only write operation is performed when (empty && r_req && w_req)
|
||||
//
|
||||
// See also "lifo.sv" module for similar LIFO buffer implementation
|
||||
|
||||
|
||||
/* --- INSTANTIATION TEMPLATE BEGIN ---
|
||||
|
||||
fifo_single_clock_reg_v2 #(
|
||||
.FWFT_MODE( "TRUE" ),
|
||||
.DEPTH( 8 ),
|
||||
.DATA_W( 32 )
|
||||
) FF1 (
|
||||
.clk( clk ),
|
||||
.nrst( 1'b1 ),
|
||||
|
||||
.w_req( ),
|
||||
.w_data( ),
|
||||
|
||||
.r_req( ),
|
||||
.r_data( ),
|
||||
|
||||
.cnt( ),
|
||||
.empty( ),
|
||||
.full( )
|
||||
);
|
||||
|
||||
--- INSTANTIATION TEMPLATE END ---*/
|
||||
|
||||
module fifo_single_clock_reg_v2 #( parameter
|
||||
|
||||
FWFT_MODE = "TRUE", // "TRUE" - first word fall-trrough" mode
|
||||
// "FALSE" - normal fifo mode
|
||||
|
||||
DEPTH = 8, // max elements count == DEPTH, DEPTH MUST be power of 2
|
||||
DEPTH_W = $clog2(DEPTH)+1, // elements counter width, extra bit to store
|
||||
// "fifo full" state, see cnt[] variable comments
|
||||
|
||||
DATA_W = 32 // data field width
|
||||
)(
|
||||
|
||||
input clk,
|
||||
input nrst, // inverted reset
|
||||
|
||||
// input port
|
||||
input w_req,
|
||||
input [DATA_W-1:0] w_data,
|
||||
|
||||
// output port
|
||||
input r_req,
|
||||
output logic [DATA_W-1:0] r_data,
|
||||
|
||||
// helper ports
|
||||
output logic [DEPTH_W-1:0] cnt = '0,
|
||||
output logic empty,
|
||||
output logic full,
|
||||
|
||||
output logic fail
|
||||
);
|
||||
|
||||
// fifo data, extra element to keep pointer positions always valid,
|
||||
// even when fifo is empty or full
|
||||
logic [DEPTH-1:0][DATA_W-1:0] data = '0;
|
||||
|
||||
// read and write pointers
|
||||
logic [DEPTH_W-1:0] w_ptr = '0;
|
||||
logic [DEPTH_W-1:0] r_ptr = '0;
|
||||
|
||||
// data output buffer for normal fifo mode
|
||||
logic [DATA_W-1:0] data_buf = '0;
|
||||
|
||||
|
||||
// filtered requests
|
||||
logic w_req_f;
|
||||
assign w_req_f = w_req && ~full;
|
||||
|
||||
logic r_req_f;
|
||||
assign r_req_f = r_req && ~empty;
|
||||
|
||||
|
||||
function [DEPTH_W-1:0] inc_ptr (
|
||||
input [DEPTH_W-1:0] ptr
|
||||
);
|
||||
|
||||
if( ptr[DEPTH_W-1:0] == DEPTH-1 ) begin
|
||||
inc_ptr[DEPTH_W-1:0] = '0;
|
||||
end else begin
|
||||
inc_ptr[DEPTH_W-1:0] = ptr[DEPTH_W-1:0] + 1'b1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
integer i;
|
||||
always_ff @(posedge clk) begin
|
||||
if ( ~nrst ) begin
|
||||
data <= '0;
|
||||
cnt[DEPTH_W-1:0] <= '0;
|
||||
|
||||
w_ptr[DEPTH_W-1:0] <= '0;
|
||||
r_ptr[DEPTH_W-1:0] <= '0;
|
||||
|
||||
data_buf[DATA_W-1:0] <= '0;
|
||||
end else begin
|
||||
unique case ({w_req_f, r_req_f})
|
||||
2'b00: ; // nothing
|
||||
|
||||
2'b01: begin // reading out
|
||||
if( ~empty ) begin
|
||||
r_ptr[DEPTH_W-1:0] <= inc_ptr(r_ptr[DEPTH_W-1:0]);
|
||||
end
|
||||
cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] - 1'b1;
|
||||
end
|
||||
|
||||
2'b10: begin // writing in
|
||||
if( ~full ) begin
|
||||
w_ptr[DEPTH_W-1:0] <= inc_ptr(w_ptr[DEPTH_W-1:0]);
|
||||
end
|
||||
data[w_ptr[DEPTH_W-1:0]] <= w_data[DATA_W-1:0];
|
||||
cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] + 1'b1;
|
||||
end
|
||||
|
||||
2'b11: begin // simultaneously reading and writing
|
||||
if( ~empty ) begin
|
||||
r_ptr[DEPTH_W-1:0] <= inc_ptr(r_ptr[DEPTH_W-1:0]);
|
||||
end
|
||||
if( ~full ) begin
|
||||
w_ptr[DEPTH_W-1:0] <= inc_ptr(w_ptr[DEPTH_W-1:0]);
|
||||
end
|
||||
data[w_ptr[DEPTH_W-1:0]] <= w_data[DATA_W-1:0];
|
||||
// data counter does not change here
|
||||
end
|
||||
endcase
|
||||
|
||||
// data buffer works only for normal fifo mode
|
||||
if( r_req_f ) begin
|
||||
data_buf[DATA_W-1:0] <= data[r_ptr[DEPTH_W-1:0]];
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_comb begin
|
||||
empty = ( cnt[DEPTH_W-1:0] == '0 );
|
||||
full = ( cnt[DEPTH_W-1:0] == DEPTH );
|
||||
|
||||
if( FWFT_MODE == "TRUE" ) begin
|
||||
if (~empty) begin
|
||||
r_data[DATA_W-1:0] = data[r_ptr[DEPTH_W-1:0]]; // first-word fall-through mode
|
||||
end else begin
|
||||
r_data[DATA_W-1:0] = '0;
|
||||
end
|
||||
end else begin
|
||||
r_data[DATA_W-1:0] = data_buf[DATA_W-1:0]; // normal mode
|
||||
end
|
||||
|
||||
fail = ( empty && r_req ) ||
|
||||
( full && w_req );
|
||||
end
|
||||
|
||||
endmodule
|
||||
305
fifo_single_clock_reg_v2_tb.sv
Normal file
305
fifo_single_clock_reg_v2_tb.sv
Normal file
@ -0,0 +1,305 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// fifo_single_clock_reg_v2_tb.sv
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// testbench for fifo_single_clock_reg_v2.sv module
|
||||
//
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module fifo_single_clock_reg_v2_tb();
|
||||
|
||||
logic clk200;
|
||||
initial begin
|
||||
#0 clk200 = 1'b0;
|
||||
forever
|
||||
#2.5 clk200 = ~clk200;
|
||||
end
|
||||
|
||||
// external device "asynchronous" clock
|
||||
logic clk33;
|
||||
initial begin
|
||||
#0 clk33 = 1'b0;
|
||||
forever
|
||||
#15.151 clk33 = ~clk33;
|
||||
end
|
||||
|
||||
logic rst;
|
||||
initial begin
|
||||
#0 rst = 1'b0;
|
||||
#10.2 rst = 1'b1;
|
||||
#5 rst = 1'b0;
|
||||
//#10000;
|
||||
forever begin
|
||||
#9985 rst = ~rst;
|
||||
#5 rst = ~rst;
|
||||
end
|
||||
end
|
||||
|
||||
logic nrst;
|
||||
assign nrst = ~rst;
|
||||
|
||||
logic rst_once;
|
||||
initial begin
|
||||
#0 rst_once = 1'b0;
|
||||
#10.2 rst_once = 1'b1;
|
||||
#5 rst_once = 1'b0;
|
||||
end
|
||||
|
||||
logic nrst_once;
|
||||
assign nrst_once = ~rst_once;
|
||||
|
||||
logic [31:0] DerivedClocks;
|
||||
clk_divider #(
|
||||
.WIDTH( 32 )
|
||||
) cd1 (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
.ena( 1'b1 ),
|
||||
.out( DerivedClocks[31:0] )
|
||||
);
|
||||
|
||||
logic [31:0] E_DerivedClocks;
|
||||
edge_detect ed1[31:0] (
|
||||
.clk( {32{clk200}} ),
|
||||
.nrst( {32{nrst_once}} ),
|
||||
.in( DerivedClocks[31:0] ),
|
||||
.rising( E_DerivedClocks[31:0] ),
|
||||
.falling( ),
|
||||
.both( )
|
||||
);
|
||||
|
||||
logic [15:0] RandomNumber1;
|
||||
c_rand rng1 (
|
||||
.clk(clk200),
|
||||
.rst(rst_once),
|
||||
.reseed(1'b0),
|
||||
.seed_val(DerivedClocks[31:0]),
|
||||
.out( RandomNumber1[15:0] )
|
||||
);
|
||||
|
||||
logic start;
|
||||
initial begin
|
||||
#0 start = 1'b0;
|
||||
#100 start = 1'b1;
|
||||
#20 start = 1'b0;
|
||||
end
|
||||
|
||||
// Module under test ==========================================================
|
||||
|
||||
|
||||
// comment or uncomment to test FWFT and normal fifo modes
|
||||
`define TEST_FWFT yes
|
||||
|
||||
// comment or uncomment to sweep-test or random test
|
||||
//`define TEST_SWEEP yes
|
||||
|
||||
// comment or uncomment to use bare scfifo or quartus wizard-generated wrappers
|
||||
//`define BARE_SCFIFO yes
|
||||
|
||||
logic full1, empty1;
|
||||
logic full1_d1, empty1_d1;
|
||||
|
||||
logic direction1 = 1'b0;
|
||||
always_ff @(posedge clk200) begin
|
||||
if( ~nrst ) begin
|
||||
direction1 <= 1'b0;
|
||||
end else begin
|
||||
// sweep logic
|
||||
if( full1_d1 ) begin
|
||||
direction1 <= 1'b1;
|
||||
end else if( empty1_d1 ) begin
|
||||
direction1 <= 1'b0;
|
||||
end
|
||||
|
||||
// these signals allow "erroring" requests testing:
|
||||
// - reads from the empty fifo
|
||||
// - writes to the filled fifo
|
||||
full1_d1 <= full1;
|
||||
empty1_d1 <= empty1;
|
||||
end
|
||||
end
|
||||
|
||||
logic [3:0] cnt1;
|
||||
logic [15:0] data_out1;
|
||||
fifo_single_clock_reg_v2 #(
|
||||
`ifdef TEST_FWFT
|
||||
.FWFT_MODE( "TRUE" ),
|
||||
`else
|
||||
.FWFT_MODE( "FALSE" ),
|
||||
`endif
|
||||
.DEPTH( 8 ),
|
||||
.DATA_W( 16 )
|
||||
) FF1 (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
|
||||
`ifdef TEST_SWEEP
|
||||
.w_req( ~direction1 && &RandomNumber1[10] ),
|
||||
.w_data( RandomNumber1[15:0] ),
|
||||
|
||||
.r_req( direction1 && &RandomNumber1[10] ),
|
||||
.r_data( data_out1[15:0] ),
|
||||
`else
|
||||
.w_req( &RandomNumber1[10:9] ),
|
||||
.w_data( RandomNumber1[15:0] ),
|
||||
|
||||
.r_req( &RandomNumber1[8:7] ),
|
||||
.r_data( data_out1[15:0] ),
|
||||
`endif
|
||||
|
||||
.cnt( cnt1[3:0] ),
|
||||
.empty( empty1 ),
|
||||
.full( full1 )
|
||||
);
|
||||
|
||||
|
||||
|
||||
logic full2, empty2;
|
||||
logic full2_d1, empty2_d1;
|
||||
|
||||
logic direction2 = 1'b0;
|
||||
always_ff @(posedge clk200) begin
|
||||
if( ~nrst ) begin
|
||||
direction2 <= 1'b0;
|
||||
end else begin
|
||||
// sweep logic
|
||||
if( full2_d1 ) begin
|
||||
direction2 <= 1'b1;
|
||||
end else if( empty2_d1 ) begin
|
||||
direction2 <= 1'b0;
|
||||
end
|
||||
|
||||
// these signals allow "erroring" requests testing:
|
||||
// - reads from the empty fifo
|
||||
// - writes to the filled fifo
|
||||
full2_d1 <= full2;
|
||||
empty2_d1 <= empty2;
|
||||
end
|
||||
end
|
||||
|
||||
//==============================================================================
|
||||
|
||||
logic [15:0] data_out2;
|
||||
`ifdef BARE_SCFIFO
|
||||
|
||||
SCFIFO #(
|
||||
.LPM_WIDTH( 16 ),
|
||||
.LPM_NUMWORDS( 8 ),
|
||||
.LPM_WIDTHU( $clog2(8) ), /// CEIL(LOG2(LPM_NUMWORDS)),
|
||||
|
||||
`ifdef TEST_FWFT
|
||||
.LPM_SHOWAHEAD( "ON" ),
|
||||
`else
|
||||
.LPM_SHOWAHEAD( "OFF" ),
|
||||
`endif
|
||||
.UNDERFLOW_CHECKING( "ON" ),
|
||||
.OVERFLOW_CHECKING( "ON" ),
|
||||
.ALLOW_RWCYCLE_WHEN_FULL( "ON" ),
|
||||
.ADD_RAM_OUTPUT_REGISTER( "OFF" ),
|
||||
|
||||
.ALMOST_FULL_VALUE( 0 ),
|
||||
.ALMOST_EMPTY_VALUE( 0 ),
|
||||
.ENABLE_ECC( "FALSE" )
|
||||
|
||||
//.USE_EAB( "ON" ),
|
||||
//.MAXIMIZE_SPEED( 5 ),
|
||||
//.DEVICE_FAMILY( "CYCLONE V" ),
|
||||
//.OPTIMIZE_FOR_SPEED( 5 ),
|
||||
//.CBXI_PARAMETER( "NOTHING" )
|
||||
) FF2 (
|
||||
.clock( clk200 ),
|
||||
.aclr( 1'b0 ),
|
||||
.sclr( ~nrst_once ),
|
||||
|
||||
`ifdef TEST_SWEEP
|
||||
.wrreq( ~direction1 && &RandomNumber1[10] ),
|
||||
.data( RandomNumber1[15:0] ),
|
||||
|
||||
.rdreq( direction1 && &RandomNumber1[10] ),
|
||||
.q( data_out2[15:0] ),
|
||||
`else
|
||||
.wrreq( &RandomNumber1[10:9] ),
|
||||
.data( RandomNumber1[15:0] ),
|
||||
|
||||
.rdreq( &RandomNumber1[8:7] ),
|
||||
.q( data_out2[15:0] ),
|
||||
`endif
|
||||
|
||||
.empty( empty2 ),
|
||||
.full( full2 ),
|
||||
|
||||
.almost_empty( ),
|
||||
.almost_full( ),
|
||||
.usedw( ),
|
||||
|
||||
.eccstatus( )
|
||||
);
|
||||
|
||||
`else
|
||||
|
||||
`ifdef TEST_FWFT
|
||||
altera_fifo FF2 (
|
||||
`else
|
||||
altera_fifo_normal FF2 (
|
||||
`endif
|
||||
.clock ( clk200 ),
|
||||
|
||||
`ifdef TEST_SWEEP
|
||||
.wrreq( ~direction1 && &RandomNumber1[10] ),
|
||||
.data( RandomNumber1[15:0] ),
|
||||
|
||||
.rdreq( direction1 && &RandomNumber1[10] ),
|
||||
.q( data_out2[15:0] ),
|
||||
`else
|
||||
.wrreq( &RandomNumber1[10:9] ),
|
||||
.data( RandomNumber1[15:0] ),
|
||||
|
||||
.rdreq( &RandomNumber1[8:7] ),
|
||||
.q( data_out2[15:0] ),
|
||||
`endif
|
||||
|
||||
.empty ( empty2 ),
|
||||
.full ( full2 ),
|
||||
.usedw ( )
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
//==============================================================================
|
||||
|
||||
logic outputs_equal;
|
||||
assign outputs_equal = ( data_out1[15:0] == data_out2[15:0] ) ||
|
||||
`ifdef TEST_FWFT
|
||||
// scipping minor discontinuity
|
||||
// seems like altera`s fifo has some additional buffering???
|
||||
( cnt1[3:0] == 1 && data_out1[15:0] != data_out2[15:0] );
|
||||
`else
|
||||
1'b0;
|
||||
`endif
|
||||
|
||||
logic empty_equal;
|
||||
assign empty_equal = ( empty1 == empty2 );
|
||||
|
||||
logic full_equal;
|
||||
assign full_equal = ( full1 == full2 );
|
||||
|
||||
logic success = 1'b1;
|
||||
always_ff @(posedge clk200) begin
|
||||
if( ~nrst ) begin
|
||||
success <= 1'b1;
|
||||
end else begin
|
||||
if( ~outputs_equal ) begin
|
||||
success <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// this condition is being processed differently by altera`s scfifo and
|
||||
// the custom fifo implementation
|
||||
logic test_cond;
|
||||
assign test_cond = empty1 && &RandomNumber1[10:9] && &RandomNumber1[8:7];
|
||||
|
||||
endmodule
|
||||
109
fifo_tb.sv
109
fifo_tb.sv
@ -1,109 +0,0 @@
|
||||
//------------------------------------------------------------------------------
|
||||
// fifo_tb.sv
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// INFO ------------------------------------------------------------------------
|
||||
// testbench for fifo.sv module
|
||||
//
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module fifo_tb();
|
||||
|
||||
logic clk200;
|
||||
initial begin
|
||||
#0 clk200 = 1;
|
||||
forever
|
||||
#2.5 clk200 = ~clk200;
|
||||
end
|
||||
|
||||
logic rst;
|
||||
initial begin
|
||||
#10.2 rst = 1;
|
||||
#5 rst = 0;
|
||||
//#10000;
|
||||
forever begin
|
||||
#9985 rst = ~rst;
|
||||
#5 rst = ~rst;
|
||||
end
|
||||
end
|
||||
|
||||
logic nrst;
|
||||
assign nrst = ~rst;
|
||||
|
||||
logic rst_once;
|
||||
initial begin // initializing non-X data before PLL starts
|
||||
#10.2 rst_once = 1;
|
||||
#5 rst_once = 0;
|
||||
end
|
||||
initial begin
|
||||
#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
|
||||
#5 rst_once = 0;
|
||||
end
|
||||
|
||||
logic nrst_once;
|
||||
assign nrst_once = ~rst_once;
|
||||
|
||||
logic [31:0] DerivedClocks;
|
||||
ClkDivider #(
|
||||
.WIDTH( 32 )
|
||||
) CD1 (
|
||||
.clk( clk200 ),
|
||||
.nrst( nrst_once ),
|
||||
.out( DerivedClocks[31:0] )
|
||||
);
|
||||
|
||||
logic [31:0] E_DerivedClocks;
|
||||
EdgeDetect ED1[31:0] (
|
||||
.clk( {32{clk200}} ),
|
||||
.nrst( {32{nrst_once}} ),
|
||||
.in( DerivedClocks[31:0] ),
|
||||
.rising( E_DerivedClocks[31:0] ),
|
||||
.falling( ),
|
||||
.both( )
|
||||
);
|
||||
|
||||
logic [15:0] RandomNumber1;
|
||||
c_rand RNG1 (
|
||||
.clk(clk200),
|
||||
.rst(rst_once),
|
||||
.reseed(1'b0),
|
||||
.seed_val(DerivedClocks[31:0]),
|
||||
.out(RandomNumber1[15:0]));
|
||||
|
||||
/*logic start;
|
||||
initial begin
|
||||
#0 start = 1'b0;
|
||||
#100.2 start = 1'b1;
|
||||
#5 start = 1'b0;
|
||||
end*/
|
||||
|
||||
logic read;
|
||||
initial begin
|
||||
#0 read = 1'b0;
|
||||
#1000.2 read = 1'b1;
|
||||
end
|
||||
|
||||
|
||||
|
||||
fifo #(
|
||||
.DEPTH( 8 ),
|
||||
.DATA_W( 16 )
|
||||
) FF1 (
|
||||
.clk( clk200 ),
|
||||
.rst( rst_once ),
|
||||
|
||||
.w_req( &RandomNumber1[10:9] ),
|
||||
.w_data( RandomNumber1[15:0] ),
|
||||
|
||||
.r_req( read ),
|
||||
.r_data( ),
|
||||
|
||||
.cnt( ),
|
||||
.empty( ),
|
||||
.full( )
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user