HLS template project and scripts update

example_projects/vitis_hls_test_prj_template_v1/hls_operator.cpp

@@ -1,19 +0,0 @@
-//------------------------------------------------------------------------------
-// published as part of https://github.com/pConst/basic_verilog
-// Konstantin Pavlov, pavlovconst@gmail.com
-//------------------------------------------------------------------------------
-
-#include "hls_operator.h"
-
-int hls_operator( int a, int b ) {
-
-  #pragma HLS DATAFLOW
-
-  static int delta = 1;
-
-  int result = a + b + delta;
-  delta++;
-
-  return result;
-}
-

example_projects/vitis_hls_test_prj_template_v1/hls_operator.h

@@ -1,9 +0,0 @@
-//------------------------------------------------------------------------------
-// published as part of https://github.com/pConst/basic_verilog
-// Konstantin Pavlov, pavlovconst@gmail.com
-//------------------------------------------------------------------------------
-
-#include "ap_int.h"
-
-int hls_operator(int a, int b);
-

example_projects/vitis_hls_test_prj_template_v2/.gitignore

@@ -0,0 +1,14 @@
+#------------------------------------------------------------------------------
+# .gitignore for Vitis HLS projects
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# INFO ------------------------------------------------------------------------
+# rename the file to ".gitignore" and place into your HLS project directory
+#
+
+/prj
+
+vitis_hls.log
+

example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl

@@ -4,9 +4,9 @@
 #------------------------------------------------------------------------------
 
 # Create a project
-open_project proj -reset
-add_files hls_operator.cpp
-add_files -tb hls_operator_tb.cpp
+open_project prj -reset
+add_files src/hls_operator.cpp
+add_files -tb src/hls_operator_tb.cpp
 set_top hls_operator
 
 # Create a solution

example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp

@@ -0,0 +1,27 @@
+//------------------------------------------------------------------------------
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+#include "ap_int.h"
+#include "hls_stream.h"
+
+void hls_operator(
+  hls::stream<int> &a,
+  hls::stream<int> &b,
+  hls::stream<int> &c,
+  hls::stream<int> &d
+){
+
+  #pragma HLS DATAFLOW disable_start_propagation
+  #pragma HLS INTERFACE mode=ap_ctrl_none port=return
+
+  #pragma HLS INTERFACE port=a ap_fifo
+  #pragma HLS INTERFACE port=b axis
+  #pragma HLS INTERFACE port=c ap_fifo
+  #pragma HLS INTERFACE port=d axis
+
+  c.write( a.read() + b.read() );
+  d.write( a.read() - b.read() );
+}
+

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_clean.sh

@@ -7,7 +7,7 @@
 # Script to clean Vitis HLS project
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-rm -rf proj
+rm -rf prj
 
 rm vitis_hls.log
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_cosim.sh

@@ -8,7 +8,7 @@
 # Script to perform HLS component co-simulation
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csim.sh

@@ -8,7 +8,7 @@
 # Script to perform HLS component simulation
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh

@@ -0,0 +1,22 @@
+#! /usr/bin/env bash
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to initialize HLS project solution and make CSYNTH compilation step
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+
+
+rm -rf ./prj/sol1/syn
+rm -rf ./prj/sol1/impl
+
+vitis_hls -f run_hls.tcl
+
+# open top Verilog
+subl ./prj/sol1/syn/verilog/hls_operator.v
+
+# open main report
+subl ./prj/sol1/syn/report/csynth.rpt
+

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_export.sh

@@ -8,7 +8,7 @@
 # Script to export HLS component to Vivado IP catalog
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_gui.sh

@@ -8,9 +8,9 @@
 # Script to open Vitis HLS GUI
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 
-vitis_hls -p proj
+nohup vitis_hls -p prj &> /dev/null & disown
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh

@@ -8,7 +8,7 @@
 # Script to perform HLS IP synthesis and implementation
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_killall.sh

@@ -1,11 +1,12 @@
 #! /usr/bin/env bash
+
 #------------------------------------------------------------------------------
 # published as part of https://github.com/pConst/basic_verilog
 # Konstantin Pavlov, pavlovconst@gmail.com
 #------------------------------------------------------------------------------
 
-# Script to initialize HLS project solution and make CSYNTH compilation step
+# Script to open Vitis HLS GUI
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-vitis_hls -f run_hls.tcl
+killall vitis_hls
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh

@@ -8,7 +8,7 @@
 # Script to perform HLS IP synthesis
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

gitignores/.gitignore_vitis_hls

@@ -0,0 +1,14 @@
+#------------------------------------------------------------------------------
+# .gitignore for Vitis HLS projects
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# INFO ------------------------------------------------------------------------
+# rename the file to ".gitignore" and place into your HLS project directory
+#
+
+/prj
+
+vitis_hls.log
+

scripts_for_xilinx_hls/run_hls.tcl

@@ -4,9 +4,9 @@
 #------------------------------------------------------------------------------
 
 # Create a project
-open_project proj -reset
-add_files hls_operator.cpp
-add_files -tb hls_operator_tb.cpp
+open_project prj -reset
+add_files src/hls_operator.cpp
+add_files -tb src/hls_operator_tb.cpp
 set_top hls_operator
 
 # Create a solution

scripts_for_xilinx_hls/vitis_hls_clean.sh

@@ -7,7 +7,7 @@
 # Script to clean Vitis HLS project
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-rm -rf proj
+rm -rf prj
 
 rm vitis_hls.log
 

scripts_for_xilinx_hls/vitis_hls_cosim.sh

@@ -8,7 +8,7 @@
 # Script to perform HLS component co-simulation
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

scripts_for_xilinx_hls/vitis_hls_csim.sh

@@ -8,7 +8,7 @@
 # Script to perform HLS component simulation
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

scripts_for_xilinx_hls/vitis_hls_csynth.sh

@@ -7,5 +7,16 @@
 # Script to initialize HLS project solution and make CSYNTH compilation step
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
+
+
+rm -rf ./prj/sol1/syn
+rm -rf ./prj/sol1/impl
+
 vitis_hls -f run_hls.tcl
 
+# open top Verilog
+subl ./prj/sol1/syn/verilog/hls_operator.v
+
+# open main report
+subl ./prj/sol1/syn/report/csynth.rpt
+

scripts_for_xilinx_hls/vitis_hls_export.sh

@@ -8,7 +8,7 @@
 # Script to export HLS component to Vivado IP catalog
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

scripts_for_xilinx_hls/vitis_hls_gui.sh

@@ -8,9 +8,9 @@
 # Script to open Vitis HLS GUI
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 
-vitis_hls -p proj
+nohup vitis_hls -p prj &> /dev/null & disown
 

scripts_for_xilinx_hls/vitis_hls_impl.sh

@@ -8,7 +8,7 @@
 # Script to perform HLS IP synthesis and implementation
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 

scripts_for_xilinx_hls/vitis_hls_killall.sh

@@ -0,0 +1,12 @@
+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to open Vitis HLS GUI
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+killall vitis_hls
+

scripts_for_xilinx_hls/vitis_hls_syn.sh

@@ -8,7 +8,7 @@
 # Script to perform HLS IP synthesis
 # see ../example_projects/vitis_hls_prj_template_v1/ for complete example
 
-if [ ! -d "./proj" ]; then
+if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi