diff --git a/example_projects/vitis_hls_test_prj_template_v1/hls_operator.cpp b/example_projects/vitis_hls_test_prj_template_v1/hls_operator.cpp deleted file mode 100644 index 0e3065b..0000000 --- a/example_projects/vitis_hls_test_prj_template_v1/hls_operator.cpp +++ /dev/null @@ -1,19 +0,0 @@ -//------------------------------------------------------------------------------ -// published as part of https://github.com/pConst/basic_verilog -// Konstantin Pavlov, pavlovconst@gmail.com -//------------------------------------------------------------------------------ - -#include "hls_operator.h" - -int hls_operator( int a, int b ) { - - #pragma HLS DATAFLOW - - static int delta = 1; - - int result = a + b + delta; - delta++; - - return result; -} - diff --git a/example_projects/vitis_hls_test_prj_template_v1/hls_operator.h b/example_projects/vitis_hls_test_prj_template_v1/hls_operator.h deleted file mode 100644 index cbea306..0000000 --- a/example_projects/vitis_hls_test_prj_template_v1/hls_operator.h +++ /dev/null @@ -1,9 +0,0 @@ -//------------------------------------------------------------------------------ -// published as part of https://github.com/pConst/basic_verilog -// Konstantin Pavlov, pavlovconst@gmail.com -//------------------------------------------------------------------------------ - -#include "ap_int.h" - -int hls_operator(int a, int b); - diff --git a/example_projects/vitis_hls_test_prj_template_v2/.gitignore b/example_projects/vitis_hls_test_prj_template_v2/.gitignore new file mode 100644 index 0000000..d023ac5 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/.gitignore @@ -0,0 +1,14 @@ +#------------------------------------------------------------------------------ +# .gitignore for Vitis HLS projects +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# INFO ------------------------------------------------------------------------ +# rename the file to ".gitignore" and place into your HLS project directory +# + +/prj + +vitis_hls.log + diff --git a/example_projects/vitis_hls_test_prj_template_v1/run_hls.tcl b/example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl similarity index 87% rename from example_projects/vitis_hls_test_prj_template_v1/run_hls.tcl rename to example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl index 9b94f5d..c4d1557 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/run_hls.tcl +++ b/example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl @@ -4,9 +4,9 @@ #------------------------------------------------------------------------------ # Create a project -open_project proj -reset -add_files hls_operator.cpp -add_files -tb hls_operator_tb.cpp +open_project prj -reset +add_files src/hls_operator.cpp +add_files -tb src/hls_operator_tb.cpp set_top hls_operator # Create a solution diff --git a/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp new file mode 100644 index 0000000..409a07b --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp @@ -0,0 +1,27 @@ +//------------------------------------------------------------------------------ +// published as part of https://github.com/pConst/basic_verilog +// Konstantin Pavlov, pavlovconst@gmail.com +//------------------------------------------------------------------------------ + +#include "ap_int.h" +#include "hls_stream.h" + +void hls_operator( + hls::stream &a, + hls::stream &b, + hls::stream &c, + hls::stream &d +){ + + #pragma HLS DATAFLOW disable_start_propagation + #pragma HLS INTERFACE mode=ap_ctrl_none port=return + + #pragma HLS INTERFACE port=a ap_fifo + #pragma HLS INTERFACE port=b axis + #pragma HLS INTERFACE port=c ap_fifo + #pragma HLS INTERFACE port=d axis + + c.write( a.read() + b.read() ); + d.write( a.read() - b.read() ); +} + diff --git a/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.h b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.h new file mode 100644 index 0000000..e69de29 diff --git a/example_projects/vitis_hls_test_prj_template_v1/hls_operator_tb.cpp b/example_projects/vitis_hls_test_prj_template_v2/src/hls_operator_tb.cpp similarity index 100% rename from example_projects/vitis_hls_test_prj_template_v1/hls_operator_tb.cpp rename to example_projects/vitis_hls_test_prj_template_v2/src/hls_operator_tb.cpp diff --git a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_clean.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_clean.sh similarity index 97% rename from example_projects/vitis_hls_test_prj_template_v1/vitis_hls_clean.sh rename to example_projects/vitis_hls_test_prj_template_v2/vitis_hls_clean.sh index 4ed111d..03828d8 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_clean.sh +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_clean.sh @@ -7,7 +7,7 @@ # Script to clean Vitis HLS project # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -rm -rf proj +rm -rf prj rm vitis_hls.log diff --git a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_cosim.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_cosim.sh similarity index 94% rename from example_projects/vitis_hls_test_prj_template_v1/vitis_hls_cosim.sh rename to example_projects/vitis_hls_test_prj_template_v2/vitis_hls_cosim.sh index 4b5ac3e..2594fbc 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_cosim.sh +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_cosim.sh @@ -8,7 +8,7 @@ # Script to perform HLS component co-simulation # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csim.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csim.sh similarity index 94% rename from example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csim.sh rename to example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csim.sh index 29bbcc9..8b37325 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csim.sh +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csim.sh @@ -8,7 +8,7 @@ # Script to perform HLS component simulation # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh new file mode 100644 index 0000000..9f4d115 --- /dev/null +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh @@ -0,0 +1,22 @@ +#! /usr/bin/env bash +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to initialize HLS project solution and make CSYNTH compilation step +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + + + +rm -rf ./prj/sol1/syn +rm -rf ./prj/sol1/impl + +vitis_hls -f run_hls.tcl + +# open top Verilog +subl ./prj/sol1/syn/verilog/hls_operator.v + +# open main report +subl ./prj/sol1/syn/report/csynth.rpt + diff --git a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_export.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_export.sh similarity index 95% rename from example_projects/vitis_hls_test_prj_template_v1/vitis_hls_export.sh rename to example_projects/vitis_hls_test_prj_template_v2/vitis_hls_export.sh index 0aaea0c..5fc713b 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_export.sh +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_export.sh @@ -8,7 +8,7 @@ # Script to export HLS component to Vivado IP catalog # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/scripts_for_xilinx_hls/vitis_hls_open_gui.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_gui.sh similarity index 85% rename from scripts_for_xilinx_hls/vitis_hls_open_gui.sh rename to example_projects/vitis_hls_test_prj_template_v2/vitis_hls_gui.sh index e3c827c..ca0149d 100644 --- a/scripts_for_xilinx_hls/vitis_hls_open_gui.sh +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_gui.sh @@ -8,9 +8,9 @@ # Script to open Vitis HLS GUI # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi -vitis_hls -p proj +nohup vitis_hls -p prj &> /dev/null & disown diff --git a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_impl.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh similarity index 95% rename from example_projects/vitis_hls_test_prj_template_v1/vitis_hls_impl.sh rename to example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh index 307b12e..d8fe3e9 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_impl.sh +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh @@ -8,7 +8,7 @@ # Script to perform HLS IP synthesis and implementation # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csynth.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_killall.sh similarity index 78% rename from example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csynth.sh rename to example_projects/vitis_hls_test_prj_template_v2/vitis_hls_killall.sh index d3af678..fe86a29 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csynth.sh +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_killall.sh @@ -1,11 +1,12 @@ #! /usr/bin/env bash + #------------------------------------------------------------------------------ # published as part of https://github.com/pConst/basic_verilog # Konstantin Pavlov, pavlovconst@gmail.com #------------------------------------------------------------------------------ -# Script to initialize HLS project solution and make CSYNTH compilation step +# Script to open Vitis HLS GUI # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -vitis_hls -f run_hls.tcl +killall vitis_hls diff --git a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_syn.sh b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh similarity index 94% rename from example_projects/vitis_hls_test_prj_template_v1/vitis_hls_syn.sh rename to example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh index ad7e2e9..0ac5c8f 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_syn.sh +++ b/example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh @@ -8,7 +8,7 @@ # Script to perform HLS IP synthesis # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/gitignores/.gitignore_vitis_hls b/gitignores/.gitignore_vitis_hls new file mode 100644 index 0000000..d023ac5 --- /dev/null +++ b/gitignores/.gitignore_vitis_hls @@ -0,0 +1,14 @@ +#------------------------------------------------------------------------------ +# .gitignore for Vitis HLS projects +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# INFO ------------------------------------------------------------------------ +# rename the file to ".gitignore" and place into your HLS project directory +# + +/prj + +vitis_hls.log + diff --git a/scripts_for_xilinx_hls/run_hls.tcl b/scripts_for_xilinx_hls/run_hls.tcl index 9b94f5d..c4d1557 100644 --- a/scripts_for_xilinx_hls/run_hls.tcl +++ b/scripts_for_xilinx_hls/run_hls.tcl @@ -4,9 +4,9 @@ #------------------------------------------------------------------------------ # Create a project -open_project proj -reset -add_files hls_operator.cpp -add_files -tb hls_operator_tb.cpp +open_project prj -reset +add_files src/hls_operator.cpp +add_files -tb src/hls_operator_tb.cpp set_top hls_operator # Create a solution diff --git a/scripts_for_xilinx_hls/vitis_hls_clean.sh b/scripts_for_xilinx_hls/vitis_hls_clean.sh index 4ed111d..03828d8 100644 --- a/scripts_for_xilinx_hls/vitis_hls_clean.sh +++ b/scripts_for_xilinx_hls/vitis_hls_clean.sh @@ -7,7 +7,7 @@ # Script to clean Vitis HLS project # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -rm -rf proj +rm -rf prj rm vitis_hls.log diff --git a/scripts_for_xilinx_hls/vitis_hls_cosim.sh b/scripts_for_xilinx_hls/vitis_hls_cosim.sh index 4b5ac3e..2594fbc 100644 --- a/scripts_for_xilinx_hls/vitis_hls_cosim.sh +++ b/scripts_for_xilinx_hls/vitis_hls_cosim.sh @@ -8,7 +8,7 @@ # Script to perform HLS component co-simulation # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/scripts_for_xilinx_hls/vitis_hls_csim.sh b/scripts_for_xilinx_hls/vitis_hls_csim.sh index 29bbcc9..8b37325 100644 --- a/scripts_for_xilinx_hls/vitis_hls_csim.sh +++ b/scripts_for_xilinx_hls/vitis_hls_csim.sh @@ -8,7 +8,7 @@ # Script to perform HLS component simulation # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/scripts_for_xilinx_hls/vitis_hls_csynth.sh b/scripts_for_xilinx_hls/vitis_hls_csynth.sh index d3af678..9f4d115 100644 --- a/scripts_for_xilinx_hls/vitis_hls_csynth.sh +++ b/scripts_for_xilinx_hls/vitis_hls_csynth.sh @@ -7,5 +7,16 @@ # Script to initialize HLS project solution and make CSYNTH compilation step # see ../example_projects/vitis_hls_prj_template_v1/ for complete example + + +rm -rf ./prj/sol1/syn +rm -rf ./prj/sol1/impl + vitis_hls -f run_hls.tcl +# open top Verilog +subl ./prj/sol1/syn/verilog/hls_operator.v + +# open main report +subl ./prj/sol1/syn/report/csynth.rpt + diff --git a/scripts_for_xilinx_hls/vitis_hls_export.sh b/scripts_for_xilinx_hls/vitis_hls_export.sh index 0aaea0c..5fc713b 100644 --- a/scripts_for_xilinx_hls/vitis_hls_export.sh +++ b/scripts_for_xilinx_hls/vitis_hls_export.sh @@ -8,7 +8,7 @@ # Script to export HLS component to Vivado IP catalog # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_open_gui.sh b/scripts_for_xilinx_hls/vitis_hls_gui.sh similarity index 85% rename from example_projects/vitis_hls_test_prj_template_v1/vitis_hls_open_gui.sh rename to scripts_for_xilinx_hls/vitis_hls_gui.sh index e3c827c..ca0149d 100644 --- a/example_projects/vitis_hls_test_prj_template_v1/vitis_hls_open_gui.sh +++ b/scripts_for_xilinx_hls/vitis_hls_gui.sh @@ -8,9 +8,9 @@ # Script to open Vitis HLS GUI # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi -vitis_hls -p proj +nohup vitis_hls -p prj &> /dev/null & disown diff --git a/scripts_for_xilinx_hls/vitis_hls_impl.sh b/scripts_for_xilinx_hls/vitis_hls_impl.sh index 307b12e..d8fe3e9 100644 --- a/scripts_for_xilinx_hls/vitis_hls_impl.sh +++ b/scripts_for_xilinx_hls/vitis_hls_impl.sh @@ -8,7 +8,7 @@ # Script to perform HLS IP synthesis and implementation # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi diff --git a/scripts_for_xilinx_hls/vitis_hls_killall.sh b/scripts_for_xilinx_hls/vitis_hls_killall.sh new file mode 100644 index 0000000..fe86a29 --- /dev/null +++ b/scripts_for_xilinx_hls/vitis_hls_killall.sh @@ -0,0 +1,12 @@ +#! /usr/bin/env bash + +#------------------------------------------------------------------------------ +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com +#------------------------------------------------------------------------------ + +# Script to open Vitis HLS GUI +# see ../example_projects/vitis_hls_prj_template_v1/ for complete example + +killall vitis_hls + diff --git a/scripts_for_xilinx_hls/vitis_hls_syn.sh b/scripts_for_xilinx_hls/vitis_hls_syn.sh index ad7e2e9..0ac5c8f 100644 --- a/scripts_for_xilinx_hls/vitis_hls_syn.sh +++ b/scripts_for_xilinx_hls/vitis_hls_syn.sh @@ -8,7 +8,7 @@ # Script to perform HLS IP synthesis # see ../example_projects/vitis_hls_prj_template_v1/ for complete example -if [ ! -d "./proj" ]; then +if [ ! -d "./prj" ]; then source vitis_hls_csynth.sh fi