Added Wishbone interface

interfaces/axi4_if.sv

@@ -77,7 +77,7 @@ interface axi4_if #( parameter
   logic                wvalid;
 
 
-  modport master(
+  modport master_mp(
 
     input arready,
     input awready,
@@ -128,7 +128,7 @@ interface axi4_if #( parameter
   );
 
 
-  modport slave(
+  modport slave_mp(
 
     input araddr,
     input arburst,

interfaces/axis_if.sv

@@ -17,17 +17,19 @@ interface axis_if #( parameter
 );
 
 
-  logic [ DATA_W-1:0   ] tdata;
+  localparam KEEP_W = DATA_W/8;
-  logic [ ID_W-1:0     ] tdest;
+
-  logic [ ID_W-1:0     ] tid;
+  logic [DATA_W-1:0] tdata;
-  logic [ DATA_W/8-1:0 ] tkeep;
+  logic [  ID_W-1:0] tdest;
-  logic                  tlast;
+  logic [  ID_W-1:0] tid;
-  logic                  tready;
+  logic [KEEP_W-1:0] tkeep;
-  logic [ USER_W-1:0   ] tuser;
+  logic              tlast;
-  logic                  tvalid;
+  logic              tready;
+  logic [USER_W-1:0] tuser;
+  logic              tvalid;
 
 
-  modport master(
+  modport master_mp(
 
     input  tready,
 
@@ -41,7 +43,7 @@ interface axis_if #( parameter
   );
 
 
-  modport slave(
+  modport slave_mp(
 
     input tdata,
     input tdest,

interfaces/wb_if.sv

@@ -0,0 +1,69 @@
+//------------------------------------------------------------------------------
+// wb_if.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+
+// INFO ------------------------------------------------------------------------
+// Wishbone instantiation
+//
+
+
+interface wb_if #( parameter
+  ADDR_W = 32,
+  DATA_W = 32,
+  SEL_W  = 4
+  //TAG_W  = 4
+);
+
+
+  logic              ack;
+  logic [ADDR_W-1:0] adr;
+  logic              cyc;
+  logic [DATA_W-1:0] dat;
+  logic [DATA_W-1:0] dat;
+  logic              err;
+  logic              rty;
+  logic [ SEL_W-1:0] sel;
+  logic              stb;
+  //logic [ TAG_W-1:0] tgd; // user-defined TAG signals
+  logic              we;
+
+
+  modport master_mp(
+
+    input ack,
+    input dat,
+    input err,
+    input rty,
+
+    output adr,
+    output cyc,
+    output dat,
+    output sel,
+    output stb,
+    //output tgd,
+    output we
+  );
+
+
+  modport slave_mp(
+
+    input adr,
+    input cyc,
+    input dat,
+    input sel,
+    input stb,
+    //input tgd,
+    input we,
+
+    output ack,
+    output dat,
+    output err,
+    output rty
+  );
+
+
+endinterface
+