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https://github.com/pConst/basic_verilog.git
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Added pulse generator modules
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Konstantin Pavlov (pt)
parent
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commit
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32
DynDelay.v
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32
DynDelay.v
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//--------------------------------------------------------------------------------
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// DynDelay.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//
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//(* keep_hierarchy = "yes" *)
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module DynDelay(clk, in, sel, out);
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input wire clk;
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input wire in;
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input wire [(LENGTH-1):0] sel; // output selector
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output reg out;
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parameter LENGTH = 8;
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(* keep = "true" *) reg [(LENGTH-1):0] data = 0;
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integer i;
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always @ (posedge clk) begin
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data[0] <= in;
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for (i=1; i<LENGTH; i=i+1) begin
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data[i] <= data[i-1];
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end
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out <= data[sel[(LENGTH-1):0]];
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end
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endmodule
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50
Main_TB.v
50
Main_TB.v
@ -1,5 +1,5 @@
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//--------------------------------------------------------------------------------
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// Counter project, 201512
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// ***** project, 201512
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// Main_TB.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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@ -10,48 +10,52 @@
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`timescale 1ns / 1ps
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module Main_TB();
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module Main_tb();
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reg TB_clk200;
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reg clk200;
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initial begin
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#0 TB_clk200 = 0;
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#0 clk200 = 1;
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forever
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#5 TB_clk200 = ~TB_clk200;
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#2.5 clk200 = ~clk200;
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end
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reg TB_rst;
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reg rst;
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initial begin
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#40 TB_rst = 1;
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#10 TB_rst = 0;
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#10.2 rst = 1;
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#5 rst = 0;
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//#10000;
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forever begin
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#9950 TB_rst = ~TB_rst;
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#50 TB_rst = ~TB_rst;
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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wire [31:0] TB_DerivedClocks;
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wire [31:0] DerivedClocks;
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ClkDivider CD1 (
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.clk(TB_clk200),
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.clk(clk200),
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.nrst(1'b1),
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.out(TB_DerivedClocks[31:0]));
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.out(DerivedClocks[31:0]));
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defparam CD1.WIDTH = 32;
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wire [15:0] TB_RandomNumber1;
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reg TB_rst1;
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wire [15:0] RandomNumber1;
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reg rst1;
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initial begin
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#40 TB_rst1 = 1;
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#10 TB_rst1 = 0;
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#10.2 rst1 = 1;
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#5 rst1 = 0;
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end
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c_rand RNG1 (
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.clk(TB_clk200),
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.rst(TB_rst1),
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.clk(clk200),
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.rst(rst1),
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.reseed(1'b0),
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.seed_val(TB_DerivedClocks[15:0]),
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.out(TB_RandomNumber1[15:0]));
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.seed_val(DerivedClocks[15:0]),
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.out(RandomNumber1[15:0]));
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reg start;
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initial begin
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#100.2 start = 1;
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#5 start = 0;
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end
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wire out1,out2;
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Main M( // module under test
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76
PulseGen.v
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76
PulseGen.v
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//--------------------------------------------------------------------------------
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// PulseGen.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD> low_wdth = 1, high_wdth = 1
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module PulseGen(clk,nrst,low_wdth,high_wdth,rpt,start,busy,out);
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input wire clk;
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input wire nrst;
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input wire [31:0] low_wdth;
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input wire [31:0] high_wdth;
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input wire rpt;
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input wire start; // Only first front matters
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output reg busy = 0;
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output reg out = 0;
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reg rpt_buf = 0;
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reg [31:0] max_low = 0;
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reg [31:0] max_high = 0;
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reg [31:0] cnt_low = 0;
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reg [31:0] cnt_high = 0;
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always @ (posedge clk) begin
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if (~nrst) begin // one and only way to stop PulseGen is to reset it
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rpt_buf <= 0;
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max_low[31:0] <= 0;
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max_high[31:0] <= 0;
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cnt_low[31:0] <= 0;
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cnt_high[31:0] <= 0;
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busy <= 0;
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out <= 0;
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end
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else begin // nrst
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if (~busy) begin
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if (start) begin // buffering input values
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busy <= 1;
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rpt_buf <= rpt;
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max_low[31:0] <= low_wdth[31:0];
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max_high[31:0] <= high_wdth[31:0];
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cnt_low[31:0] <= 0;
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cnt_high[31:0] <= 0;
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end
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end
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else begin
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if (cnt_low[31:0] < (max_low[31:0]-1)) begin // compensation for firs initialization cycle
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out <= 0;
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cnt_low[31:0] <= cnt_low[31:0] + 1;
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end
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else begin
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out <= 1;
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if (cnt_high[31:0] < max_high[31:0]) begin
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cnt_high[31:0] <= cnt_high[31:0] + 1;
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end
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else begin
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out <= 0;
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if (rpt_buf) begin
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cnt_low[31:0] <= 0;
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cnt_high[31:0] <= 0;
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end
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else begin
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busy <= 0; // end of sequence
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end
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end // cnt_high
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end // cnt_low
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end // busy
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end // nrst
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end
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endmodule
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57
SimplePulseGen.v
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57
SimplePulseGen.v
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//--------------------------------------------------------------------------------
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// SimplePulseGen.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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module SimplePulseGen(clk,nrst,low_wdth,start,busy,out);
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input wire clk;
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input wire nrst;
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input wire [31:0] low_wdth;
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input wire start;
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output reg busy = 0;
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output reg out = 0;
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reg [31:0] max_low = 0;
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reg [31:0] cnt_low = 0;
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always @ (posedge clk) begin
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if (~nrst) begin // one and only way to stop SimplePulseGen is to reset it
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max_low[31:0] <= 0;
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cnt_low[31:0] <= 0;
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busy <= 0;
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out <= 0;
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end
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else begin // nrst
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if (~busy) begin
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if (start) begin // buffering input values
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max_low[31:0] <= low_wdth[31:0];
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cnt_low[31:0] <= 0;
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busy <= 1;
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end
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end
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else begin
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if (cnt_low[31:0] < (max_low[31:0]-1)) begin // compensation for firs initialization cycle
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out <= 0;
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cnt_low[31:0] <= cnt_low[31:0] + 1;
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end
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else begin
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if (~out) begin
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out <= 1;
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end
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else begin
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busy <= 0;
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out <= 0;
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end // out
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end // cnt_low
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end // busy
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end // nrst
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end
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endmodule
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23
Synch.v
23
Synch.v
@ -7,27 +7,24 @@
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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(* keep_hierarchy = "yes" *) module Synch(clk, in, out);
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//(* keep_hierarchy = "yes" *)
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module Synch(clk, in, out); // aka "static delay"
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input wire clk;
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input wire in;
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output wire out;
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input wire [(WIDTH-1):0] in;
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output wire [(WIDTH-1):0] out;
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parameter LENGTH = 2; // length of each sincronizer chain
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//parameter WIDTH = 1; // independent channels
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parameter LENGTH = 2; // length of each synchronizer chain
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parameter WIDTH = 1; // independent channels
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//(* keep = "true" *)
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reg [(LENGTH-1):0] data = 0;
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integer i;
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(* keep = "true" *) reg [(LENGTH*WIDTH-1):0] data = 0;
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always @ (posedge clk) begin
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data[0] <= in;
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for (i=1; i<LENGTH; i=i+1) begin
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data[i] <= data[i-1];
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end
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data[(LENGTH*WIDTH-1):0] << WIDTH;
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data[(WIDTH-1):0] <= in[(WIDTH-1):0];
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end
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assign
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out = data[LENGTH-1];
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out[(WIDTH-1):0] = data[(LENGTH*WIDTH-1):(((LENGTH-1)*WIDTH)];
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endmodule
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