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Added pulse generator modules

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Konstantin Pavlov (pt) 2015-12-24 19:05:06 +03:00
parent df4a0b222c
commit 4a5b91219e
5 changed files with 202 additions and 36 deletions
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32
DynDelay.v Normal file
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//--------------------------------------------------------------------------------
// DynDelay.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//
//(* keep_hierarchy = "yes" *)
module DynDelay(clk, in, sel, out);
input wire clk;
input wire in;
input wire [(LENGTH-1):0] sel; // output selector
output reg out;
parameter LENGTH = 8;
(* keep = "true" *) reg [(LENGTH-1):0] data = 0;
integer i;
always @ (posedge clk) begin
data[0] <= in;
for (i=1; i<LENGTH; i=i+1) begin
data[i] <= data[i-1];
end
out <= data[sel[(LENGTH-1):0]];
end
endmodule

50
Main_TB.v
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//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// Counter project, 201512 // ***** project, 201512
// Main_TB.v // Main_TB.v
// Konstantin Pavlov, pavlovconst@gmail.com // Konstantin Pavlov, pavlovconst@gmail.com
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
@ -10,48 +10,52 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module Main_TB(); module Main_tb();
reg TB_clk200; reg clk200;
initial begin initial begin
#0 TB_clk200 = 0; #0 clk200 = 1;
forever forever
#5 TB_clk200 = ~TB_clk200; #2.5 clk200 = ~clk200;
end end
reg TB_rst; reg rst;
initial begin initial begin
#40 TB_rst = 1; #10.2 rst = 1;
#10 TB_rst = 0; #5 rst = 0;
//#10000; //#10000;
forever begin forever begin
#9950 TB_rst = ~TB_rst; #9985 rst = ~rst;
#50 TB_rst = ~TB_rst; #5 rst = ~rst;
end end
end end
wire [31:0] TB_DerivedClocks; wire [31:0] DerivedClocks;
ClkDivider CD1 ( ClkDivider CD1 (
.clk(TB_clk200), .clk(clk200),
.nrst(1'b1), .nrst(1'b1),
.out(TB_DerivedClocks[31:0])); .out(DerivedClocks[31:0]));
defparam CD1.WIDTH = 32; defparam CD1.WIDTH = 32;
wire [15:0] RandomNumber1;
reg rst1;
wire [15:0] TB_RandomNumber1;
reg TB_rst1;
initial begin initial begin
#40 TB_rst1 = 1; #10.2 rst1 = 1;
#10 TB_rst1 = 0; #5 rst1 = 0;
end end
c_rand RNG1 ( c_rand RNG1 (
.clk(TB_clk200), .clk(clk200),
.rst(TB_rst1), .rst(rst1),
.reseed(1'b0), .reseed(1'b0),
.seed_val(TB_DerivedClocks[15:0]), .seed_val(DerivedClocks[15:0]),
.out(TB_RandomNumber1[15:0])); .out(RandomNumber1[15:0]));
reg start;
initial begin
#100.2 start = 1;
#5 start = 0;
end
wire out1,out2; wire out1,out2;
Main M( // module under test Main M( // module under test

76
PulseGen.v Normal file
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//--------------------------------------------------------------------------------
// PulseGen.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD> low_wdth = 1, high_wdth = 1
module PulseGen(clk,nrst,low_wdth,high_wdth,rpt,start,busy,out);
input wire clk;
input wire nrst;
input wire [31:0] low_wdth;
input wire [31:0] high_wdth;
input wire rpt;
input wire start; // Only first front matters
output reg busy = 0;
output reg out = 0;
reg rpt_buf = 0;
reg [31:0] max_low = 0;
reg [31:0] max_high = 0;
reg [31:0] cnt_low = 0;
reg [31:0] cnt_high = 0;
always @ (posedge clk) begin
if (~nrst) begin // one and only way to stop PulseGen is to reset it
rpt_buf <= 0;
max_low[31:0] <= 0;
max_high[31:0] <= 0;
cnt_low[31:0] <= 0;
cnt_high[31:0] <= 0;
busy <= 0;
out <= 0;
end
else begin // nrst
if (~busy) begin
if (start) begin // buffering input values
busy <= 1;
rpt_buf <= rpt;
max_low[31:0] <= low_wdth[31:0];
max_high[31:0] <= high_wdth[31:0];
cnt_low[31:0] <= 0;
cnt_high[31:0] <= 0;
end
end
else begin
if (cnt_low[31:0] < (max_low[31:0]-1)) begin // compensation for firs initialization cycle
out <= 0;
cnt_low[31:0] <= cnt_low[31:0] + 1;
end
else begin
out <= 1;
if (cnt_high[31:0] < max_high[31:0]) begin
cnt_high[31:0] <= cnt_high[31:0] + 1;
end
else begin
out <= 0;
if (rpt_buf) begin
cnt_low[31:0] <= 0;
cnt_high[31:0] <= 0;
end
else begin
busy <= 0; // end of sequence
end
end // cnt_high
end // cnt_low
end // busy
end // nrst
end
endmodule

57
SimplePulseGen.v Normal file
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//--------------------------------------------------------------------------------
// SimplePulseGen.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,
// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
module SimplePulseGen(clk,nrst,low_wdth,start,busy,out);
input wire clk;
input wire nrst;
input wire [31:0] low_wdth;
input wire start;
output reg busy = 0;
output reg out = 0;
reg [31:0] max_low = 0;
reg [31:0] cnt_low = 0;
always @ (posedge clk) begin
if (~nrst) begin // one and only way to stop SimplePulseGen is to reset it
max_low[31:0] <= 0;
cnt_low[31:0] <= 0;
busy <= 0;
out <= 0;
end
else begin // nrst
if (~busy) begin
if (start) begin // buffering input values
max_low[31:0] <= low_wdth[31:0];
cnt_low[31:0] <= 0;
busy <= 1;
end
end
else begin
if (cnt_low[31:0] < (max_low[31:0]-1)) begin // compensation for firs initialization cycle
out <= 0;
cnt_low[31:0] <= cnt_low[31:0] + 1;
end
else begin
if (~out) begin
out <= 1;
end
else begin
busy <= 0;
out <= 0;
end // out
end // cnt_low
end // busy
end // nrst
end
endmodule

23
Synch.v
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. // <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. // <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
(* keep_hierarchy = "yes" *) module Synch(clk, in, out); //(* keep_hierarchy = "yes" *)
module Synch(clk, in, out); // aka "static delay"
input wire clk; input wire clk;
input wire in; input wire [(WIDTH-1):0] in;
output wire out; output wire [(WIDTH-1):0] out;
parameter LENGTH = 2; // length of each sincronizer chain parameter LENGTH = 2; // length of each synchronizer chain
//parameter WIDTH = 1; // independent channels parameter WIDTH = 1; // independent channels
//(* keep = "true" *) (* keep = "true" *) reg [(LENGTH*WIDTH-1):0] data = 0;
reg [(LENGTH-1):0] data = 0;
integer i;
always @ (posedge clk) begin always @ (posedge clk) begin
data[0] <= in; data[(LENGTH*WIDTH-1):0] << WIDTH;
for (i=1; i<LENGTH; i=i+1) begin data[(WIDTH-1):0] <= in[(WIDTH-1):0];
data[i] <= data[i-1];
end
end end
assign assign
out = data[LENGTH-1]; out[(WIDTH-1):0] = data[(LENGTH*WIDTH-1):(((LENGTH-1)*WIDTH)];
endmodule endmodule