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Minor fixes for Quartus test project

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This commit is contained in:
Konstantin Pavlov 2022-03-30 19:28:46 +03:00
parent a2f57048dc
commit 4c6c8eabb7
1 changed files with 5 additions and 5 deletions
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example_projects/quartus_test_prj_template_v3/src/main.sv
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@ -28,27 +28,27 @@ module main(
logic [`WIDTH-1:0] in_data_reg = 0; logic [`WIDTH-1:0] in_data_reg = 0;
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if( ~nrst ) begin if( ~nrst ) begin
in_data_reg <= '0; in_data_reg[`WIDTH-1:0] <= '0;
end else begin end else begin
in_data_reg <= in_data; in_data_reg[`WIDTH-1:0] <= in_data;
end end
end end
// place your test logic here ================================================== // place your test logic here ==================================================
logic [31:0] divided_clk; logic [31:0] div_clk;
clk_divider #( clk_divider #(
.WIDTH( 32 ) .WIDTH( 32 )
) cd1 ( ) cd1 (
.clk( clk ), .clk( clk ),
.nrst( nrst ), .nrst( nrst ),
.ena( 1'b1 ), .ena( 1'b1 ),
.out( divided_clk[31:0] ) .out( div_clk[31:0] )
); );
logic [`WIDTH-1:0] out_data_comb = 0; logic [`WIDTH-1:0] out_data_comb = 0;
always_comb begin always_comb begin
out_data_comb[`WIDTH-1:0] <= out_data_comb[`WIDTH-1:0] ^ divided_clk[31:0]; out_data_comb[`WIDTH-1:0] <= in_data_reg[`WIDTH-1:0] ^ div_clk[31:0];
end end