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Added universal block RAM fifo
This commit is contained in:
Konstantin Pavlov (ms)
parent
1efbd7c243
commit
4cd95ad2dc
223
fifo_single_clock_ram.sv
Executable file
223
fifo_single_clock_ram.sv
Executable file
@ -0,0 +1,223 @@
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//------------------------------------------------------------------------------
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// fifo_single_clock_ram.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Single-clock FIFO buffer implementation, also known as "queue"
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//
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// This fifo variant should synthesize into block RAM seamlessly, both for
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// Altera and for Xilinx chips. Simulation is also consistent.
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// Use this fifo when you need cross-vendor and sim/synth compatibility.
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//
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// Features:
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// - single clock operation
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// - configurable depth and data width
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// - only "normal" mode is supported here, no FWFT mode
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// - protected against overflow and underflow
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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fifo_single_clock_ram #(
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.DEPTH( 8 ),
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.DATA_W( 32 )
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) FF1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.w_req( ),
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.w_data( ),
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.r_req( ),
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.r_data( ),
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.cnt( ),
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.empty( ),
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.full( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module fifo_single_clock_ram #( parameter
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//FWFT_MODE = "TRUE", // "TRUE" - first word fall-trrough" mode
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// "FALSE" - normal fifo mode
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DEPTH = 8, // max elements count == DEPTH, DEPTH MUST be power of 2
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DEPTH_W = $clog2(DEPTH)+1, // elements counter width, extra bit to store
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// "fifo full" state, see cnt[] variable comments
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DATA_W = 32 // data field width
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)(
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input clk,
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input nrst, // inverted reset
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// input port
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input w_req,
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input [DATA_W-1:0] w_data,
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// output port
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input r_req,
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output [DATA_W-1:0] r_data,
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// helper ports
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output logic [DEPTH_W-1:0] cnt = '0,
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output logic empty,
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output logic full,
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output logic fail
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);
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// read and write pointers
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logic [DEPTH_W-1:0] w_ptr = '0;
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logic [DEPTH_W-1:0] r_ptr = '0;
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// filtered requests
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logic w_req_f;
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assign w_req_f = w_req && ~full;
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logic r_req_f;
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assign r_req_f = r_req && ~empty;
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true_dual_port_write_first_2_clock_ram #(
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.RAM_WIDTH( DATA_W ),
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.RAM_DEPTH( DEPTH ),
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.INIT_FILE( "" )
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) data_ram (
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.clka( clk ),
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.addra( w_ptr[DEPTH_W-1:0] ),
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.ena( w_req_f ),
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.wea( 1'b1 ),
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.dina( w_data[DATA_W-1:0] ),
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.douta( ),
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.clkb( clk ),
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.addrb( r_ptr[DEPTH_W-1:0] ),
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.enb( r_req_f ),
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.web( 1'b0 ),
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.dinb( '0 ),
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.doutb( r_data[DATA_W-1:0] )
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);
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function [DEPTH_W-1:0] inc_ptr (
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input [DEPTH_W-1:0] ptr
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);
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if( ptr[DEPTH_W-1:0] == DEPTH-1 ) begin
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inc_ptr[DEPTH_W-1:0] = '0;
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end else begin
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inc_ptr[DEPTH_W-1:0] = ptr[DEPTH_W-1:0] + 1'b1;
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end
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endfunction
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always_ff @(posedge clk) begin
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if ( ~nrst ) begin
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w_ptr[DEPTH_W-1:0] <= '0;
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r_ptr[DEPTH_W-1:0] <= '0;
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cnt[DEPTH_W-1:0] <= '0;
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end else begin
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if( w_req_f ) begin
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w_ptr[DEPTH_W-1:0] <= inc_ptr(w_ptr[DEPTH_W-1:0]);
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end
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if( r_req_f ) begin
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r_ptr[DEPTH_W-1:0] <= inc_ptr(r_ptr[DEPTH_W-1:0]);
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end
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if( w_req_f && ~r_req_f ) begin
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cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] + 1'b1;
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end else if( ~w_req_f && r_req_f ) begin
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cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] - 1'b1;
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end
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end
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end
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always_comb begin
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empty = ( cnt[DEPTH_W-1:0] == '0 );
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full = ( cnt[DEPTH_W-1:0] == DEPTH );
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fail = ( empty && r_req ) ||
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( full && w_req );
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end
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endmodule
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module true_dual_port_write_first_2_clock_ram #( parameter
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RAM_WIDTH = 16,
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RAM_DEPTH = 8,
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INIT_FILE = ""
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)(
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input clka,
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input [clogb2(RAM_DEPTH-1)-1:0] addra,
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input ena,
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input wea,
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input [RAM_WIDTH-1:0] dina,
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output [RAM_WIDTH-1:0] douta,
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input clkb,
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input [clogb2(RAM_DEPTH-1)-1:0] addrb,
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input enb,
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input web,
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input [RAM_WIDTH-1:0] dinb,
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output [RAM_WIDTH-1:0] doutb
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);
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reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
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reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
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reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
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// either initializes the memory values to a specified file or to all zeros
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// to match hardware
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generate
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if (INIT_FILE != "") begin: use_init_file
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initial
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$readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
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end else begin: init_bram_to_zero
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integer ram_index;
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initial
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for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
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BRAM[ram_index] = {RAM_WIDTH{1'b0}};
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end
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endgenerate
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always @(posedge clka)
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if (ena)
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if (wea) begin
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BRAM[addra] <= dina;
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ram_data_a <= dina;
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end else
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ram_data_a <= BRAM[addra];
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always @(posedge clkb)
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if (enb)
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if (web) begin
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BRAM[addrb] <= dinb;
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ram_data_b <= dinb;
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end else
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ram_data_b <= BRAM[addrb];
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// no output register
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assign douta = ram_data_a;
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assign doutb = ram_data_b;
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// calculates the address width based on specified RAM depth
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function integer clogb2;
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input integer depth;
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for (clogb2=0; depth>0; clogb2=clogb2+1)
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depth = depth >> 1;
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endfunction
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endmodule
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277
fifo_single_clock_ram_tb.sv
Executable file
277
fifo_single_clock_ram_tb.sv
Executable file
@ -0,0 +1,277 @@
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//------------------------------------------------------------------------------
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// fifo_single_clock_ram_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for fifo_single_clock_reg_ram.sv module
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//
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`timescale 1ns / 1ps
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module fifo_single_clock_ram_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33;
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initial begin
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#0 clk33 = 1'b0;
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forever
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#15.151 clk33 = ~clk33;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand rng1 (
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.clk(clk200),
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.rst(rst_once),
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.reseed(1'b0),
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.seed_val(DerivedClocks[31:0]),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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// Module under test ==========================================================
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// comment or uncomment to test FWFT and normal fifo modes
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//`define TEST_FWFT yes
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// comment or uncomment to sweep-test or random test
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`define TEST_SWEEP yes
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// comment or uncomment to use bare scfifo or quartus wizard-generated wrappers
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//`define BARE_SCFIFO yes
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logic full1, empty1;
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logic full1_d1, empty1_d1;
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logic direction1 = 1'b0;
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always_ff @(posedge clk200) begin
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if( ~nrst ) begin
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direction1 <= 1'b0;
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end else begin
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// sweep logic
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if( full1_d1 ) begin
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direction1 <= 1'b1;
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end else if( empty1_d1 ) begin
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direction1 <= 1'b0;
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end
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// these signals allow "erroring" requests testing:
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// - reads from the empty fifo
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// - writes to the filled fifo
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full1_d1 <= full1;
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empty1_d1 <= empty1;
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end
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end
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logic [3:0] cnt1;
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logic [15:0] data_out1;
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fifo_single_clock_ram #(
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.DEPTH( 8 ),
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.DATA_W( 16 )
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) FF1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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`ifdef TEST_SWEEP
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.w_req( ~direction1 && &RandomNumber1[10] ),
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.w_data( RandomNumber1[15:0] ),
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.r_req( direction1 && &RandomNumber1[10] ),
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.r_data( data_out1[15:0] ),
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`else
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.w_req( &RandomNumber1[10:9] ),
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.w_data( RandomNumber1[15:0] ),
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.r_req( &RandomNumber1[8:7] ),
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.r_data( data_out1[15:0] ),
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`endif
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.cnt( cnt1[3:0] ),
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.empty( empty1 ),
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.full( full1 )
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);
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logic full2, empty2;
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logic full2_d1, empty2_d1;
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logic direction2 = 1'b0;
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always_ff @(posedge clk200) begin
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if( ~nrst ) begin
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direction2 <= 1'b0;
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end else begin
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// sweep logic
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if( full2_d1 ) begin
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direction2 <= 1'b1;
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end else if( empty2_d1 ) begin
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direction2 <= 1'b0;
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end
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// these signals allow "erroring" requests testing:
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// - reads from the empty fifo
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// - writes to the filled fifo
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full2_d1 <= full2;
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empty2_d1 <= empty2;
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end
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end
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//==============================================================================
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logic [15:0] data_out2;
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DCFIFO #(
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.LPM_WIDTH( 16 ),
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.LPM_NUMWORDS( 8 ),
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.LPM_WIDTHU( $clog2(8) ), /// CEIL(LOG2(LPM_NUMWORDS)),
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`ifdef TEST_FWFT
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.LPM_SHOWAHEAD( "ON" ),
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`else
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.LPM_SHOWAHEAD( "OFF" ),
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`endif
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.UNDERFLOW_CHECKING( "ON" ),
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.OVERFLOW_CHECKING( "ON" ),
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.ADD_RAM_OUTPUT_REGISTER( "OFF" ),
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.ENABLE_ECC( "FALSE" ),
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// output delay to the usedw[] outputs
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.DELAY_RDUSEDW( 1 ), // one clock cycle by default
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.DELAY_WRUSEDW( 1 ),
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// Pipe length used for synchronization and metastability resolving
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// If the rdclk and wrclk are unrelated, most often used values range from 2 to 4
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// If they are syncronized to one another, 0 might be used
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.RDSYNC_DELAYPIPE( 3 ), // from the wrclk to the rdclk subsystem
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.WRSYNC_DELAYPIPE( 3 ), // from the rdclk to the wrclk subsystem
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.CLOCKS_ARE_SYNCHRONIZED( "TRUE" ), // Are the clocks sufficiently synchronized (or clock multiples of each other with no pashe shift)
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// such that the synchronization and pipeline registers may be elliminated
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.ADD_USEDW_MSB_BIT( "ON" ),
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.WRITE_ACLR_SYNCH( "OFF" ),
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.READ_ACLR_SYNCH( "OFF" )
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//.USE_EAB( "ON" ),
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//.MAXIMIZE_SPEED( 5 ),
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//.DEVICE_FAMILY( "CYCLONE V" ),
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//.OPTIMIZE_FOR_SPEED( 5 ),
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//.CBXI_PARAMETER( "NOTHING" )
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) FF2 (
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.aclr( 1'b0 ),
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.wrclk( clk200 ),
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`ifdef TEST_SWEEP
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.wrreq( ~direction1 && &RandomNumber1[10] ),
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.data( RandomNumber1[15:0] ),
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`else
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.wrreq( &RandomNumber1[10:9] ),
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.data( RandomNumber1[15:0] ),
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`endif
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.wrempty( ),
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.wrfull( ),
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.wrusedw( ),
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.rdclk( clk200 ),
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`ifdef TEST_SWEEP
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.rdreq( direction1 && &RandomNumber1[10] ),
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.q( data_out2[15:0] ),
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`else
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.rdreq( &RandomNumber1[8:7] ),
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.q( data_out2[15:0] ),
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`endif
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.rdempty( empty2 ),
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.rdfull( full2 ),
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.rdusedw( ),
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.eccstatus( )
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);
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//==============================================================================
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logic outputs_equal;
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assign outputs_equal = ( data_out1[15:0] == data_out2[15:0] ) ||
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`ifdef TEST_FWFT
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// scipping minor discontinuity
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// seems like altera`s fifo has some additional buffering???
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( cnt1[3:0] == 1 && data_out1[15:0] != data_out2[15:0] );
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`else
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1'b0;
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`endif
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logic empty_equal;
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assign empty_equal = ( empty1 == empty2 );
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logic full_equal;
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assign full_equal = ( full1 == full2 );
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logic success = 1'b1;
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always_ff @(posedge clk200) begin
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if( ~nrst ) begin
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success <= 1'b1;
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end else begin
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if( ~outputs_equal ) begin
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success <= 1'b0;
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end
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end
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end
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endmodule
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