mirror of
https://github.com/pConst/basic_verilog.git
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Restored testbenches
This commit is contained in:
Konstantin Pavlov
parent
7c9acbfbf0
commit
51f484b204
95
dynamic_delay_tb.sv
Normal file
95
dynamic_delay_tb.sv
Normal file
@ -0,0 +1,95 @@
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// testbench for dynamic_delay_tb.sv module
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`timescale 1ns / 1ps
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module dynamic_delay_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand rng1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.reseed( 1'b0 ),
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.seed_val( DerivedClocks[31:0] ),
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.out( RandomNumber1[15:0] )
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);
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// Module under test ==========================================================
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logic [5:0] test_data = '0;
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logic [3:0] sel = '0;
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always_ff @(posedge clk200) begin
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if( ~nrst_once ) begin
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test_data[5:0] <= '0;
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sel[3:0] <= '0;
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end else begin
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test_data[5:0] <= test_data[5:0] + 1'b1;
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if( test_data[5:0]=='1 ) begin
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sel[3:0] <= sel[3:0] + 1'b1;
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end
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end
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end
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dynamic_delay #(
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.LENGTH( 3 ),
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.WIDTH( 4 )
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) M (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.in( test_data[3:0] ),
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.sel( sel[3:0] ),
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.out( )
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);
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endmodule
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99
reverse_dimensions_tb.sv
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99
reverse_dimensions_tb.sv
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@ -0,0 +1,99 @@
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//------------------------------------------------------------------------------
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// reverse_dimensions_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for reverse_dimensions module
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`timescale 1ns / 1ps
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module reverse_dimensions_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1;
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forever
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#2.5 clk200 = ~clk200;
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end
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logic rst;
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initial begin
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#10.2 rst = 1;
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#5 rst = 0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin // initializing non-X data before PLL starts
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#10.2 rst_once = 1;
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#5 rst_once = 0;
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end
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initial begin
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#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
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#5 rst_once = 0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) CD1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ED1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand RNG1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.reseed( 1'b0 ),
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.seed_val( DerivedClocks[31:0] ),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100.2 start = 1'b1;
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#5 start = 1'b0;
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end
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// Module under test ==========================================================
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logic [1:0][7:0] in;
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assign in = RandomNumber1[15:0];
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logic [7:0][1:0] out;
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reverse_dimensions #(
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.D1_WIDTH( 2 ),
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.D2_WIDTH( 8 )
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) RD1 (
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.in( in ),
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.out( out )
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);
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endmodule
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271
spi_master_tb.sv
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271
spi_master_tb.sv
Normal file
@ -0,0 +1,271 @@
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//------------------------------------------------------------------------------
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// spi_master_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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//
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`timescale 1ns / 1ps
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module spi_master_tb();
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logic clk800;
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initial begin
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#0 clk800 = 1'b0;
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forever
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#0.625 clk800 = ~clk800;
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end
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33;
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initial begin
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#0 clk33 = 1'b0;
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forever
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#15.151 clk33 = ~clk33;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand rng1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.reseed( 1'b0 ),
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.seed_val( DerivedClocks[31:0] ),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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// Module under test ==========================================================
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logic oe1_pin, ncs1_pin, din1_pin, clk1_pin, clk1_pin_rise, clk1_pin_fall;
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logic oe2_pin, ncs2_pin, din2_pin, clk2_pin, clk2_pin_rise, clk2_pin_fall;
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logic oe3_pin, ncs3_pin, din3_pin, clk3_pin, clk3_pin_rise, clk3_pin_fall;
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logic oe4_pin, ncs4_pin, din4_pin, clk4_pin, clk4_pin_rise, clk4_pin_fall;
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reg [7:0] test1_data = 8'b1010_0011;
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reg [7:0] test2_data = 8'b1010_0011;
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reg [7:0] test3_data = 8'b1010_0011;
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reg [7:0] test4_data = 8'b1010_0011;
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spi_master #(
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.CPOL( 0 ),
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.FREE_RUNNING_SPI_CLK( 0 ),
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.MOSI_DATA_WIDTH( 8 ),
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.WRITE_MSB_FIRST( 1 ),
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.MISO_DATA_WIDTH( 8 ),
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.READ_MSB_FIRST( 1 )
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) SM1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.spi_clk( DerivedClocks[0] ),
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.spi_wr_cmd( 0 ),
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.spi_rd_cmd( start ),
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.spi_busy( ),
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.mosi_data( 8'b1010_0011 ),
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.miso_data( ),
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.clk_pin( clk1_pin ),
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.ncs_pin( ncs1_pin ),
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.mosi_pin( ),
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.oe_pin( oe1_pin ),
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.miso_pin( din1_pin )
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);
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spi_master #(
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.CPOL( 1 ),
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.FREE_RUNNING_SPI_CLK( 0 ),
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.MOSI_DATA_WIDTH( 8 ),
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.WRITE_MSB_FIRST( 1 ),
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.MISO_DATA_WIDTH( 8 ),
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.READ_MSB_FIRST( 1 )
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) SM2 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.spi_clk( DerivedClocks[0] ),
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.spi_wr_cmd( 0 ),
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.spi_rd_cmd( start ),
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.spi_busy( ),
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.mosi_data( 8'b1010_0011 ),
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.miso_data( ),
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.clk_pin( clk2_pin ),
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.ncs_pin( ncs2_pin ),
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.mosi_pin( ),
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.oe_pin( oe2_pin ),
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.miso_pin( din2_pin )
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);
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spi_master #(
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.CPOL( 0 ),
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.FREE_RUNNING_SPI_CLK( 1 ),
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.MOSI_DATA_WIDTH( 8 ),
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.WRITE_MSB_FIRST( 0 ),
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.MISO_DATA_WIDTH( 8 ),
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.READ_MSB_FIRST( 0 )
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) SM3 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.spi_clk( DerivedClocks[0] ),
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.spi_wr_cmd( 0 ),
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.spi_rd_cmd( start ),
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.spi_busy( ),
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.mosi_data( 8'b1010_0011 ),
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.miso_data( ),
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.clk_pin( clk3_pin ),
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.ncs_pin( ncs3_pin ),
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.mosi_pin( ),
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.oe_pin( oe3_pin ),
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.miso_pin( din3_pin )
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);
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spi_master #(
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.CPOL( 0 ),
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.FREE_RUNNING_SPI_CLK( 1 ),
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.MOSI_DATA_WIDTH( 8 ),
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.WRITE_MSB_FIRST( 0 ),
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.MISO_DATA_WIDTH( 8 ),
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.READ_MSB_FIRST( 0 )
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) SM4 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.spi_clk( DerivedClocks[0] ),
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.spi_wr_cmd( 0 ),
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.spi_rd_cmd( start ),
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.spi_busy( ),
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.mosi_data( 8'b1010_0011 ),
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.miso_data( ),
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.clk_pin( clk4_pin ),
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.ncs_pin( ncs4_pin ),
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.mosi_pin( ),
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.oe_pin( oe4_pin ),
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.miso_pin( din4_pin )
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);
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// emulating external divice ==================================================
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// that works asynchronously on clk33 clock
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// clk800 emulates some high-speed "ideal" slave
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edge_detect ed2[3:0] (
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.clk( {4{clk800}} ),
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.nrst( {4{1'b1}} ),
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.in( {clk1_pin, clk2_pin, clk3_pin, clk4_pin} ),
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.rising( {clk1_pin_rise, clk2_pin_rise, clk3_pin_rise, clk4_pin_rise} ),
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.falling( {clk1_pin_fall, clk2_pin_fall, clk3_pin_fall, clk4_pin_fall} ),
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.both( )
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);
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always_ff @(posedge clk800) begin
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if( ~nrst_once) begin
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din1_pin <= 0;
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test1_data[7:0] = 8'b1010_0011;
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end else begin
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if( ~ncs1_pin && ~oe1_pin && clk1_pin_fall ) begin
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din1_pin <=test1_data[7];
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test1_data[7:0] <= {test1_data[6:0],1'b0};
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end
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end
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end
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always_ff @(posedge clk800) begin
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if( ~nrst_once) begin
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din2_pin <= 0;
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test2_data[7:0] = 8'b1010_0011;
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end else begin
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if( ~ncs2_pin && ~oe2_pin && clk2_pin_rise ) begin
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din2_pin <=test2_data[7];
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test2_data[7:0] <= {test2_data[6:0],1'b0};
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end
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end
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end
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always_ff @(posedge clk800) begin
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if( ~nrst_once) begin
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din3_pin <= 0;
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test3_data[7:0] = 8'b1010_0011;
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end else begin
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if( ~ncs3_pin && ~oe3_pin && clk3_pin_fall ) begin
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din3_pin <=test3_data[7];
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test3_data[7:0] <= {test3_data[6:0],1'b0};
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end
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end
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end
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always_ff @(posedge clk800) begin
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if( ~nrst_once) begin
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din4_pin <= 0;
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test4_data[7:0] = 8'b1010_0011;
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end else begin
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if( ~ncs4_pin && ~oe4_pin && clk4_pin_fall ) begin
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din4_pin <=test4_data[7];
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test4_data[7:0] <= {test4_data[6:0],1'b0};
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end
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end
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end
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endmodule
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