FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity

Updated Vivado gitignore

Browse Source
This commit is contained in:
Konstantin Pavlov 2022-11-11 14:29:24 +03:00
parent f9cfe3935b
commit 553e74c437
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gitignores/.gitignore_vivado
View File

@ -11,11 +11,18 @@
*.cache
*.hw
*.gen
*.ip_user_files
*.runs
*.sim
.Xil
*.srcs/sources*/bd/**
!*.srcs/sources*/bd/**/*.xci
*.srcs/sources*/ip/**
!*.srcs/sources*/ip/**/*.xci
.ioplanning
*.jou
*.log
*.str