FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity

Added dsp_everywhere

Browse Source
This commit is contained in:
Konstantin Pavlov 2023-10-08 12:07:57 +03:00
parent 5020e0b13e
commit 64e0408e0c
1 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
scripts/dsp_everywhere.xdc Normal file
View File

@ -0,0 +1,19 @@
#------------------------------------------------------------------------------
# dsp_everywhere.xdc
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------
# INFO ------------------------------------------------------------------------
# Experimental XDC constraints to explore how many DSPs could be used in your
# project. After the exploration you can write more specific DSP constraints
#
# add all project cells first
set_property use_dsp48 yes [get_cells -hierarchical -filter { IS_PRIMITIVE == "FALSE" }]
# (OPTIONAL) and then exclude specific cells if they fail timings with DSP`s
# set_property use_dsp no [get_cells -hierarchical -filter { IS_PRIMITIVE == "FALSE" && NAME =~ "top/my_instance_a*" }]
# set_property use_dsp no [get_cells -hierarchical -filter { IS_PRIMITIVE == "FALSE" && NAME =~ "top/my_instance_b*" }]
# set_property use_dsp no [get_cells -hierarchical -filter { IS_PRIMITIVE == "FALSE" && NAME =~ "top/my_instance_c*" }]