FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity

Added benchmark_projects dir README

Browse Source
This commit is contained in:
Konstantin Pavlov 2022-05-16 19:21:43 +03:00
parent f6a5726184
commit 66733fa819
1 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
benchmark_projects/README.md Executable file
View File

@ -0,0 +1,22 @@
readme for "benchmark_projects" directory
published as part of https://github.com/pConst/basic_verilog
Konstantin Pavlov, pavlovconst@gmail.com
The directory contains single reference System Verilog codebase, compiled consistently for multiple FPGA platforms and vendors.
Supported and committed IDE projects include
* Xilinx ISE
* Xilinx Vivado
* Intel Quartus
* Gowin IDE
Currently working on
* Microsemi Libero
* Lattice iCEcube
* Lattice FOSS toolchain
See comparative compile time results in ./benchmark_results.txt