Added error suppression for Modelsim script

example_projects/testbench_template_tb/compile.tcl

@@ -28,6 +28,8 @@ set vsim_params "-L altera_mf_ver -L altera_mf -L lpm_ver -L lpm"
 
 set top_level work.main_tb
 
+set suppress_err_list ""
+
 # Console commands:
 # r = Recompile changed and dependent files
 # rr = Recompile everything
@@ -61,7 +63,7 @@ foreach {library file_list} $library_file_list {
       if [regexp {.vhdl?$} $file] {
         vcom -93 $file
       } else {
-        vlog $file
+        vlog $file -suppress $suppress_err_list
       }
       set last_compile_time 0
     }

example_projects/testbench_template_tb/main_tb.sv

@@ -1,5 +1,6 @@
 //------------------------------------------------------------------------------
 // main_tb.sv
+// published as part of https://github.com/pConst/basic_verilog
 // Konstantin Pavlov, pavlovconst@gmail.com
 //------------------------------------------------------------------------------
 
@@ -21,11 +22,17 @@ initial begin
 end
 
 // external device "asynchronous" clock
-logic clk33;
+logic clk33a;
 initial begin
-  #0 clk33 = 1'b0;
+  #0 clk33a = 1'b0;
   forever
-    #15.151 clk33 = ~clk33;
+    #7 clk33a = ~clk33a;
+end
+
+logic clk33;
+//assign clk33 = clk33a;
+always @(*) begin
+  clk33 = #($urandom_range(0, 2000)*10ps) clk33a;
 end
 
 logic rst;

main_tb.sv

@@ -1,5 +1,6 @@
 //------------------------------------------------------------------------------
 // main_tb.sv
+// published as part of https://github.com/pConst/basic_verilog
 // Konstantin Pavlov, pavlovconst@gmail.com
 //------------------------------------------------------------------------------