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Added error suppression for Modelsim script

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This commit is contained in:
Konstantin Pavlov 2022-04-25 01:03:37 +03:00
parent 98040673a3
commit 66ff427e1e
3 changed files with 14 additions and 4 deletions
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4
example_projects/testbench_template_tb/compile.tcl
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@ -28,6 +28,8 @@ set vsim_params "-L altera_mf_ver -L altera_mf -L lpm_ver -L lpm"
set top_level work.main_tb set top_level work.main_tb
set suppress_err_list ""
# Console commands: # Console commands:
# r = Recompile changed and dependent files # r = Recompile changed and dependent files
# rr = Recompile everything # rr = Recompile everything
@ -61,7 +63,7 @@ foreach {library file_list} $library_file_list {
if [regexp {.vhdl?$} $file] { if [regexp {.vhdl?$} $file] {
vcom -93 $file vcom -93 $file
} else { } else {
vlog $file vlog $file -suppress $suppress_err_list
} }
set last_compile_time 0 set last_compile_time 0
} }

13
example_projects/testbench_template_tb/main_tb.sv
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@ -1,5 +1,6 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// main_tb.sv // main_tb.sv
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com // Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
@ -21,11 +22,17 @@ initial begin
end end
// external device "asynchronous" clock // external device "asynchronous" clock
logic clk33; logic clk33a;
initial begin initial begin
#0 clk33 = 1'b0; #0 clk33a = 1'b0;
forever forever
#15.151 clk33 = ~clk33; #7 clk33a = ~clk33a;
end
logic clk33;
//assign clk33 = clk33a;
always @(*) begin
clk33 = #($urandom_range(0, 2000)*10ps) clk33a;
end end
logic rst; logic rst;

1
main_tb.sv
View File

@ -1,5 +1,6 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// main_tb.sv // main_tb.sv
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com // Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------