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Updated benchmark projects. Added 'benchmark_results.txt' that i got on my machine

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Konstantin Pavlov 2020-12-17 18:42:52 +03:00
parent d44ef08c2c
commit 68922a34d2
7 changed files with 177 additions and 75 deletions
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18
example_projects/benchmark_results.txt Normal file
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Compilation time results for reference benchmark projects
=========================================================
Xeon E5-2630 v4, RAM 32GB, Windows 7
------------------------------------
quartus_benchmark - 4m 58s ( Quartus Lite 17 )
vivado_benchmark - 5m 58s ( Vivado 2019.2 )
gowin_benchmark - 4m 15s ( Gowin_V1.9.6Beta )
ise_benchmark - 9m 10s ( ISE 12.4 )
Xeon E5-2630 v4, RAM 32GB, Windows 7, project files on RamDisk
--------------------------------------------------------------
quartus_benchmark - 4m 57s
vivado_benchmark - 5m 56s

77
example_projects/gowin_benchmark/src/dynamic_delay.sv
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@ -4,55 +4,82 @@
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Dynamic delay for arbitrary signal
// Dynamic delay for arbitrary signal.
//
// CAUTION: The module intentionally does NOT implement error handling when
// LENGTH is not a multiple of 2. Please handle "out of range"
// checks externally.
// Incoming data elements have WIDTH bits each. Module does serialization of
// input data and outputs flattened bits, based on provided selector value.
// You can perform delays bit-wize, not just element-wize.
//
// CAUTION: Be careful selecting last, most-delayed "WIDTH" number of bits.
// The module intentionally does NOT implement "out of range"
// checks. Please handle them externally.
/* --- INSTANTIATION TEMPLATE BEGIN ---
dynamic_delay #(
.LENGTH( 8 )
//.SEL_W( 3 )
) DD1 (
.LENGTH( 3 ),
.WIDTH( 4 )
) M (
.clk( clk ),
.nrst( 1'b1 ),
.nrst( nrst ),
.ena( 1'b1 ),
.in( ),
.sel( ),
.out( )
.in( in_data[3:0] ),
.sel( sel[3:0] ),
.out( out_data[3:0] )
);
--- INSTANTIATION TEMPLATE END ---*/
module dynamic_delay #( parameter
LENGTH = 8, // maximum delay chain width
SEL_W = $clog2(LENGTH) // output selector width
LENGTH = 63, // maximum delay chain length
WIDTH = 4, // data width
SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
// plus one is for zero delay element
)(
input clk,
input nrst,
input ena,
input in,
input [SEL_W-1:0] sel, // output selector
output logic out
input [WIDTH-1:0] in, // input data
// bit in[0] is the "oldest" one
// bit in[WIDTH] is considered the most recent
input [SEL_W-1:0] sel, // output selector
output logic [WIDTH-1:0] out // output data
);
logic [(LENGTH-1):0] data = 0;
logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;
// packed vector includes extra bits
logic [(LENGTH+1)*WIDTH-1:0] pack_data;
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;
integer i;
always_ff @(posedge clk) begin
if (~nrst) begin
data[(LENGTH-1):0] <= 0;
out <= 0;
end else if (ena) begin
data[0] <= in;
for (i=1; i<LENGTH; i=i+1) begin
data[i] <= data[i-1];
if( ~nrst ) begin
// reset all data except zero element
for( i=1; i<(LENGTH+1); i=i+1 ) begin
data[i][WIDTH-1:0] <= '0;
end
out <= data[sel[SEL_W-1:0]];
end else if (ena) begin
for( i=1; i<(LENGTH+1); i=i+1 ) begin
data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
end
end
end
integer j;
always_comb begin
// zero element assignment
data[0][WIDTH-1:0] <= in[WIDTH-1:0];
// output selector, sel==0 gives non-delayed output
for( j=0; j<WIDTH; j=j+1 ) begin
out[j] <= pack_data[sel[SEL_W-1:0]+j];
end
end

1
example_projects/gowin_benchmark/src/main.sv
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@ -28,6 +28,7 @@ module main(
dynamic_delay #(
.LENGTH( `LENGTH ),
.WIDTH( 1 ),
.SEL_W( `SEL_W )
) dd [`WIDTH-1:0] (
.clk( {`WIDTH{clk}} ),

77
example_projects/quartus_benchmark/dynamic_delay.sv
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@ -4,55 +4,82 @@
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Dynamic delay for arbitrary signal
// Dynamic delay for arbitrary signal.
//
// CAUTION: The module intentionally does NOT implement error handling when
// LENGTH is not a multiple of 2. Please handle "out of range"
// checks externally.
// Incoming data elements have WIDTH bits each. Module does serialization of
// input data and outputs flattened bits, based on provided selector value.
// You can perform delays bit-wize, not just element-wize.
//
// CAUTION: Be careful selecting last, most-delayed "WIDTH" number of bits.
// The module intentionally does NOT implement "out of range"
// checks. Please handle them externally.
/* --- INSTANTIATION TEMPLATE BEGIN ---
dynamic_delay #(
.LENGTH( 8 )
//.SEL_W( 3 )
) DD1 (
.LENGTH( 3 ),
.WIDTH( 4 )
) M (
.clk( clk ),
.nrst( 1'b1 ),
.nrst( nrst ),
.ena( 1'b1 ),
.in( ),
.sel( ),
.out( )
.in( in_data[3:0] ),
.sel( sel[3:0] ),
.out( out_data[3:0] )
);
--- INSTANTIATION TEMPLATE END ---*/
module dynamic_delay #( parameter
LENGTH = 8, // maximum delay chain width
SEL_W = $clog2(LENGTH) // output selector width
LENGTH = 63, // maximum delay chain length
WIDTH = 4, // data width
SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
// plus one is for zero delay element
)(
input clk,
input nrst,
input ena,
input in,
input [SEL_W-1:0] sel, // output selector
output logic out
input [WIDTH-1:0] in, // input data
// bit in[0] is the "oldest" one
// bit in[WIDTH] is considered the most recent
input [SEL_W-1:0] sel, // output selector
output logic [WIDTH-1:0] out // output data
);
logic [(LENGTH-1):0] data = 0;
logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;
// packed vector includes extra bits
logic [(LENGTH+1)*WIDTH-1:0] pack_data;
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;
integer i;
always_ff @(posedge clk) begin
if (~nrst) begin
data[(LENGTH-1):0] <= 0;
out <= 0;
end else if (ena) begin
data[0] <= in;
for (i=1; i<LENGTH; i=i+1) begin
data[i] <= data[i-1];
if( ~nrst ) begin
// reset all data except zero element
for( i=1; i<(LENGTH+1); i=i+1 ) begin
data[i][WIDTH-1:0] <= '0;
end
out <= data[sel[SEL_W-1:0]];
end else if (ena) begin
for( i=1; i<(LENGTH+1); i=i+1 ) begin
data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
end
end
end
integer j;
always_comb begin
// zero element assignment
data[0][WIDTH-1:0] <= in[WIDTH-1:0];
// output selector, sel==0 gives non-delayed output
for( j=0; j<WIDTH; j=j+1 ) begin
out[j] <= pack_data[sel[SEL_W-1:0]+j];
end
end

1
example_projects/quartus_benchmark/main.sv
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@ -28,6 +28,7 @@ module main(
dynamic_delay #(
.LENGTH( `LENGTH ),
.WIDTH( 1 ),
.SEL_W( `SEL_W )
) dd [`WIDTH-1:0] (
.clk( {`WIDTH{clk}} ),

77
example_projects/vivado_benchmark/vivado_benchmark.srcs/sources_1/dynamic_delay.sv
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@ -4,55 +4,82 @@
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Dynamic delay for arbitrary signal
// Dynamic delay for arbitrary signal.
//
// CAUTION: The module intentionally does NOT implement error handling when
// LENGTH is not a multiple of 2. Please handle "out of range"
// checks externally.
// Incoming data elements have WIDTH bits each. Module does serialization of
// input data and outputs flattened bits, based on provided selector value.
// You can perform delays bit-wize, not just element-wize.
//
// CAUTION: Be careful selecting last, most-delayed "WIDTH" number of bits.
// The module intentionally does NOT implement "out of range"
// checks. Please handle them externally.
/* --- INSTANTIATION TEMPLATE BEGIN ---
dynamic_delay #(
.LENGTH( 8 )
//.SEL_W( 3 )
) DD1 (
.LENGTH( 3 ),
.WIDTH( 4 )
) M (
.clk( clk ),
.nrst( 1'b1 ),
.nrst( nrst ),
.ena( 1'b1 ),
.in( ),
.sel( ),
.out( )
.in( in_data[3:0] ),
.sel( sel[3:0] ),
.out( out_data[3:0] )
);
--- INSTANTIATION TEMPLATE END ---*/
module dynamic_delay #( parameter
LENGTH = 8, // maximum delay chain width
SEL_W = $clog2(LENGTH) // output selector width
LENGTH = 63, // maximum delay chain length
WIDTH = 4, // data width
SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
// plus one is for zero delay element
)(
input clk,
input nrst,
input ena,
input in,
input [SEL_W-1:0] sel, // output selector
output logic out
input [WIDTH-1:0] in, // input data
// bit in[0] is the "oldest" one
// bit in[WIDTH] is considered the most recent
input [SEL_W-1:0] sel, // output selector
output logic [WIDTH-1:0] out // output data
);
logic [(LENGTH-1):0] data = 0;
logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;
// packed vector includes extra bits
logic [(LENGTH+1)*WIDTH-1:0] pack_data;
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;
integer i;
always_ff @(posedge clk) begin
if (~nrst) begin
data[(LENGTH-1):0] <= 0;
out <= 0;
end else if (ena) begin
data[0] <= in;
for (i=1; i<LENGTH; i=i+1) begin
data[i] <= data[i-1];
if( ~nrst ) begin
// reset all data except zero element
for( i=1; i<(LENGTH+1); i=i+1 ) begin
data[i][WIDTH-1:0] <= '0;
end
out <= data[sel[SEL_W-1:0]];
end else if (ena) begin
for( i=1; i<(LENGTH+1); i=i+1 ) begin
data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
end
end
end
integer j;
always_comb begin
// zero element assignment
data[0][WIDTH-1:0] <= in[WIDTH-1:0];
// output selector, sel==0 gives non-delayed output
for( j=0; j<WIDTH; j=j+1 ) begin
out[j] <= pack_data[sel[SEL_W-1:0]+j];
end
end

1
example_projects/vivado_benchmark/vivado_benchmark.srcs/sources_1/main.sv
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@ -28,6 +28,7 @@ module main(
dynamic_delay #(
.LENGTH( `LENGTH ),
.WIDTH( 1 ),
.SEL_W( `SEL_W )
) dd [`WIDTH-1:0] (
.clk( {`WIDTH{clk}} ),