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Updated EdgeDetect module instantiation

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This commit is contained in:
Konstantin Pavlov (fm) 2018-12-07 11:26:03 +03:00
parent 24312652ab
commit 6b22c900b1
12 changed files with 30 additions and 45 deletions
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0
main_tb.v → 00_obsolete/main_tb.v
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4
ActionBurst2_tb.v
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@ -1,5 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// SimWrapper.v // ActionBurst2_tb.v
// Konstantin Pavlov, pavlovconst@gmail.com // Konstantin Pavlov, pavlovconst@gmail.com
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
@ -9,7 +9,7 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module SimWrapper(); module ActionBurst2_tb();
reg clk200; reg clk200;
initial begin initial begin

4
ActionBurst_tb.v
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@ -1,5 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// SimWrapper.v // ActionBurst_tb.v
// Konstantin Pavlov, pavlovconst@gmail.com // Konstantin Pavlov, pavlovconst@gmail.com
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
@ -9,7 +9,7 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module SimWrapper(); module ActionBurst_tb();
reg clk200; reg clk200;
initial begin initial begin

4
DeBounce_tb.v
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@ -1,5 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// Main_TB.v // DeBounce_tb.v
// Konstantin Pavlov, pavlovconst@gmail.com // Konstantin Pavlov, pavlovconst@gmail.com
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
@ -9,7 +9,7 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module Main_tb(); module DeBounce_tb();
reg clk200; reg clk200;
initial begin initial begin

5
Encoder_tb.v
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@ -1,6 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// Encoder_test project, 201601 // Encoder_tb.v
// Main_tb.v
// Konstantin Pavlov, pavlovconst@gmail.com // Konstantin Pavlov, pavlovconst@gmail.com
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
@ -10,7 +9,7 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module Main_tb(); module Encoder_tb();
reg clk200; reg clk200;
initial begin initial begin

10
PulseGen_tb.v
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@ -1,6 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// PulseGen_test project, 201512 // PulseGen.v
// Main_tb.v
// Konstantin Pavlov, pavlovconst@gmail.com // Konstantin Pavlov, pavlovconst@gmail.com
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
@ -10,12 +9,12 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module Main_tb(); module PulseGen_tb();
reg clk200; reg clk200;
initial begin initial begin
#0 clk200 = 1; #0 clk200 = 1;
forever forever
#2.5 clk200 = ~clk200; #2.5 clk200 = ~clk200;
end end
@ -62,6 +61,5 @@ PulseGen PG1 (clk200,~rst,1,1,1'b1,start,busy1,out1);
wire busy2,out2; wire busy2,out2;
PulseGen PG2 (clk200,~rst,{28'b0,RandomNumber1[3:0]},{28'b0,RandomNumber1[7:4]},1'b0,&RandomNumber1[2:0],busy2,out2); PulseGen PG2 (clk200,~rst,{28'b0,RandomNumber1[3:0]},{28'b0,RandomNumber1[7:4]},1'b0,&RandomNumber1[2:0],busy2,out2);
endmodule endmodule

8
ReverseVector_tb.sv
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@ -55,11 +55,9 @@ ClkDivider #(
); );
logic [31:0] E_DerivedClocks; logic [31:0] E_DerivedClocks;
EdgeDetect #( EdgeDetect ED1[31:0] (
.WIDTH( 32 ) .clk( {32{clk200}} ),
) ED1 ( .nrst( {32{nrst_once}} ),
.clk( clk200 ),
.nrst( nrst_once ),
.in( DerivedClocks[31:0] ), .in( DerivedClocks[31:0] ),
.rising( E_DerivedClocks[31:0] ), .rising( E_DerivedClocks[31:0] ),
.falling( ), .falling( ),

8
bin2pos_tb.sv
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@ -55,11 +55,9 @@ ClkDivider #(
); );
logic [31:0] E_DerivedClocks; logic [31:0] E_DerivedClocks;
EdgeDetect #( EdgeDetect ED1[31:0] (
.WIDTH( 32 ) .clk( {32{clk200}} ),
) ED1 ( .nrst( {32{nrst_once}} ),
.clk( clk200 ),
.nrst( nrst_once ),
.in( DerivedClocks[31:0] ), .in( DerivedClocks[31:0] ),
.rising( E_DerivedClocks[31:0] ), .rising( E_DerivedClocks[31:0] ),
.falling( ), .falling( ),

8
fifo_tb.sv
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@ -55,11 +55,9 @@ ClkDivider #(
); );
logic [31:0] E_DerivedClocks; logic [31:0] E_DerivedClocks;
EdgeDetect #( EdgeDetect ED1[31:0] (
.WIDTH( 32 ) .clk( {32{clk200}} ),
) ED1 ( .nrst( {32{nrst_once}} ),
.clk( clk200 ),
.nrst( nrst_once ),
.in( DerivedClocks[31:0] ), .in( DerivedClocks[31:0] ),
.rising( E_DerivedClocks[31:0] ), .rising( E_DerivedClocks[31:0] ),
.falling( ), .falling( ),

8
lifo_tb.sv
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@ -55,11 +55,9 @@ ClkDivider #(
); );
logic [31:0] E_DerivedClocks; logic [31:0] E_DerivedClocks;
EdgeDetect #( EdgeDetect ED1[31:0] (
.WIDTH( 32 ) .clk( {32{clk200}} ),
) ED1 ( .nrst( {32{nrst_once}} ),
.clk( clk200 ),
.nrst( nrst_once ),
.in( DerivedClocks[31:0] ), .in( DerivedClocks[31:0] ),
.rising( E_DerivedClocks[31:0] ), .rising( E_DerivedClocks[31:0] ),
.falling( ), .falling( ),

8
main_tb.sv
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@ -54,11 +54,9 @@ ClkDivider #(
); );
logic [31:0] E_DerivedClocks; logic [31:0] E_DerivedClocks;
EdgeDetect #( EdgeDetect ED1[31:0] (
.WIDTH( 32 ) .clk( {32{clk200}} ),
) ED1 ( .nrst( {32{nrst_once}} ),
.clk( clk200 ),
.nrst( nrst_once ),
.in( DerivedClocks[31:0] ), .in( DerivedClocks[31:0] ),
.rising( E_DerivedClocks[31:0] ), .rising( E_DerivedClocks[31:0] ),
.falling( ), .falling( ),

8
pos2bin_tb.sv
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@ -55,11 +55,9 @@ ClkDivider #(
); );
logic [31:0] E_DerivedClocks; logic [31:0] E_DerivedClocks;
EdgeDetect #( EdgeDetect ED1[31:0] (
.WIDTH( 32 ) .clk( {32{clk200}} ),
) ED1 ( .nrst( {32{nrst_once}} ),
.clk( clk200 ),
.nrst( nrst_once ),
.in( DerivedClocks[31:0] ), .in( DerivedClocks[31:0] ),
.rising( E_DerivedClocks[31:0] ), .rising( E_DerivedClocks[31:0] ),
.falling( ), .falling( ),