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Added errors supression script for Vivado to allow 'proto' projects w/o pin assignments

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Konstantin Pavlov 2019-04-16 04:42:39 +03:00
parent 1fdc31ad05
commit 6bdafa6d56
1 changed files with 14 additions and 0 deletions
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scripts/allow_undefined_ports.tcl Normal file
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#------------------------------------------------------------------------------
# allow_undefined_ports.tcl
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------
# INFO ------------------------------------------------------------------------
# Use this script for Xilinx Vivado environment to allow generation of test
# projects with undefines pins (that will eventually have DEFAULT positional
# and electrical standard constraints)
#
# Place this script as a pre-tcl-script for "Generate bitstream" step
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]