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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

snake_case naming for edge detector

This commit is contained in:
Konstantin Pavlov (fm) 2018-12-11 15:34:14 +03:00
parent 6b22c900b1
commit 6ec509c3c6
2 changed files with 6 additions and 6 deletions

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@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
// EdgeDetect.sv
// edge_detect.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
@ -14,7 +14,7 @@
/* --- INSTANTIATION TEMPLATE BEGIN ---
EdgeDetect ED1[31:0] (
edge_detect ED1[31:0] (
.clk( {32{clk}} ),
.nrst( {32{1'b1}} ),
.in( in[31:0] ),
@ -26,7 +26,7 @@ EdgeDetect ED1[31:0] (
--- INSTANTIATION TEMPLATE END ---*/
module EdgeDetect(
module edge_detect(
input clk,
input nrst,

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@ -1,5 +1,5 @@
//------------------------------------------------------------------------------
// EdgeDetect_tb.sv
// edge_detect_tb.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
@ -8,7 +8,7 @@
`timescale 1ns / 1ps
module EdgeDetect_tb();
module edge_detect_tb();
logic clk200;
initial begin
@ -71,7 +71,7 @@ end
// Module under test ==========================================================
EdgeDetect ED1[15:0] (
edge_detect ED1[15:0] (
.clk( {16{clk200}} ),
.nrst( {16{nrst_once}} ),
.in( RandomNumber1[15:0] ),