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https://github.com/pConst/basic_verilog.git
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snake_case naming for edge detector
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@ -1,5 +1,5 @@
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// EdgeDetect.sv
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// edge_detect.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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@ -14,7 +14,7 @@
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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EdgeDetect ED1[31:0] (
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edge_detect ED1[31:0] (
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.clk( {32{clk}} ),
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.clk( {32{clk}} ),
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.nrst( {32{1'b1}} ),
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.nrst( {32{1'b1}} ),
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.in( in[31:0] ),
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.in( in[31:0] ),
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@ -26,7 +26,7 @@ EdgeDetect ED1[31:0] (
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--- INSTANTIATION TEMPLATE END ---*/
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--- INSTANTIATION TEMPLATE END ---*/
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module EdgeDetect(
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module edge_detect(
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input clk,
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input clk,
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input nrst,
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input nrst,
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@ -1,5 +1,5 @@
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// EdgeDetect_tb.sv
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// edge_detect_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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@ -8,7 +8,7 @@
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module EdgeDetect_tb();
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module edge_detect_tb();
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logic clk200;
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logic clk200;
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initial begin
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initial begin
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@ -71,7 +71,7 @@ end
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// Module under test ==========================================================
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// Module under test ==========================================================
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EdgeDetect ED1[15:0] (
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edge_detect ED1[15:0] (
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.clk( {16{clk200}} ),
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.clk( {16{clk200}} ),
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.nrst( {16{nrst_once}} ),
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.nrst( {16{nrst_once}} ),
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.in( RandomNumber1[15:0] ),
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.in( RandomNumber1[15:0] ),
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