Added pulse_stretch.sv module

pulse_stretch.sv

@@ -0,0 +1,62 @@
+//--------------------------------------------------------------------------------
+// pulse_stretch.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+// Pulse stretcher/extender module
+//   this implementftion uses a simple delay line
+//   suits when LENGTH of desired output pulse is low
+//   when you need wide output pulses - counter implementation will make sense
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+pulse_stretch #(
+  .LENGTH( 8 )
+) ps1 (
+  .clk( clk ),
+  .nrst( nrst ),
+  .in(  ),
+  .out(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+module pulse_stretch #( parameter
+  LENGTH = 8
+)(
+  input clk,
+  input nrst,
+
+  input in,
+  output out
+);
+
+
+generate
+
+  if ( LENGTH == 0 ) begin
+    assign out = 0;
+
+  end else if( LENGTH == 1 ) begin
+    assign out = in;
+
+  end else begin
+    logic [LENGTH-1:0] shifter = '0;
+    always_ff @(posedge clk) begin
+      if( ~nrst ) begin
+        shifter[LENGTH-1:0] <= '0;
+      end else begin
+        shifter[LENGTH-1:0] <= {shifter[LENGTH-2:0],in};
+      end // nrst
+    end // always
+
+    assign out = |shifter[LENGTH-1:0];
+
+  end // if LENGTH
+endgenerate
+
+
+endmodule
+

pulse_stretch_tb.sv

@@ -0,0 +1,89 @@
+
+// RXI - PIN400M
+// testbench for pulse_stretch.sv module
+
+`timescale 1ns / 1ps
+
+module pulse_stretch_tb();
+
+logic clk200;
+initial begin
+  #0 clk200 = 1'b0;
+  forever
+    #2.5 clk200 = ~clk200;
+end
+
+logic rst;
+initial begin
+  #0 rst = 1'b0;
+  #10.2 rst = 1'b1;
+  #5 rst = 1'b0;
+  //#10000;
+  forever begin
+    #9985 rst = ~rst;
+    #5 rst = ~rst;
+  end
+end
+
+logic nrst;
+assign nrst = ~rst;
+
+logic rst_once;
+initial begin
+  #0 rst_once = 1'b0;
+  #10.2 rst_once = 1'b1;
+  #5 rst_once = 1'b0;
+end
+
+logic nrst_once;
+assign nrst_once = ~rst_once;
+
+logic [31:0] DerivedClocks;
+clk_divider #(
+  .WIDTH( 32 )
+) cd1 (
+  .clk( clk200 ),
+  .nrst( nrst_once ),
+  .ena( 1'b1 ),
+  .out( DerivedClocks[31:0] )
+);
+
+logic [31:0] E_DerivedClocks;
+edge_detect ed1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
+  .in( DerivedClocks[31:0] ),
+  .rising( E_DerivedClocks[31:0] ),
+  .falling(  ),
+  .both(  )
+);
+
+logic [15:0] RandomNumber1;
+c_rand rng1 (
+  .clk( clk200 ),
+  .rst( rst_once ),
+  .reseed( 1'b0 ),
+  .seed_val( DerivedClocks[31:0] ),
+  .out( RandomNumber1[15:0] )
+);
+
+logic start;
+initial begin
+  #0 start = 1'b0;
+  #100 start = 1'b1;
+  #5 start = 1'b0;
+end
+
+// Modules under test ==========================================================
+
+pulse_stretch #(
+  .LENGTH( 8 )
+) ps1 (
+  .clk( clk200 ),
+  .nrst( nrst ),
+  .in( start ),
+  .out(  )
+);
+
+
+endmodule