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Konstantin Pavlov 2023-05-22 13:44:20 +03:00
parent 23709d8278
commit 8043f65f2b
1 changed files with 15 additions and 2 deletions
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clogb2.svh
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@ -5,10 +5,23 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// INFO ------------------------------------------------------------------------ // INFO ------------------------------------------------------------------------
// Calculates counter/address width based on specified vector/RAM depth // Calculates counter width based on specified vector/RAM depth
//
// see also: http://www.sunburst-design.com/papers/CummingsHDLCON2001_Verilog2001.pdf // see also: http://www.sunburst-design.com/papers/CummingsHDLCON2001_Verilog2001.pdf
// //
// WARNING:
// ========
// - clogb2() usage is a quite obsolete technique, left from Verilog-2001 era
// when system function $clog2() was not supported or was implemented falcely
//
// - don`t use clogb2() for new designs! Instead:
//
// - use $clog2(DEPTH) when declaring wr_addr[] pointer, which can refer any
// RAM element from 0 to DEPTH-1
//
// - use $clog2(DEPTH+1) to declare counters, which should hold any walue from
// 0 up to the DEPTH (inclusive)
//
//
// Compared with system function $clog2(): // Compared with system function $clog2():
// ======================================= // =======================================
// $clog2(0) = 0; clogb2(0) = 0; // $clog2(0) = 0; clogb2(0) = 0;