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Updated SystemVerilog variants of SR trigger featuring dominant logic state

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Konstantin Pavlov (fm) 2019-01-09 14:28:29 +03:00
parent d39ccb2dd7
commit 842496f0da
2 changed files with 90 additions and 0 deletions
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45
reset_set.sv Normal file
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//--------------------------------------------------------------------------------
// reset_set.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// SR trigger variant
// No metastable state. SET dominates here
/* --- INSTANTIATION TEMPLATE BEGIN ---
reset_set RS1 (
.clk( clk ),
.nrst( 1'b1 ),
.s( ),
.r( ),
.q( ),
.nq( )
);
--- INSTANTIATION TEMPLATE END ---*/
module reset_set(
input wire clk,
input wire nrst,
input wire s,
input wire r,
output reg q = 0, // aka "present state"
output wire nq
);
always_ff @(posedge clk) begin
if (~nrst) begin
q = 0;
end else begin
if r q = 0;
if s q = 1;
end
end
assign nq = ~q;
endmodule

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set_reset.sv Normal file
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//--------------------------------------------------------------------------------
// set_reset.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// SR trigger variant
// No metastable state. RESET dominates here
/* --- INSTANTIATION TEMPLATE BEGIN ---
set_reset SR1 (
.clk( clk ),
.nrst( 1'b1 ),
.s( ),
.r( ),
.q( ),
.nq( )
);
--- INSTANTIATION TEMPLATE END ---*/
module set_reset(
input wire clk,
input wire nrst,
input wire s,
input wire r,
output reg q = 0, // aka "present state"
output wire nq
);
always_ff @(posedge clk) begin
if (~nrst) begin
q = 0;
end else begin
if s q = 1;
if r q = 0;
end
end
assign nq = ~q;
endmodule