mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-14 06:42:54 +08:00
More README fixes
This commit is contained in:
parent
8d569ce7a1
commit
864a6900b9
@ -1,6 +1,6 @@
|
||||
### readme for "benchmark_projects" directory
|
||||
### published as part of https://github.com/pConst/basic_verilog
|
||||
### Konstantin Pavlov, pavlovconst@gmail.com
|
||||
// readme for "benchmark_projects" directory
|
||||
// published as part of https://github.com/pConst/basic_verilog
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
|
||||
|
||||
The directory contains single reference System Verilog codebase, compiled consistently for multiple FPGA platforms and vendors.
|
||||
|
@ -1,6 +1,6 @@
|
||||
### readme for "scripts_for_intel_hls" directory
|
||||
### published as part of https://github.com/pConst/basic_verilog
|
||||
### Konstantin Pavlov, pavlovconst@gmail.com
|
||||
// readme for "scripts_for_intel_hls" directory
|
||||
// published as part of https://github.com/pConst/basic_verilog
|
||||
// Konstantin Pavlov, pavlovconst@gmail.com
|
||||
|
||||
|
||||
The directory contains automation scripts to work with Intel HLS technology on Windows machines.
|
||||
|
Loading…
x
Reference in New Issue
Block a user