1
0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

More README fixes

This commit is contained in:
Konstantin Pavlov 2022-05-16 19:39:38 +03:00
parent 8d569ce7a1
commit 864a6900b9
2 changed files with 6 additions and 6 deletions

View File

@ -1,6 +1,6 @@
### readme for "benchmark_projects" directory
### published as part of https://github.com/pConst/basic_verilog
### Konstantin Pavlov, pavlovconst@gmail.com
// readme for "benchmark_projects" directory
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com
The directory contains single reference System Verilog codebase, compiled consistently for multiple FPGA platforms and vendors.

View File

@ -1,6 +1,6 @@
### readme for "scripts_for_intel_hls" directory
### published as part of https://github.com/pConst/basic_verilog
### Konstantin Pavlov, pavlovconst@gmail.com
// readme for "scripts_for_intel_hls" directory
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com
The directory contains automation scripts to work with Intel HLS technology on Windows machines.