Updated delay module to support LENGTH=0

delay.sv

@@ -1,5 +1,5 @@
 //------------------------------------------------------------------------------
-// delay.sv
+// delay.v
 // Konstantin Pavlov, pavlovconst@gmail.com
 //------------------------------------------------------------------------------
 
@@ -11,6 +11,14 @@
 //
 // Tip for Xilinx-based implementations: Leave nrst=1'b1 and ena=1'b1 on
 // purpose of inferring Xilinx`s SRL16E/SRL32E primitives
+//
+//
+// CAUTION: delay module is widely used for synchronizing signals across clock
+//   domains. To automatically exclude input data paths from timing analisys
+//   set_false_path SDC constraint is integrated into this module. Applicable
+//   only to Intel/Altera Quartus IDE. Xilinx users still should write the
+//   constraints manually
+//
 
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
@@ -39,17 +47,36 @@ module delay #( parameter
   output out
 );
 
+generate
 
-logic [LENGTH-1:0] data = 0;
-always_ff @(posedge clk) begin
-  if (~nrst) begin
-    data[LENGTH-1:0] <= 0;
-  end else if (ena) begin
-    data[LENGTH-1:0] <= {data[LENGTH-2:0],in};
-  end
-end
+  if ( LENGTH == 0 ) begin
+    assign out = in;
+  end else if( LENGTH == 1 ) begin
 
-assign
-    out = data[LENGTH-1];
+    logic data = 0;
+    always_ff @(posedge clk) begin
+      if (~nrst) begin
+        data <= 0;
+      end else if (ena) begin
+        data <= in;
+      end
+    end
+    assign out = data;
+
+  end else begin
+
+    logic [LENGTH:1] data = 0;
+    always_ff @(posedge clk) begin
+      if (~nrst) begin
+        data[LENGTH:1] <= 0;
+      end else if (ena) begin
+        data[LENGTH:1] <= {data[LENGTH-1:1],in};
+      end
+    end
+    assign out = data[LENGTH];
+
+  end // if
+
+endgenerate
 
 endmodule