1
0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

Fixed READMEs

This commit is contained in:
Konstantin Pavlov 2022-05-16 19:29:41 +03:00
parent 66733fa819
commit 8d569ce7a1
2 changed files with 43 additions and 4 deletions

View File

@ -1,11 +1,11 @@
readme for "benchmark_projects" directory
published as part of https://github.com/pConst/basic_verilog
Konstantin Pavlov, pavlovconst@gmail.com
### readme for "benchmark_projects" directory
### published as part of https://github.com/pConst/basic_verilog
### Konstantin Pavlov, pavlovconst@gmail.com
The directory contains single reference System Verilog codebase, compiled consistently for multiple FPGA platforms and vendors.
Supported and committed IDE projects include
Supported IDE projects include
* Xilinx ISE
* Xilinx Vivado
* Intel Quartus

39
scripts_for_intel_hls/README.md Executable file
View File

@ -0,0 +1,39 @@
### readme for "scripts_for_intel_hls" directory
### published as part of https://github.com/pConst/basic_verilog
### Konstantin Pavlov, pavlovconst@gmail.com
The directory contains automation scripts to work with Intel HLS technology on Windows machines.
My setup includes:
* Intel Quartus Prime 18.0 Standard Edition
* Mentor Modelsim Intel edition that comes with Quartus
* Microsoft Visual Studio 10 x64
Don't hesitate meaningless (at the first glance) sctipt names. It is done on purpose to speedup commandline typing.
b.bat is an universal b[uild] script template for HLS components. Place the script at your HLS project directory. You may specify your FPGA target, desired HLS component clock and other options. Run it by typing "b q[Enter]" in terminal window after HLS initialization (see i.bat description below).
There are several options to select build type
* e[mulation] - perform HLS component emulation with standard i++ compiler
* s[imulation] - perform HLS component simulation in Modelsim
* m[svc] - perform HLS component emulation with Visual Studio compiler instead of standard i++
* c[lean] - clean generated files, for example, before committing
* r[eport] - show HLS component report in your browser
* v[sim] - open "vsim.wlf" file in Modelsim
* q[uartus] - perform HLS component compilation in Quartus
build_recursively.bat is a recursive compilation entry-point script in case you have multiple components in your project and you want to compile them all
i.bat - helper script to perform HLS initialization. See instruction comments inside
README.md - this file
test.cpp - common HLS component template to start with