From 90a8836c3d371c933c613a65987013f50341874f Mon Sep 17 00:00:00 2001
From: Konstantin Pavlov <pavlovconst@gmail.com>
Date: Thu, 31 Mar 2022 15:42:11 +0300
Subject: [PATCH] Added clogb2 function

---
 clogb2.svh | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100755 clogb2.svh

diff --git a/clogb2.svh b/clogb2.svh
new file mode 100755
index 0000000..5c7336e
--- /dev/null
+++ b/clogb2.svh
@@ -0,0 +1,24 @@
+//------------------------------------------------------------------------------
+// clogb2.svh
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  Calculates counter/address width based on specified vector/RAM depth
+//
+//  Function should be instantiated inside a module
+//  But you are free to call it from anywhere by its hierarchical name
+//
+//  To add clogb2 function to your module:
+//  `include "clogb2.svh"
+//
+
+function integer clogb2;
+  input integer depth;
+
+  for( clogb2=0; depth>0; clogb2=clogb2+1 ) begin
+    depth = depth >> 1;
+  end
+endfunction
+