Added sample code

example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl

@@ -6,7 +6,7 @@
 # Create a project
 open_project prj -reset
 add_files src/hls_operator.cpp
-add_files -tb src/hls_operator_tb.cpp
+add_files -tb src/hls_operator_tb.cpp -cflags "-Wno-unknown-pragmas" -csimflags "-Wno-unknown-pragmas"
 set_top hls_operator
 
 # Create a solution
@@ -14,6 +14,8 @@ open_solution -reset sol1 -flow_target vitis
 set_part {xcvu9p-flga2104-2-i}
 create_clock -period 5 -name default
 
+#source "./prj/sol1/directives.tcl"
+
 #csim_design
 csynth_design
 #cosim_design

example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp

@@ -6,6 +6,75 @@
 #include "ap_int.h"
 #include "hls_stream.h"
 
+//#include "hls_operator.h"
+
+
+//==================================================================================================
+void stream_splitter(
+  hls::stream<int> &is,
+  hls::stream<int> &os1,
+  hls::stream<int> &os2
+){
+
+//#pragma HLS INLINE
+
+  int data;
+  data = is.read();
+
+  os1.write( data );
+  os2.write( data );
+}
+
+//==================================================================================================
+void func_1(
+  hls::stream<int> &is,
+  hls::stream<int> &os
+){
+
+//#pragma HLS INLINE
+
+  const int st_k = 5;
+
+  os.write( is.read() + st_k );
+}
+
+
+//==================================================================================================
+void func_2(
+  hls::stream<int> &is,
+  hls::stream<int> &os
+){
+
+//#pragma HLS INLINE
+
+  static int st_k;
+
+  os.write( is.read() + st_k );
+
+  if( st_k < 4 ){
+    st_k++;
+  } else {
+    st_k = 0;
+  }
+}
+
+
+//==================================================================================================
+void func_3(
+  hls::stream<int> &is,
+  hls::stream<int> &os
+){
+
+//#pragma HLS INLINE
+
+  //#pragma HLS DATAFLOW disable_start_propagation
+  //#pragma HLS INTERFACE mode=ap_ctrl_none port=return
+
+  os.write( is.read() / 13 );
+}
+
+
+//==================================================================================================
 void hls_operator(
   hls::stream<int> &a,
   hls::stream<int> &b,
@@ -16,12 +85,33 @@ void hls_operator(
   #pragma HLS DATAFLOW disable_start_propagation
   #pragma HLS INTERFACE mode=ap_ctrl_none port=return
 
-  #pragma HLS INTERFACE port=a ap_fifo
+  //#pragma HLS PIPELINE
-  #pragma HLS INTERFACE port=b axis
+
-  #pragma HLS INTERFACE port=c ap_fifo
+  #pragma HLS INTERFACE port=a ap_fifo
-  #pragma HLS INTERFACE port=d axis
+  #pragma HLS INTERFACE port=b ap_fifo
+  #pragma HLS INTERFACE port=c ap_fifo
+  #pragma HLS INTERFACE port=d ap_fifo
+
+
+  hls::stream<int> a1;
+  hls::stream<int> a2;
+  stream_splitter(a, a1, a2);
+
+
+  // first branch (short)
+  hls::stream<int> fa_os;
+  func_1( a1, fa_os );
+
+
+  // second branch (long)
+  hls::stream<int> fb_os;
+  func_2( a2, fb_os );
+
+  hls::stream<int> fc_os;
+  func_3( fb_os, fc_os );
+
+
+  b.write( fa_os.read() + fc_os.read() );
 
-  c.write( a.read() + b.read() );
-  d.write( a.read() - b.read() );
 }
 

example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.h

@@ -0,0 +1,21 @@
+
+void stream_splitter(
+  hls::stream<int> &is,
+  hls::stream<int> &os1
+  hls::stream<int> &os2
+);
+
+void func_1(
+  hls::stream<int> &is,
+  hls::stream<int> &os
+);
+
+void func_2(
+  hls::stream<int> &is,
+  hls::stream<int> &os
+);
+
+void func_3(
+  hls::stream<int> &is,
+  hls::stream<int> &os
+);

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh

@@ -12,11 +12,13 @@
 rm -rf ./prj/sol1/syn
 rm -rf ./prj/sol1/impl
 
-vitis_hls -f run_hls.tcl
+if (vitis_hls -f run_hls.tcl | grep --color -P "ERROR:|") ; then
 
-# open top Verilog
+    # open top Verilog
-subl ./prj/sol1/syn/verilog/hls_operator.v
+    subl ./prj/sol1/syn/verilog/hls_operator.v
 
-# open main report
+    # open main report
-subl ./prj/sol1/syn/report/csynth.rpt
+    subl ./prj/sol1/syn/report/csynth.rpt
+    subl ./prj/sol1/syn/report/hls_operator_csynth.rpt
+fi
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh

@@ -12,5 +12,14 @@ if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 
-vitis_hls -eval 'export_design -flow impl -rtl verilog -format ip_catalog'
+if (vitis_hls -eval 'export_design -flow impl -rtl verilog -format ip_catalog' | grep --color -P "ERROR:|") ; then
+
+    # open top Verilog
+    subl ./prj/sol1/syn/verilog/hls_operator.v
+
+    # open main report
+    subl ./prj/sol1/impl/report/verilog/hls_operator_export.rpt
+    subl ./prj/sol1/impl/report/verilog/export_syn.rpt
+    subl ./prj/sol1/impl/report/verilog/export_impl.rpt
+fi
 

example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh

@@ -12,5 +12,13 @@ if [ ! -d "./prj" ]; then
   source vitis_hls_csynth.sh
 fi
 
-vitis_hls -eval 'export_design -flow syn -rtl verilog -format ip_catalog'
+if (vitis_hls -eval 'export_design -flow syn -rtl verilog -format ip_catalog' | grep --color -P "ERROR:|") ; then
+
+    # open top Verilog
+    subl ./prj/sol1/syn/verilog/hls_operator.v
+
+    # open main report
+    subl ./prj/sol1/impl/report/verilog/hls_operator_export.rpt
+    subl ./prj/sol1/impl/report/verilog/export_syn.rpt
+fi