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Added fifo initialization
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Konstantin Pavlov
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68b33a10d4
commit
98040673a3
@ -1,11 +1,16 @@
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//------------------------------------------------------------------------------
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// fifo_single_clock_reg_v1.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Single-clock FIFO buffer implementation, also known as "queue"
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//
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// I`ve made two variants of fifo_single_clock_reg module - v1 and v2
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// Both variants are valid, both operate identically from an outside observer`s
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// view. Only internal r/w pointers operation is different.
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//
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// Features:
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// - single clock operation
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// - configurable depth and data width
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@ -14,6 +19,7 @@
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// - simultaneous read and write operations supported if not full and not empty
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// - only read operation is performed when (full && r_req && w_req)
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// - only write operation is performed when (empty && r_req && w_req)
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// - (new!) optional fifo contents initialization
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//
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// See also "lifo.sv" module for similar LIFO buffer implementation
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@ -23,7 +29,11 @@
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fifo_single_clock_reg_v1 #(
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.FWFT_MODE( "TRUE" ),
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.DEPTH( 8 ),
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.DATA_W( 32 )
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.DATA_W( 32 ),
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// optional initialization
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.INIT_FILE( "fifo_single_clock_reg_v1_init.svh" ),
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.INIT_CNT( 10 )
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) FF1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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@ -45,16 +55,19 @@ module fifo_single_clock_reg_v1 #( parameter
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FWFT_MODE = "TRUE", // "TRUE" - first word fall-trrough" mode
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// "FALSE" - normal fifo mode
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DEPTH = 8, // max elements count == DEPTH, DEPTH MUST be power of 2
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DEPTH_W = $clog2(DEPTH)+1, // elements counter width, extra bit to store
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DEPTH_W = clogb2(DEPTH)+1, // elements counter width, extra bit to store
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// "fifo full" state, see cnt[] variable comments
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DATA_W = 32 // data field width
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)(
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DATA_W = 32, // data field width
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// optional initialization
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USE_INIT_FILE = "FALSE", // "TRUE" - uses special filethat provides init data
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// "FALSE" - initializes with '0
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INIT_CNT = '0 // sets desired initial cnt[]
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)(
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input clk,
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input nrst, // inverted reset
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input nrst, // inverted reset
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// input port
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input w_req,
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@ -65,86 +78,108 @@ module fifo_single_clock_reg_v1 #( parameter
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output logic [DATA_W-1:0] r_data,
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// helper ports
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output logic [DEPTH_W-1:0] cnt = '0,
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output logic [DEPTH_W-1:0] cnt,
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output logic empty,
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output logic full,
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output logic fail
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);
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// fifo data
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logic [DEPTH-1:0][DATA_W-1:0] data = '0;
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// fifo data
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logic [DEPTH-1:0][DATA_W-1:0] data;
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// data output buffer for normal fifo mode
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logic [DATA_W-1:0] data_buf = '0;
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// cnt[] vector always holds fifo elements count
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// data[cnt[]] points to the first empty fifo slot
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// when fifo is full data[cnt[]] points "outside" of data[]
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// filtered requests
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logic w_req_f;
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assign w_req_f = w_req && ~full;
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logic r_req_f;
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assign r_req_f = r_req && ~empty;
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integer i;
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always_ff @(posedge clk) begin
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if ( ~nrst ) begin
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data <= '0;
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cnt[DEPTH_W-1:0] <= '0;
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data_buf[DATA_W-1:0] <= '0;
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end else begin
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unique case ({w_req_f, r_req_f})
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2'b00: ; // nothing
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2'b01: begin // reading out
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for ( i = (DEPTH-1); i > 0; i-- ) begin
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data[i-1] <= data[i];
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end
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cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] - 1'b1;
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// fofo initialization
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// Modelsim gives suppressable error here
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// "(vlog-7061) Variable 'data' driven in an always_ff block, may not be driven by any other process"
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generate
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initial begin
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if( USE_INIT_FILE ) begin
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`include "fifo_single_clock_reg_v1_init.svh"
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cnt[DEPTH_W-1:0] <= INIT_CNT[DEPTH_W-1:0];
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end else begin
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data <= '0;
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cnt[DEPTH_W-1:0] <= '0;
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end
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end // initial
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endgenerate
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2'b10: begin // writing in
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data[cnt[DEPTH_W-1:0]] <= w_data[DATA_W-1:0];
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cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] + 1'b1;
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// data output buffer for normal fifo mode
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logic [DATA_W-1:0] data_buf = '0;
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// cnt[] vector always holds fifo elements count
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// data[cnt[]] points to the first empty fifo slot
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// when fifo is full data[cnt[]] points "outside" of data[]
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// filtered requests
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logic w_req_f;
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assign w_req_f = w_req && ~full;
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logic r_req_f;
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assign r_req_f = r_req && ~empty;
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always_ff @(posedge clk) begin
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integer i;
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if ( ~nrst ) begin
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if( USE_INIT_FILE ) begin
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`include "fifo_single_clock_reg_v1_init.svh"
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cnt[DEPTH_W-1:0] <= INIT_CNT[DEPTH_W-1:0];
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end else begin
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data <= '0;
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cnt[DEPTH_W-1:0] <= '0;
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end
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2'b11: begin // simultaneously reading and writing
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for ( i = (DEPTH-1); i > 0; i-- ) begin
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data[i-1] <= data[i];
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end
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data[cnt[DEPTH_W-1:0]-1] <= w_data[DATA_W-1:0];
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// data counter does not change here
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end
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endcase
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// data buffer works only for normal fifo mode
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if( r_req_f ) begin
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data_buf[DATA_W-1:0] <= data[0];
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end
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end
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end
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always_comb begin
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empty = ( cnt[DEPTH_W-1:0] == '0 );
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full = ( cnt[DEPTH_W-1:0] == DEPTH );
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if( FWFT_MODE == "TRUE" ) begin
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if (~empty) begin
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r_data[DATA_W-1:0] = data[0]; // first-word fall-through mode
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data_buf[DATA_W-1:0] <= '0;
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end else begin
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r_data[DATA_W-1:0] = '0;
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unique case ({w_req_f, r_req_f})
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2'b00: ; // nothing
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2'b01: begin // reading out
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for ( i = (DEPTH-1); i > 0; i=i-1 ) begin
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data[i-1] <= data[i];
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end
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cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] - 1'b1;
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end
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2'b10: begin // writing in
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data[cnt[DEPTH_W-1:0]] <= w_data[DATA_W-1:0];
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cnt[DEPTH_W-1:0] <= cnt[DEPTH_W-1:0] + 1'b1;
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end
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2'b11: begin // simultaneously reading and writing
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for ( i = (DEPTH-1); i > 0; i=i-1 ) begin
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data[i-1] <= data[i];
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end
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data[cnt[DEPTH_W-1:0]-1] <= w_data[DATA_W-1:0];
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// data counter does not change here
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end
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endcase
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// data buffer works only for normal fifo mode
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if( r_req_f ) begin
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data_buf[DATA_W-1:0] <= data[0];
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end
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end
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end else begin
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r_data[DATA_W-1:0] = data_buf[DATA_W-1:0]; // normal mode
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end
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fail = ( empty && r_req ) ||
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( full && w_req );
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end
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always_comb begin
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empty = ( cnt[DEPTH_W-1:0] == '0 );
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full = ( cnt[DEPTH_W-1:0] == DEPTH );
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if( FWFT_MODE == "TRUE" ) begin
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if( ~empty ) begin
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r_data[DATA_W-1:0] = data[0]; // first-word fall-through mode
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end else begin
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r_data[DATA_W-1:0] = '0;
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end
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end else begin
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r_data[DATA_W-1:0] = data_buf[DATA_W-1:0]; // normal mode
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end
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fail = ( empty && r_req ) ||
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( full && w_req );
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end
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`include "clogb2.svh"
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endmodule
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43
fifo_single_clock_reg_v1_init.svh
Executable file
43
fifo_single_clock_reg_v1_init.svh
Executable file
@ -0,0 +1,43 @@
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//------------------------------------------------------------------------------
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// fifo_single_clock_reg_v1_init.svh
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Initialization statements example for fifo_single_clock_reg_v1 fifo
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//
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data[0] <= 32'hAAAA;
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data[1] <= 32'h0001;
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data[2] <= 32'h0002;
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data[3] <= 32'h0003;
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data[4] <= 32'h0004;
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data[5] <= 32'h0005;
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data[6] <= 32'h0006;
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data[7] <= 32'h0007;
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data[8] <= 32'hBBBB;
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data[9] <= 32'h0001;
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data[10] <= 32'h0002;
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data[11] <= 32'h0003;
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data[12] <= 32'h0004;
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data[13] <= 32'h0005;
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data[14] <= 32'h0006;
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data[15] <= 32'h0007;
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data[16] <= 32'hCCCC;
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data[17] <= 32'h0001;
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data[18] <= 32'h0002;
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data[19] <= 32'h0003;
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data[20] <= 32'h0004;
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data[21] <= 32'h0005;
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data[22] <= 32'h0006;
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data[23] <= 32'h0007;
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data[24] <= 32'hDDDD;
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data[25] <= 32'h0001;
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data[26] <= 32'h0002;
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data[27] <= 32'h0003;
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data[28] <= 32'h0004;
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data[29] <= 32'h0005;
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data[30] <= 32'h0006;
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data[31] <= 32'h0007;
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@ -94,11 +94,14 @@ end
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//`define TEST_FWFT yes
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// comment or uncomment to sweep-test or random test
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//`define TEST_SWEEP yes
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`define TEST_SWEEP yes
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// comment or uncomment to use bare scfifo or quartus wizard-generated wrappers
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//`define BARE_SCFIFO yes
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// initialization is not supported for Altera fifo
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`define TEST_INIT yes
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logic full1, empty1;
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logic full1_d1, empty1_d1;
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@ -131,10 +134,20 @@ fifo_single_clock_reg_v1 #(
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.FWFT_MODE( "FALSE" ),
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`endif
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.DEPTH( 8 ),
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.DATA_W( 16 )
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.DATA_W( 16 ),
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`ifdef TEST_INIT
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// optional initialization
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.USE_INIT_FILE( "TRUE" ),
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.INIT_CNT( 10 )
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`endif
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) FF1 (
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.clk( clk200 ),
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`ifdef TEST_INIT
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.nrst( 1'b1 ),
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`else
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.nrst( nrst_once ),
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`endif
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`ifdef TEST_SWEEP
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.w_req( ~direction1 && &RandomNumber1[10] ),
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