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Added 8b10b encoder/decoder
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Konstantin Pavlov
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274
encdec_8b10b.v
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274
encdec_8b10b.v
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// Chuck Benz, Hollis, NH Copyright (c)2002
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//
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// The information and description contained herein is the
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// property of Chuck Benz.
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//
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// Permission is granted for any reuse of this information
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// and description as long as this copyright notice is
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// preserved. Modifications may be made as long as this
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// notice is preserved.
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// per Widmer and Franaszek
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module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err);
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input [9:0] datain;
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input dispin;
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output [8:0] dataout;
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output dispout;
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output code_err;
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output disp_err;
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wire ai = datain[0];
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wire bi = datain[1];
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wire ci = datain[2];
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wire di = datain[3];
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wire ei = datain[4];
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wire ii = datain[5];
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wire fi = datain[6];
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wire gi = datain[7];
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wire hi = datain[8];
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wire ji = datain[9];
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wire aeqb = (ai & bi) | (!ai & !bi);
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wire ceqd = (ci & di) | (!ci & !di);
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wire p22 = (ai & bi & !ci & !di) |
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(ci & di & !ai & !bi) |
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( !aeqb & !ceqd);
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wire p13 = ( !aeqb & !ci & !di) |
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( !ceqd & !ai & !bi);
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wire p31 = ( !aeqb & ci & di) |
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( !ceqd & ai & bi);
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wire p40 = ai & bi & ci & di;
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wire p04 = !ai & !bi & !ci & !di;
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wire disp6a = p31 | (p22 & dispin); // pos disp if p22 and was pos, or p31.
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wire disp6a2 = p31 & dispin; // disp is ++ after 4 bits
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wire disp6a0 = p13 & ! dispin; // -- disp after 4 bits
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wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 |
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(ei & ii & di)) & (ei | ii | di));
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// The 5B/6B decoding special cases where ABCDE != abcde
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wire p22bceeqi = p22 & bi & ci & (ei == ii);
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wire p22bncneeqi = p22 & !bi & !ci & (ei == ii);
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wire p13in = p13 & !ii;
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wire p31i = p31 & ii;
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wire p13dei = p13 & di & ei & ii;
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wire p22aceeqi = p22 & ai & ci & (ei == ii);
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wire p22ancneeqi = p22 & !ai & !ci & (ei == ii);
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wire p13en = p13 & !ei;
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wire anbnenin = !ai & !bi & !ei & !ii;
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wire abei = ai & bi & ei & ii;
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wire cdei = ci & di & ei & ii;
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wire cndnenin = !ci & !di & !ei & !ii;
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// non-zero disparity cases:
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wire p22enin = p22 & !ei & !ii;
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wire p22ei = p22 & ei & ii;
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//wire p13in = p12 & !ii;
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//wire p31i = p31 & ii;
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wire p31dnenin = p31 & !di & !ei & !ii;
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//wire p13dei = p13 & di & ei & ii;
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wire p31e = p31 & ei;
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wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi |
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p13en | abei | cndnenin;
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wire compb = p22bceeqi | p31i | p13dei | p22aceeqi |
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p13en | abei | cndnenin;
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wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi |
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p13en | anbnenin | cndnenin;
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wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi |
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p13en | abei | cndnenin;
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wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi |
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p13en | anbnenin | cndnenin;
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wire ao = ai ^ compa;
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wire bo = bi ^ compb;
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wire co = ci ^ compc;
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wire do_ = di ^ compd;
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wire eo = ei ^ compe;
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wire feqg = (fi & gi) | (!fi & !gi);
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wire heqj = (hi & ji) | (!hi & !ji);
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wire fghj22 = (fi & gi & !hi & !ji) |
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(!fi & !gi & hi & ji) |
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( !feqg & !heqj);
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wire fghjp13 = ( !feqg & !hi & !ji) |
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( !heqj & !fi & !gi);
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wire fghjp31 = ( (!feqg) & hi & ji) |
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( !heqj & fi & gi);
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wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji);
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wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) |
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(p13 & !ei & ii & gi & hi & ji) |
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(p31 & ei & !ii & !gi & !hi & !ji));
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wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1
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((dispin & ci & di & !ei & !ii) | ko |
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(dispin & !ci & di & !ei & !ii))) |
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(!fi & gi & hi & // 0111 cases, where disp6b is 0
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(( !dispin & !ci & !di & ei & ii) | ko |
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( !dispin & ci & !di & ei & ii)));
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wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii);
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// k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
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wire k28p = ! (ci | di | ei | ii);
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wire fo = (ji & !fi & (hi | !gi | k28p)) |
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(fi & !ji & (!hi | gi | !k28p)) |
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(k28p & gi & hi) |
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(!k28p & !gi & !hi);
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wire go = (ji & !fi & (hi | !gi | !k28p)) |
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(fi & !ji & (!hi | gi |k28p)) |
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(!k28p & gi & hi) |
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(k28p & !gi & !hi);
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wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) |
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(fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) |
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(!fi & gi & hi & ji) | (fi & !gi & !hi & !ji);
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wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii);
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wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii);
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wire disp4p = fghjp31;
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wire disp4n = fghjp13;
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assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) |
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(p13 & !ei & !ii) | (p31 & ei & ii) |
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(ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) |
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(ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) |
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(!p31 & ei & !ii & !gi & !hi & !ji) |
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(!p13 & !ei & ii & gi & hi & ji) |
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(((ei & ii & !gi & !hi & !ji) |
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(!ei & !ii & gi & hi & ji)) &
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! ((ci & di & ei) | (!ci & !di & !ei))) |
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(disp6p & disp4p) | (disp6n & disp4n) |
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(ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) |
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(!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) |
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(fi & gi & !hi & !ji & disp6p) |
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(!fi & !gi & hi & ji & disp6n) |
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(ci & di & ei & ii & !fi & !gi & !hi) |
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(!ci & !di & !ei & !ii & fi & gi & hi);
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assign dataout = {ko, ho, go, fo, eo, do_, co, bo, ao};
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// my disp err fires for any legal codes that violate disparity, may fire for illegal codes
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assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) |
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(dispin & !disp6n & fi & gi) |
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(dispin & ai & bi & ci) |
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(dispin & !disp6n & disp4p) |
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(!dispin & !disp6p & !fi & !gi) |
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(!dispin & !ai & !bi & !ci) |
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(!dispin & !disp6p & disp4n) |
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(disp6p & disp4p) | (disp6n & disp4n));
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endmodule
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module encode_8b10b (datain, dispin, dataout, dispout);
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input [8:0] datain;
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input dispin; // 0 = neg disp; 1 = pos disp
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output [9:0] dataout;
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output dispout;
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wire ai = datain[0];
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wire bi = datain[1];
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wire ci = datain[2];
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wire di = datain[3];
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wire ei = datain[4];
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wire fi = datain[5];
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wire gi = datain[6];
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wire hi = datain[7];
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wire ki = datain[8];
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wire aeqb = (ai & bi) | (!ai & !bi);
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wire ceqd = (ci & di) | (!ci & !di);
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wire l22 = (ai & bi & !ci & !di) |
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(ci & di & !ai & !bi) |
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( !aeqb & !ceqd);
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wire l40 = ai & bi & ci & di;
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wire l04 = !ai & !bi & !ci & !di;
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wire l13 = ( !aeqb & !ci & !di) |
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( !ceqd & !ai & !bi);
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wire l31 = ( !aeqb & ci & di) |
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( !ceqd & ai & bi);
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// The 5B/6B encoding
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wire ao = ai;
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wire bo = (bi & !l40) | l04;
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wire co = l04 | ci | (ei & di & !ci & !bi & !ai);
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wire do_ = di & ! (ai & bi & ci);
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wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai);
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wire io = (l22 & !ei) |
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(ei & !di & !ci & !(ai&bi)) | // D16, D17, D18
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(ei & l40) |
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(ki & ei & di & ci & !bi & !ai) | // K.28
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(ei & !di & ci & !bi & !ai);
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// pds16 indicates cases where d-1 is assumed + to get our encoded value
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wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31);
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// nds16 indicates cases where d-1 is assumed - to get our encoded value
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wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai);
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// ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
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wire ndos6 = pd1s6;
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// pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
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wire pdos6 = ki | (ei & !l22 & !l13);
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// some Dx.7 and all Kx.7 cases result in run length of 5 case unless
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// an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
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// specifically, D11, D13, D14, D17, D18, D19.
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wire alt7 = fi & gi & hi & (ki |
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(dispin ? (!ei & di & l31) : (ei & !di & l13)));
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wire fo = fi & ! alt7;
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wire go = gi | (!fi & !gi & !hi);
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wire ho = hi;
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wire jo = (!hi & (gi ^ fi)) | alt7;
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// nd1s4 is cases where d-1 is assumed - to get our encoded value
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wire nd1s4 = fi & gi;
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// pd1s4 is cases where d-1 is assumed + to get our encoded value
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wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi)));
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// ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
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wire ndos4 = (!fi & !gi);
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// pdos4 is nd1s4 cases where d-1 is - yields + disp out
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wire pdos4 = fi & gi & hi;
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// only legal K codes are K28.0->.7, K23/27/29/30.7
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// K28.0->7 is ei=di=ci=1,bi=ai=0
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// K23 is 10111
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// K27 is 11011
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// K29 is 11101
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// K30 is 11110 - so K23/27/29/30 are ei & l31
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wire illegalk = ki &
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(ai | bi | !ci | !di | !ei) & // not K28.0->7
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(!fi | !gi | !hi | !ei | !l31); // not K23/27/29/30.7
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// now determine whether to do the complementing
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// complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
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wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin);
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// disparity out of 5b6b is disp in with pdso6 and ndso6
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// pds16 indicates cases where d-1 is assumed + to get our encoded value
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// ndos6 is cases where d-1 is + yields - disp out
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// nds16 indicates cases where d-1 is assumed - to get our encoded value
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// pdos6 is cases where d-1 is - yields + disp out
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// disp toggles in all ndis16 cases, and all but that 1 nds16 case
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wire disp6 = dispin ^ (ndos6 | pdos6);
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wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6);
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assign dispout = disp6 ^ (ndos4 | pdos4);
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assign dataout = {(jo ^ compls4), (ho ^ compls4),
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(go ^ compls4), (fo ^ compls4),
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(io ^ compls6), (eo ^ compls6),
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(do_ ^ compls6), (co ^ compls6),
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(bo ^ compls6), (ao ^ compls6)};
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endmodule
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