FPGA/basic_verilog
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Minor code style update

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This commit is contained in:
Konstantin Pavlov 2021-01-26 15:24:09 +03:00
parent cf3b4f5d20
commit b4b191c26f
2 changed files with 5 additions and 5 deletions
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4
uart_tx_rx_shifter_tb.sv
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@ -101,10 +101,10 @@ logic serial_data;
logic start;
// continious transfer (no automatic data check implemented)
//assign start = 1'b1;
assign start = 1'b1;
// random transfer (features automatic data check)
assign start = ~tx_busy && &RandomNumber1[11:8];
//assign start = ~tx_busy && &RandomNumber1[11:8];
uart_tx_shifter #(
.START_BITS( `STB ),

6
uart_tx_shifter.sv
View File

@ -77,7 +77,7 @@ always_ff @(posedge clk) begin
if( tx_start ) begin
// buffering input data
tx_data_buf[DATA_BITS-1:0] <= tx_data[DATA_BITS-1:0];
state_cntr[7:0] <= START_BITS-1;
state_cntr[7:0] <= START_BITS - 1'b1;
tx_state <= tx_state.next();
end // tx_start
end // state_cntr
@ -91,7 +91,7 @@ always_ff @(posedge clk) begin
state_cntr[7:0]--;
end else begin
// transition
state_cntr[7:0] <= DATA_BITS-1;
state_cntr[7:0] <= DATA_BITS - 1'b1;
tx_state <= tx_state.next();
end // state_cntr
@ -105,7 +105,7 @@ always_ff @(posedge clk) begin
state_cntr[7:0]--;
end else begin
// transition
state_cntr[7:0] <= STOP_BITS-1;
state_cntr[7:0] <= STOP_BITS - 1'b1;
tx_state <= tx_state.next();
end // state_cntr