From b4b191c26f7717b6771ea8782221e0e58e1a8e34 Mon Sep 17 00:00:00 2001
From: Konstantin Pavlov <pavlovconst@gmail.com>
Date: Tue, 26 Jan 2021 15:24:09 +0300
Subject: [PATCH] Minor code style update

---
 uart_tx_rx_shifter_tb.sv | 4 ++--
 uart_tx_shifter.sv       | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/uart_tx_rx_shifter_tb.sv b/uart_tx_rx_shifter_tb.sv
index c0aa44e..99193ff 100644
--- a/uart_tx_rx_shifter_tb.sv
+++ b/uart_tx_rx_shifter_tb.sv
@@ -101,10 +101,10 @@ logic serial_data;
 logic start;
 
 // continious transfer (no automatic data check implemented)
-//assign start = 1'b1;
+assign start = 1'b1;
 
 // random transfer (features automatic data check)
-assign start = ~tx_busy && &RandomNumber1[11:8];
+//assign start = ~tx_busy && &RandomNumber1[11:8];
 
 uart_tx_shifter #(
   .START_BITS( `STB ),
diff --git a/uart_tx_shifter.sv b/uart_tx_shifter.sv
index 05f0198..595d20a 100644
--- a/uart_tx_shifter.sv
+++ b/uart_tx_shifter.sv
@@ -77,7 +77,7 @@ always_ff @(posedge clk) begin
             if( tx_start ) begin
               // buffering input data
               tx_data_buf[DATA_BITS-1:0] <= tx_data[DATA_BITS-1:0];
-              state_cntr[7:0] <= START_BITS-1;
+              state_cntr[7:0] <= START_BITS - 1'b1;
               tx_state <= tx_state.next();
             end // tx_start
           end // state_cntr
@@ -91,7 +91,7 @@ always_ff @(posedge clk) begin
             state_cntr[7:0]--;
           end else begin
             // transition
-            state_cntr[7:0] <= DATA_BITS-1;
+            state_cntr[7:0] <= DATA_BITS - 1'b1;
             tx_state <= tx_state.next();
           end // state_cntr
 
@@ -105,7 +105,7 @@ always_ff @(posedge clk) begin
             state_cntr[7:0]--;
           end else begin
             // transition
-            state_cntr[7:0] <= STOP_BITS-1;
+            state_cntr[7:0] <= STOP_BITS - 1'b1;
             tx_state <= tx_state.next();
           end // state_cntr