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Updated delay module. Added block RAM implementation
This commit is contained in:
Konstantin Pavlov
parent
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commit
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122
delay.sv
122
delay.sv
@ -4,7 +4,7 @@
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//------------------------------------------------------------------------------
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// INFO -------------------------------------------------------------------------
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// Static Delay for arbitrary signal
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// Static Delay for arbitrary signal, v2
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// Another equivalent names for this module:
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// conveyor.sv
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// synchronizer.sv
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@ -14,21 +14,26 @@
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//
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//
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// CAUTION: delay module is widely used for synchronizing signals across clock
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// domains. To automatically exclude input data paths from timing analisys
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// set_false_path SDC constraint is integrated into this module. Applicable
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// only to Intel/Altera Quartus IDE. Xilinx users still should write the
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// constraints manually
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// domains. When synchronizing, please exclude input data paths from timing
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// analisys manually by writing appropriate set_false_path SDC constraint
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//
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// Version 2 introduces "ALTERA_BLOCK_RAM" option to implement delays using
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// block RAM. Quartus can make shifters on block RAM aautomatically
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// using 'altshift_taps' internal module when "Auto Shift Register
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// Replacement" option is ON
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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delay #(
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.LENGTH( 2 )
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.LENGTH( 2 ),
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.WIDTH( 1 ),
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.TYPE( "CELLS" )
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) S1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.ena( 1'b1 ),
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.in( ),
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.out( )
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);
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@ -37,45 +42,110 @@ delay #(
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module delay #( parameter
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LENGTH = 2 // delay/synchronizer chain length
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// default length for synchronizer chain is 2
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LENGTH = 2, // delay/synchronizer chain length
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WIDTH = 1, // signal width
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TYPE = "CELLS", // "ALTERA_BLOCK_RAM" infers block ram fifo
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// all other values infer registers
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CNTR_W = $clog2(LENGTH)
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)(
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input clk,
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input nrst,
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input ena,
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input in,
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output out
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input [WIDTH-1:0] in,
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output [WIDTH-1:0] out
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);
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generate
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if ( LENGTH == 0 ) begin
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assign out = in;
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assign out[WIDTH-1:0] = in[WIDTH-1:0];
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end else if( LENGTH == 1 ) begin
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logic data = 0;
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logic [WIDTH-1:0] data = '0;
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always_ff @(posedge clk) begin
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if (~nrst) begin
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data <= 0;
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end else if (ena) begin
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data <= in;
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if( ~nrst ) begin
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data[WIDTH-1:0] <= '0;
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end else if( ena ) begin
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data[WIDTH-1:0] <= in[WIDTH-1:0];
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end
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end
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assign out = data;
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assign out[WIDTH-1:0] = data[WIDTH-1:0];
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end else begin
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if( TYPE=="ALTERA_BLOCK_RAM" && LENGTH>=4 ) begin
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logic [LENGTH:1] data = 0;
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always_ff @(posedge clk) begin
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if (~nrst) begin
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data[LENGTH:1] <= 0;
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end else if (ena) begin
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data[LENGTH:1] <= {data[LENGTH-1:1],in};
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logic [CNTR_W-1:0] delay_cntr = '0;
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logic fifo_output_ena;
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assign fifo_output_ena = (delay_cntr[CNTR_W-1:0] == LENGTH);
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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delay_cntr[CNTR_W-1:0] <= '0;
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end else begin
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if( ena && ~fifo_output_ena) begin
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delay_cntr[CNTR_W-1:0] <= delay_cntr[CNTR_W-1:0] + 1'b1;
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end
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end
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end
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end
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assign out = data[LENGTH];
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end // if
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logic [WIDTH-1:0] fifo_out;
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scfifo #(
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.LPM_WIDTH( WIDTH ),
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.LPM_NUMWORDS( LENGTH ), // must be at least 4
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.LPM_WIDTHU( CNTR_W ),
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.LPM_SHOWAHEAD( "ON" ),
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.UNDERFLOW_CHECKING( "ON" ),
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.OVERFLOW_CHECKING( "ON" ),
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.ALMOST_FULL_VALUE( 0 ),
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.ALMOST_EMPTY_VALUE( 0 ),
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.ENABLE_ECC( "FALSE" ),
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.ALLOW_RWCYCLE_WHEN_FULL( "ON" ),
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.USE_EAB( "ON" ),
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.MAXIMIZE_SPEED( 5 ),
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.DEVICE_FAMILY( "Cyclone V" )
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) internal_fifo (
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.clock( clk ),
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.aclr( 1'b0 ),
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.sclr( ~nrst ),
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.data( in[WIDTH-1:0] ),
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.wrreq( ena ),
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.rdreq( ena && fifo_output_ena ),
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.q( fifo_out[WIDTH-1:0] ),
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.empty( ),
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.full( ),
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.almost_full( ),
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.almost_empty( ),
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.usedw( ),
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.eccstatus( )
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);
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assign out[WIDTH-1:0] = (fifo_output_ena)?(fifo_out[WIDTH-1:0]):('0);
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end else begin
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logic [LENGTH:1][WIDTH-1:0] data = '0;
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always_ff @(posedge clk) begin
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integer i;
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if( ~nrst ) begin
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data <= '0;
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end else if( ena ) begin
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for(i=LENGTH-1; i>0; i--) begin
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data[i+1][WIDTH-1:0] <= data[i][WIDTH-1:0];
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end
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data[1][WIDTH-1:0] <= in[WIDTH-1:0];
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end
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end
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assign out[WIDTH-1:0] = data[LENGTH][WIDTH-1:0];
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end // if TYPE
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end // if LENGTH
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endgenerate
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120
delay_tb.sv
Normal file
120
delay_tb.sv
Normal file
@ -0,0 +1,120 @@
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//------------------------------------------------------------------------------
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// delay_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for delay_tb.sv module
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`timescale 1ns / 1ps
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module delay_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b1;
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forever
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#2.5 clk200 = ~clk200;
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end
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logic clk400;
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initial begin
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#0 clk400 = 1'b1;
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forever
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#1.25 clk400 = ~clk400;
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end
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logic clk33;
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initial begin
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#0 clk33 = 1'b1;
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forever
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#15.151 clk33 = ~clk33;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [31:0] RandomNumber1;
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c_rand rng1 (
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.clk( clk200 ),
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.rst( 1'b0 ),
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.reseed( rst_once ),
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.seed_val( DerivedClocks[31:0] ^ (DerivedClocks[31:0] << 1) ),
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.out( RandomNumber1[15:0] )
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);
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c_rand rng2 (
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.clk( clk200 ),
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.rst( 1'b0 ),
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.reseed( rst_once ),
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.seed_val( DerivedClocks[31:0] ^ (DerivedClocks[31:0] << 2) ),
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.out( RandomNumber1[31:16] )
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);
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// Module under test ==========================================================
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delay #(
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.LENGTH( 10 ),
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.WIDTH( 8 )
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//.TYPE( "CELLS" )
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) d1 (
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.clk( clk200 ),
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.nrst( ~E_DerivedClocks[8] ),
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.ena( 1'b1 ),
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.in( RandomNumber1[7:0] ),
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.out( )
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);
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delay #(
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.LENGTH( 10 ),
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.WIDTH( 8 ),
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.TYPE( "ALTERA_BLOCK_RAM" )
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) d2 (
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.clk( clk200 ),
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.nrst( ~E_DerivedClocks[8] ),
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.ena( 1'b1 ),
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.in( RandomNumber1[7:0] ),
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.out( )
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);
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endmodule
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